Abstract: A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

Abstract: A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillation frequency of the FIFO control ring may be increased to accommodate higher-speed chips, while maintaining synchronization of clock pulses at each stage of the FIFO control ring.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: A method and apparatus for generating multiple frequency clock signals using a single input clock signal are provided. Each clock signal generated has a cycle time that is an integer multiple of the input clock cycle time. The fastest clock signal, i.e., the clock signal with the highest frequency generated has the same cycle time as the input clock. The rising edges of all the clock signals generated are synchronized and each clock signal generated has an approximate duty cycle of 50%. This is achieved by first applying the input clock signal to an input terminal of a plurality of registers and of a frequency control module of the signal generator, presenting control signals to input terminals of the registers and of the frequency control module, and generating a plurality of output clock signals in the frequency control module, dependent on the input clock signal and on the control signals.

Abstract: A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal.

Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.

Abstract: The invention provides a clock distribution circuit which can be applied readily also to a chip (semiconductor integrated circuit) of the building block type and can realize reduction in skew. The clock distribution circuit includes a first buffer disposed at a central location of the chip for receiving an output of an input driver, four second buffers individually disposed at central locations of four sides of the chip for receiving an output of the first buffer, a plurality of third buffers for receiving outputs of the second buffers, and a last stage connection wiring line system for connecting all of outputs of the third buffers commonly to extract a clock signal to be supplied to clock terminals. The third buffers are disposed on linear lines parallel to the two upper and lower sides of the chip, and the outputs of the third buffers are connected to each other by linear wiring lines.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A clock distribution circuit reliably reduces clock skew, while preventing the waveform of a clock signal from rounding, which would otherwise occur due to an increase in resistance, and preventing instability of the clock signal, which would otherwise occur due to an increase in inductance, thereby realizing ideal clock distribution. In the clock distribution circuit, a clock wiring pattern for distributing the clock signal is formed on a chip, and a wiring pattern whose resistance is lower than the clock wiring pattern is formed on a substrate, on which the chip is mounted, in such a way as to be connected to the clock wiring pattern at a plurality of locations. The clock distribution circuit is applied to semiconductor integrated circuits such as LSIs built in multichip modules.

Abstract: A programmable clock circuit generates a plurality of phase clock signals in correspondence with an associated control word programmed into a memory. Programmable clock circuit is implemented digitally in an application specific integrated circuit. Each phase clock signal is synchronized by a master clock signal which reduces signal jitter and improves phase signal accuracy.

Abstract: A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal.

Abstract: A clock signal generator having a pre-phase converter for generating in response to an input clock signal a plurality of pre-delay clock signals with different phases; and main phase converters each of which receives one of the pre-delay clock signals, and generates a plurality of main delay clock signals with their phases different from each other, thereby generating multiple main delay clock signals with their phases different from each other.

Abstract: A system for synchronizing circuit operation within an integrated circuit having a high frequency clock. The system includes an oscillator for providing a clock signal and a transmission line coupled to the oscillator for distributing the clock signal to load buffers. The load buffers provide sub-circuits within the integrated circuit with synchronized clock signals. The load buffers are resonant and convert the capacitive load impedance of receiving circuits into a virtual inductive load. The impedance converter boosts the clock signal transition times to provide improved high frequency circuit synchronization within the integrated circuit.

Abstract: A multiple chip self-aligning clock distribution system. The clock signal provided to any given chip is delayed by the on-chip distribution time of every other chip with which it is to be synchronized. Equal delay paths are added to each chip which provide a delay equal to the clock distribution delay of the chip. The equal delay paths can comprise a series of logic gates, such as for example inverters. The clock distribution delay of the equal delay path is designed to be equal to the clock distribution delay of the clock distribution tree on the chip. For each chip to be synchronized, the clock signal is routed through an equal delay path on each of the other chips to be synchronized before being coupled to the clock distribution input terminal of the destination chip. The number of equal delay paths that is included on each chip is a function of the number of chips to be synchronized. "N" equal delay paths are used where the number of chips is greater than 2.sup.N-1 and is less than or equal to 2.sup.N.

Abstract: There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.

Abstract: A method for increasing a working speed in a synchronous digital system, which includes a plurality of separate system parts, and for permitting communication between at least two of the system parts. A common reference signal having a reference frequency is distributed to all system parts. An internal signal clock oscillator of each system part is phase locked to the reference signal. Data is communicated between the at least two system parts by relating the reference signal with the internal clock signal of each of the two system parts by adjusting a phase position of the internal clock signal of a second of the two system parts dependent upon a time delay of the data communicated from the first system part to the second system part so that the phase positions of the internal clock signals correspond.

Abstract: A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.

Abstract: The circuit arrangement for generating two signals staggered in time from a clock signal and for measuring their time stagger receives at its input a clock signal, from which it generates an undelayed signal and a signal delayed relative to the undelayed signal. The generated signals appear at a first and second output of the circuit arrangement, respectively. A delay time measuring arrangement comprises a reversible inverter connected between the input of the circuit arrangement and the first output of the circuit arrangement and a NAND gate. The NAND gate receives at one input the delayed signal and at the other input the output signal of the inverter and furnishes an output signal from which the time stagger existing between the undelayed signal and the delayed signal can be precisely determined. The reversible inverter is switchable by a switching signal between a non-inverting condition in a working phase and an inverting condition in a measuring phase.

Abstract: A method and apparatus for distributing clock signals in an integrated circuit is disclosed. In a preferred embodiment, the power grid of the integrated circuit is used to distribute a periodic timing signal, in addition to the power supply voltage, to local areas of the integrated circuit, the local areas having circuitry for extracting a local clock signal from the periodic timing signal. Instead of simply carrying a DC power supply signal, the power grid is provided with a waveform constituting the sum of the DC power supply signal and the periodic signal, and the power grid then supplies all areas of the integrated circuit with this waveform. Local circuits then tap the power grid as needed to extract the periodic signal, from which local clock signals are then generated. In another preferred embodiment, a periodic timing signal is provided in the form of electromagnetic radiation to local areas of the integrated circuit by means of an optical or radio frequency transmitter.

Abstract: A method and apparatus are provided for synchronizing communications between different integrated circuits having different individual clock rates. In accordance with exemplary embodiments of the invention, a common clock signal is provided having a frequency greater than or equal to the highest individual clock rate, and the common clock signal is divided to obtain individual clock signals for the different integrated circuits For each integrated circuit an arrangement including a switching device and an edge-triggered storage member is also provided. The arrangement has an input for receiving signals, for example from the other integrated circuits. The arrangement also has an output connected to an input of the integrated circuit. The common clock signal and the individual clock signal corresponding to the integrated circuit are provided to the arrangement.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Abstract: A non-overlapping two-phase signal generator includes an oscillator to produce an oscillation signal of period 2t, a NAND (or NOR) gate, and a 2t-long time delay circuit. The output terminal of the oscillator is connected to one input terminal of the NAND (or NOR) gate; the output terminal of the NAND (or NOR) gate is connected to the input terminal of the delay circuit; and the output terminal of the delay circuit is connected to the other input terminal of the NAND (or NOR) gate. Non-overlapping two-phase signals appear at the output terminal of the delay circuit and at the output terminal of the NAND (or NOR) gate.

Abstract: A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other.

Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.

Abstract: A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected.

Abstract: A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.

Abstract: Letting p be a definite integer, q be a varying integer from 1 to p, r be an arbitrary integer such that 1.ltoreq.r.ltoreq.p, and s be a varying integer from 2 to 2p+1, among a total of 2p+1 fan-like stages each having fan-out outputs thereof equalized to each other in load and number of associated fan-like stages, a respective 2q-th one comprises branch circuits each composed of one of a pair of logic gates, a 2r+1-th one comprises branch circuits each composed of a multi-input logic gate, a respective 2q-1-th one excepting the 2r+1-th one comprises branch circuits of which any one is composed of the other of the pair of logic gates, and a respective s-th one comprises branch circuits each respectively arranged within a cell layout region therefor and connected to an s+1-th stage at a vicinal location to a barycenter of the cell layout region to repeat a fan-out output of an s-1-th fan-like stage, as it is a clock signal distributed thereto.

Abstract: A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks.

Abstract: An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc-Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers invert the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.

Abstract: A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit.

Abstract: External control signals are input to a semiconductor memory device via a synchronizing semiconductor circuit. An internal clock (ICLK) in the synchronizing semiconductor circuit is produced as a phase shifted version of an external clock (S11) which is input to the memory device. First latch circuits (321-324) latch external control signals in response to the external clock (S11). Decoder circuits (331.sub.0 -331.sub.n) produce internal control signals (S31.sub.0 -S331.sub.n) based upon the latched signals (S21-S24) output from the first latch circuits (321-324). Second latch circuits (341.sub.0 -341.sub.n) latch the internal control signals (S31.sub.0 14 S31.sub.n) in response to the internal clock signal (ICLK).

Abstract: A circuit for producing multiple pulse width modulated outputs. The circuit includes a logic device for each pulse width modulated output. Each of the logic devices includes a first input, a second input, and a clock input, and each of logic device produces a logical high output in response to a logical high at its first input in coincidence with a clock signal at its clock input. The logical high output of the logic device remains high until a logical high is applied at its second input in coincidence with a clock signal at the clock input, whereupon the logic device produces a logical low output. The logical low output of the logic device remains low until a logical high is again applied at its first input in coincidence with a clock signal at the clock input. The circuit includes programmable circuitry for selectively applying logical high and low signals to the first and second inputs of the logic devices.

Abstract: A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.

Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate.

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: A multi-phase clock generator for receiving an external clock signal through a PLL and for generating a plurality of internal clock signals differing in phase from each other. The multi-phase clock generator includes two large gates whose outputs are the two internal clock signals, and two latch circuits for controlling the logic gate outputs. The output from the PLL is fed forward to the logic gates so that the rise of one internal clock signal is separated from a prior fall of the other internal clock signal by a period related to the frequency of the PLL output.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: A clock distribution system for low power operation. Such a clock distribution system includes a global clock generation circuit coupled to generate a global clock signal. This global clock signal is received by a local clock generation circuit which generates a local clock signal. While the system has an operating voltage generally used throughout the system, at least one of the global clock signal and the local clock signal is a small swing clock signal which has a voltage swing substantially less than the operating voltage of the system.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: An illuminator system is provided that is responsive to a trigger signal from a remote source to supply controlled pulses to a load, such as an array of light emitting diodes in a LED strobe. The LED strobe is positioned in close proximity to a lens mounting system. The system of the present invention includes a remote trigger source, a load such as an array of light emitting diodes, and a pulse gate section. The pulse gate section includes a trigger interface having an input connected to the trigger source and is configured to generate a pulse trigger signal in response to a trigger signal from the trigger source. A clock generator responds to the pulse trigger signal by generating at least one clock signal, and a flash pulse generator responds to the clock signal and to at least one user definable input signal by generating a flash pulse signal. The flash pulse signal is used to activate or deactivate the load, and a load drive section is used to drive the load.

Abstract: The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.

Abstract: A remote clock signal generation means is provided which allows a plurality of clock signals to be generated remotely at the "leaf" level thereby removing the need to have multiple clock signals at the system, or "tree" level. More particularly, this system is designed for use in an LBIST circuit featuring LSSD master-slave clock control. This disclosure teaches a clock control method and structure in which the master and slave clocks are generated directly from the system clock after the clock powering logic to thereby avoid intrusion or modification effects associated with logical manipulation of the clock signals.

Abstract: Independent functional units are clocked by a clock source generator having at least two adjustable delay lines for independently adjusting the duty cycles of at least two clocks so that speed path margins are individually optimized for each functional unit.

Abstract: A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the circuit comprising a plurality of data drivers and a plurality of delayed I/O clock generators, wherein the I/O clock generators generate delayed I/O clocks signals that follow the I/O clock signal by a phase multiple of the core clock signal. The integrated circuit outputs data through output nodes that are synchronized with I/O clock signal. By outputting data signals in the I/O clock domain and using the delayed I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals are valid before the external component latches the data. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signal is valid before the external component latches the data.

Abstract: A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.

Abstract: A clock signal generated by a clock signal generating circuit is supplied to a frequency-dividing circuit formed using a D-type flip-flop circuit, being supplied to a controlled circuit after being divided down. Furthermore, the clock signal generated by the clock signal generating circuit is supplied to the controlled circuit by way of a through circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity of the frequency-dividing circuit, the through circuit being formed using the D-type flip-flop circuit in the same way as the frequency-dividing circuit.

Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.