Abstract: Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.

Abstract: A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

Abstract: An apparatus for generating a clock signal of a semiconductor Integrated circuit includes a first clock driver block configured to generate a plurality of first clock signals, a second clock driver block configured to generate a plurality of second clock signals, and a controller configured to stop an operation of at least one of the first clock driver block and the second clock driver block when the semiconductor Integrated circuit is in a predetermined operational state.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.

Abstract: The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.

Abstract: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

Abstract: Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.

Abstract: Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

Abstract: Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.

Abstract: An internal clock generator that modulates a high-frequency clock signal to a low-frequency signal to transmit the low-frequency signal if a transmission line for transmitting the high-frequency clock signal is long, and then restores the transmitted low-frequency signal to the high-frequency signal. The internal clock generator includes a first signal generation unit for receiving a first signal having a first frequency and generating a second signal having a second frequency that is lower than the first frequency, and a second signal generation unit for receiving the second signal and generating a third signal having a frequency equal to the first frequency. Here, the third signal is used as a signal for controlling an operating time point of an internal circuit of a synchronous memory device.

Abstract: A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control signal.

Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external clock signal and a drowsy clock signal output unit configured to divide frequencies of the plurality of clock signals by a first factor, align the frequency-divided clock signals so that each consecutive clock signal has a constant phase difference relative to a phase difference of a preceding clock signal, and output the drowsy clock signals having lower frequencies and different phases. The integrated circuit device also includes a feedback unit configured to divide frequency of a clock signal with a phase angle of 0 output by the phase synchronizer by the first factor and output the frequency-divided clock signal having a phase angle of 0 degrees to an input port of the phase synchronizer.

Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

Abstract: A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks. An optical driver circuit of an optical driving system and a method for implementing a write-strategy for preventing “overlapping” of marks written on adjacent grooves on an optical disc. The circuit and method produce multiple write-strategy waveforms (channels) switching at a high resolution (e.g., T/32) in the Gigahertz frequency range.

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract: A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.

Abstract: A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n?1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N?1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.

Abstract: A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have a first negative delay property respectively and of which an even number is ring-coupled; and a second delay block including second unit blocks which have a second negative delay property respectively and of which even number is ring-coupled. The number of the first unit block and the number of the second unit block are the same. A plurality of output nodes is formed based on one-to-one sharing between the first unit block and the second unit block having output signals of different level. Each output node outputs a pulse generated by racing the output signals of different level to each other which are provided from the first unit block and the second unit block connected to the each output node.

Abstract: A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.

Abstract: An integrated circuit includes first and second circuits, and a clock structure. The clock structure consists of a crystal oscillation circuit, a plurality of buffers, and a plurality of clock generating modules. An input of each of the plurality of buffers is coupled to receive a reference clock signal from the crystal oscillation circuit. Each of the plurality of clock generating modules is coupled to a corresponding one of the plurality of buffers and, when enabled, generates a clock signal.

Abstract: A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Abstract: The real number counter subtracts the positive integer C if the count value RC is equal to or larger than 0, or adds (the positive integer B-C) and outputs a Carry if the count value RC is negative. The first integer counter for generating the first clock f1 calculates (the count value IC1+the Carry+the positive integer A). The second integer counter 150 for generating the second clock f2 (f2=f1*G) calculates (the count value IC2+the Carry+the positive integer A+the offset value) at each input clock. The correction circuit outputs the offset value so that the second integer counter counts “the maximum count value*(f2/f1?1)*D” times more than the first integer counter with respect to each cycle D having a synchronization cycle length of the first clock f1 and the second clock f2.

Abstract: An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.

Abstract: A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

Abstract: A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2.

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: multiple clocked elements; a clock signal source providing clock signals to the multiple clocked elements; and a clock shifting means coupled between the clock signal source and each of the multiple clocked elements; wherein the clock shifting means shifts clock signals of the multiple clocked elements such that the clock signals of the multiple clocked elements have aligned active edges and misaligned inactive edges to reduce the clock noise generated by the inactive edges of the clock signals.

Abstract: A flip-flop circuit of the present invention includes a first switch and a second switch which are connected in series to each other. The first switch includes: two input ports upon which light source light and signal light are incident; two output ports for outputting an optical output; and a thermal lens forming element for forming a thermal lens in a predetermined optical inputting condition. Although the second switch is composed in the same manner as that of the first switch, a relation between the wave-lengths to be utilized is inverted. When a state is changed from OFF to ON, a pulse signal is inputted for setting and one of the rays of output light of the second switch is fed-back to the first switch so as to maintain the state of ON. When the state is changed from ON to OFF, a pulse of additional signal light is inputted. Due to the foregoing, the two states of ON and OFF can be stably maintained.

Abstract: A network processor or other type of processor includes clock generation circuitry which generates one or more clock signals for each of a number of clock domains of the processor. The clock generation circuitry comprises at least one clock generator and at least one control register subject to software-based updating. The clock generation circuitry determines a first clock configuration for the processor based on sampling one or more external clock configuration signal lines of the processor, and configures the clock generator in accordance with the first clock configuration. The clock generation circuitry subsequently determines a second clock configuration for the processor, different than the first clock configuration, based on contents of at least one control register subject to software-based updating, and reconfigures the clock generator in accordance with the second clock configuration.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.

Abstract: A clock generator includes a first circuit, a second circuit, and a third circuit. The first circuit generates a first clock signal. The second circuit divides the frequency of the first clock signal to generate a second clock signal. The third circuit generates a third clock signal from the first and second clock signals. The third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.

Abstract: This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock signal, level sense type sequence circuits which are contained in the functional modules and configured as clock supply destinations, a clock supply system which propagates the clock signal to the level sense type sequence circuits, etc. The clock supply system includes a clock wiring which propagates the clock signal outputted from the clock generator to ends thereof via a plurality of branches. At least pulse generators are disposed in the midstream of the clock wiring. Each of the pulse generators varies timing provided to change the falling edge of the clock signal, which defines an endpoint of an input operating period of each level sense type sequence circuit.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Abstract: A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

Abstract: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: A pulse generating circuit includes a starting circuit which generates m (two or larger integer) starting signals at predetermined time intervals based on a generation starting signal, and m pulse wave generating sub circuits which have the same characteristics and generate pulse waves having pulse width Pw for n cycles (n: 1 or larger integer) based on the respective m starting signals.

Abstract: Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and the control signal. A delay circuit provides a delay to the clock signal based on the delay control signal.

Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.