Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: A synchronous memory device and system are described which communicates bi-directional data via a bus and data clock. To capture data from the bus, a memory device latch circuit is described which operates in response to internally generated clock signals. A pulse generator circuit is described which produces these internal clock signals, and insures accurate latching of data by minimizing signal skew between the internal clock signals to avoid wasting valuable timing. The pulse generator circuit has at least two propagation paths that are symmetrical and operate in response to clock signals which are 90 degrees out-of-phase. A second pulse generator circuit is described minimizes skew by having symmetrical clock paths and also corrects duty cycle error present on the data clock. This second circuit uses three clock signals which have relative phases of 0, 90 and 180 degrees.

Abstract: A clock pulse transmission circuit is provided which can automatically correct, in case the duty factor of transmitted clock pulses has an error, the duty factor error. In a receiving unit 2, a pair of positive and negative clock pulses Sp and Sn transmitted from a transmitting unit 1 are inputted to a receiver 12 which outputs, in response thereto, a pair of positive and negative clock pulses V3 and V4. The DC components of these positive and negative clock pulses are taken out by a first integrator circuit and a second integrator circuit respectively to transmit them to the transmitting unit 1 through a pair of transmission lines 25 and 26, respectively. In the transmitting unit 1, a difference between the direct current levels of the respective positive and negative clock pulses is found and integrated. The integrated value is supplied to a driver 6 as a threshold voltage Vth.

Abstract: A clock driver circuit includes a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common line 18 and 21. The second common line 21 is connected to a plurality of clock signal supply lines 20(1) through 20(m) which in turn are connected to the clock input nodes of second macro cells 16 each requiring a clock signal. In a test mode, the clock signal supply lines 20a(1) through 20a(m) of the first clock driver 15a are connected respectively to the clock signal supply lines 20b(1) through 20b(m) of the second clock driver 15b by connection means 22. Thus, a clock driver circuit is provided which offers high driving ability with negligible clock skews in both normal mode and test mode.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A multiplier and a neural network synapse capable of removing nonlinear current using current mirror circuits. The multiplier produces a linear current by using MOS transistors operating in a nonsaturation region. The multiplier includes a first current mirror including a plurality of MOS transistors to form a first current and a second current mirror including a plurality of MOS transistors to form a second current, wherein the second current mirror is coupled in parallel to the first current mirror. As a result, the multiplier outputs an output current by subtracting a second current from said first current.

Abstract: External control signals are input to a semiconductor memory device via a synchronizing semiconductor circuit. An internal clock (ICLK) in the synchronizing semiconductor circuit is produced as a phase shifted version of an external clock (S11) which is input to the memory device. First latch circuits (321-324) latch external control signals in response to the external clock (S11). Decoder circuits (331.sub.0 -331.sub.n) produce internal control signals (S31.sub.0 -S331.sub.n) based upon the latched signals (S21-S24) output from the first latch circuits (321-324). Second latch circuits (341.sub.0 -341.sub.n) latch the internal control signals (S31.sub.0 14 S31.sub.n) in response to the internal clock signal (ICLK).

Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q.sub.3 and a BJT Q.sub.5 and also the BJT Q.sub.3 is coupled in series to the n-channel MOSFET M1 between the voltage V.sub.1 and a ground voltage level. A second current mirror includes a BJT Q.sub.7 and a BJT Q.sub.8. A third current mirror includes a BJT Q.sub.4 and a BJT Q.sub.6. Consequently, input voltage signals V.sub.1 and V.sub.dc applied to the n-channel MOSFETs M1 determine the current I.sub.1 and input voltage signals V.sub.1 and V.sub.2 applied to the n-channel MOSFET M2 determine the current I.sub.2.

Abstract: A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: The present invention provides a clocking circuit allowing individual macrocells in a particular macrocell block of a CPLD to use different polarities of the same clock. The input clock pin can now drive all the macrocells directly, which can eliminate additional buffering states and improve the clock to out timing, Tco, by (for example) 300 ps. The clocks are presented directly to the clock selection multiplexers for each macrocell. Additional functioning may be realized by implementing additional configuration bits inside the clocking architecture.

Abstract: Generator of clock pulses having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator controlled by a binary selection signal having a first and second logic level, in order to generate periodic pulses having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor triggered by the periodic pulses and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal and the periodic pulses, and generating the selection signal at a f

Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: A clock generation circuit which includes a first circuit for generating first and second trains of non-overlapping and opposite phase clock pulses from an input train of clock pulses, and second and third circuits each for generating a pair of non-overlapping and opposite phase trains of clock pulses from one of the first or second trains of opposite phase clock pulses provided by the first circuit.

Abstract: A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: A semiconductor integrated circuit device is equipped with a series of data handling stages, at least one of which includes a plurality of functional blocks arranged in parallel, a connecting means for connecting the functional blocks to functional blocks in a subsequent data handling stage, and a detection means for detecting data flow along a first connection in the connecting means. The detection means is included within a control means which controls data flow through at least one other connection in the connecting means based on the detection of data flow through the first connection in the connecting means.

Abstract: A signal is supplied to a number of synchronizing circuits with a small skew. A signal supply circuit (400a) includes four driver circuits (1a), (401), (402) and (403). The driver circuit (1a) receives an input signal which is supplied to synchronizing circuits (301) to (332). An output of the driver circuit (1a) is supplied to the left-hand side edge of a first wire (5). The driver circuits (401), (403) and (402) are disposed at the left-hand side edge, the right-hand side edge and a center of first wire (5), respectively, so that outputs from the driver circuits (401), (403) and (402) are supplied to a second wire (6). Input terminals of the synchronizing circuits (301) to (332) are each connected to the second wire (6). The driver circuits (401), (402) and (403), i.e., second signal transmitting elements, start transmission in this order, and therefore, a transition of the signal becomes abrupt at the driver circuits (401), (402) and (403) in this order.

Abstract: A clock-generating circuit for logic circuits with clock-controlled decoupling stages includes an interlock circuit which, in an interlocking mode, sets the outputs of the clock-generating circuit and thus, the clock lines, to an interlocking potential, thereby causing the decoupling stages to be placed into a shunt-current-free operating state.

Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.