Abstract: A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

Abstract: An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay.

Abstract: A semiconductor device includes a clock buffer block for receiving and buffering an external clock signal and then outputting an internal clock in response is a second control signal; a clock enable buffer block, which is enabled by a buffer enable signal, for comparing a reference voltage having a constant potential with a clock enable buffer signal and then generating a first control signal; a clock enable signal timing control block for outputting the second control signal by passing the clock enable signal to the clock buffer block in response to the buffer enable signal or by delaying the clock enable signal for a predetermined time; and a clock enable signal latch block for generating the enable signal after a power-up signal is inputted.

Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.

Abstract: A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

Abstract: A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.

Abstract: A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

Abstract: An interconnect structure includes a signal wire and an active shield line adjacent to, but removed from, the signal wire. The interconnect structure also includes another active shield line adjacent to, but removed from, the signal wire. A signal driver is connected to the signal wire. The signal driver drives a pulse on the signal wire. A shield driver is connected to the active shield line. The shield driver asserts a signal on the active shield line substantially simultaneous with the pulse. Another shield driver is connected to the another active shield line. The another shield driver asserts a signal on the another active shield line substantially simultaneous with the pulse. The effect of the simultaneous signals on the signal wire and the active shield lines is to effectively cancel the lateral capacitances between these lines.

Abstract: Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.

Abstract: A clock modulating circuit includes a first to nth delay circuits, a selection signal generator and a selection circuit. The first delay circuit receives an original clock signal and outputs a delayed clock signal. The second to nth delay circuits receive the delayed signal output from the preceding delay circuit and output delayed clock signals. The selection signal generator outputs a selection signal in response to the original clock signal. The selection signal has an instruction for selecting in ascending order from the first to nth delay circuits and then in descending order from the nth to first delay circuits. The selection circuit is connected to the first to nth delay circuits and the selection signal generator. The selection circuit receives the delayed signals from the first to nth delay circuits and outputs one of the delayed clock signals in response to the selection signal.

Abstract: An improved oscillator system has a control logic block which has an input from an external device to which clock is being provided. The input controls a counter which counts cycles from the oscillator. If some predetermined number of cycles has passed in the absence of a predetermined input condition, then the oscillator halts, thus reducing power consumption by the oscillator system. Later, upon the predetermined input condition, the oscillator resumes oscillation. The system has improved noise immunity and permits a continuous-oscillation mode without the need of an extra pin or memory bit. The control logic block may also employ a counter which counts the number of times the predetermined input condition has occurred, and only after some predetermined number of occurrences does the oscillator-halting activity take place.

Abstract: A phase detection system and method for use with a synchronous mirror delay (“SMD”) or a delay-locked loop (“DLL”) reduces the number of delay stages required and increases efficiency. The invention takes a clock input signal and clock delay or feedback signal, each having timing characteristics, and differentiates between four conditions based upon timing characteristics of the signals. The phase detector and associated circuitry determines, based upon timing characteristics of the signals, which phase conditions the signals are in. Selectors select the signals to be introduced into the SMD or DLL by the timing characteristics of the phase conditions. The invention utilizes the falling clock edge of the clock input signal and decreases the lock time under specific phase conditions. The invention increases efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.

Abstract: Counter-based duty cycle correction (DCC) circuits and methods. A first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in a register. Thus, the value stored in the register represents a point halfway through the input clock period. Each time the input clock signal changes from a first state to a second state, an output clock generator also changes the output clock signal from the first state to the second state, and the second counter is enabled. A comparator compares the value in the second counter to the value stored in the register. When the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached, and the output clock generator changes the output clock signal from the second state back to the first state.

Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.

Abstract: An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Abstract: A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

Abstract: Disclosed is a clock signal control device which has: an oscillator which generates a clock signal; a pulse detecting circuit which detects the frequency or duty of the clock signal and outputs a control signal based on the result of detection; and a clock signal supply selecting circuit which generates a supply clock signal from the clock signal generated from the oscillator in response to the control signal from the pulse detecting circuit.

Abstract: A high-speed digitally voltage controlled oscillator with 1/N phase resolution, having a load counter, 1/N phase difference generator, a multiplexor, a clock selector, and a load controller. The high-speed digitally voltage controlled oscillator only needs a load counter with an input frequency D+1 (D is far smaller than N) times an output frequency thereof. The phases of first and (M/2+1)th phases of M clock signals with 1/N phase difference (M is far smaller than N) generated by the 1/N phase difference generator are fixed at 0° and 180° with respect to a reference clock. Therefore, only (M/2−1) clock signals are affected by variation of process parameters. Consequently, the high-speed digitally voltage controlled oscillator can tolerate variation error of process parameter and is applicable for high resolution and high frequency operation.

Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.

Abstract: A semiconductor device includes a transmission line bounded by a first buffer and a second buffer. The first and second buffers are placed such that the transmission line has a length between a minimum and a maximum, thereby permitting narrow clock signal pulses to be transmitted with reduced distortion.

Abstract: A delay locked loop has a delay unit with a delay time that can be controlled in a manner dependent on a control signal. In order to generate complementary delayed clock signals, provision is made of switching elements, which tap off the clock signal to be delayed along the series circuit of delay elements. Each of the delay elements has a series circuit of two inverters. One of the delayed clock signals is tapped off in each case at the output of the second of the inverters of the delay elements, and the complementary output signal from the delayed output signals is tapped off at the first of the inverters. What is thus made possible is that, disregarding the frequency of the clock signal to be delayed and the length of the delay time, the complementary delayed clock signals always have the same phase angle with respect to one another.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: A master clock input circuit with excellent amplification characteristics which generates little noise during mode switching. In a master clock input circuit, the output electric potential of an amplification gate circuit (for example, a NAND gate) is superimposed on a master clock and supplied to the input terminal of an amplification gate circuit. A transmission gate circuit and impedance control gate are provided between the output terminal and input terminal. The transmission gate circuit has low impedance and the impedance control circuit has high impedance. The transmission gate circuit opens and closes the line between the output terminal and input terminal of the amplification gate circuit. Since the impedance of the transmission gate circuit is low, generation of noise is reduced. In addition, since the impedance of the impedance control circuit is high, the amplification factor of the amplification gate circuit becomes higher.

Abstract: A digital spread spectrum system provides a simple, digital device and method for reducing electromagnetic interference even where a clock signal to the device is rapidly turned on and off. A primary clock signal drives a signal selector. A signal delay is provided in the circuit to provide delayed clock pulse signals. The signal delay detunes the primary clock signal. By repeatedly switching the delay in and out of the clock signal path, a first signal is generated having a frequency at or about the clock signal, and, a second signal is generated which is displaced slightly from the first signal, but still at or about the clock frequency. By repeatedly switching the delay in and out of the primary clock signal path at a rate greater than the frequency of the clock signal, smaller portions of each primary clock pulse may be parsed for subsequent reaggregation to create a spread spectrum clock signal.

Abstract: A system and method for distributing clock signal information as rising and falling edge signals is disclosed. In one embodiment a first pulse signal includes a pulse generated for the rising edge of each clock pulse signal includes a pulse generated for the falling edge of each clock pulse. The temporal information associated with the time delay of the leading edges of corresponding pulses of the first and second pulse signals may be used to recover the clock signal. In one embodiment, skewed amplifiers are used to amplify the first and second pulse signal edge pulse. In one embodiment, the first and second pulse signals are regenerated and amplified before they are and into a tri-state buffer to recover the clock signal.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A control circuit for a FIFO datapath is described. The control circuit consists of a chain of Muller C-elements with adjustable delay elements placed between the output of each Muller C-element and one of the inputs of the preceding and successive Muller C-elements. The adjustable delay elements allow the control circuit to match the delays of processing elements in the datapath, thereby creating overall faster operation.

Abstract: An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.

Abstract: A method and apparatus for synthesizing an approximation to a sine wave comprising generating a number of pulse width modulated signals, each having a predetermine duty cycle and being the same frequency as each other, from a clock signal. The generated pulse width modulated signals are then combined to produce an approximation to a sine wave having the same frequency as the pulse width modulated signals. The clock signal is provided by an oscillator arranged to produce clock signals over a continuous range of frequencies so that approximations to a sine wave can be produced over a continuous range of frequencies.

Abstract: A waveform generation apparatus comprises a delay circuit comprising i pieces of unit delay circuits connected in series, and providing i kinds of delay states by deriving signals from the respective unit delay circuits; k pieces of selection circuits each selecting one delay state from among the i kinds of delay states; a waveform generation circuit for generating n pieces of binary state signals in the same state, or generating n pieces of binary-state signals having a shape according to recording data supplied from the outside, on the basis of the signals having the i kinds of delay states; a transmission path for transmitting the n pieces of binary-state signals generated by the waveform generation circuit; a waveform synthesis circuit for generating a signal having multi-valued information from the n pieces of binary-state signals transmitted through the transmission path; a phase difference detection circuit for detecting phase differences among the n pieces of binary-state signals in the same state, wh

Abstract: A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

Abstract: An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Abstract: A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Abstract: A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

Abstract: For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to an input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.

Abstract: A clock generating circuit 10, for generating a clock signal of which frequency is variable, has a delay circuit 20, a selector 30 and a control circuit 40. The delay circuit 20 has buffers 21 to 24 for delaying the input clock signal and output terminals 30A to 30D each of which outputs a clock signal delayed by a different delay time. The selector 30 selects one of the output terminals in the delay circuit 20, based on the output from the control circuit 40. The control circuit 40 supplies an output signal formed of a group of bits that is circulated in a predetermined cycle, to the selector 30. A cycle in an output clock signals OUT sequentially outputted from the output terminal 12 through the output terminals selected by the selector 30 increases or decreases in accordance with the group of bits in the output signal. Thus, the frequency in the output clock signal OUT will vary to reduce EMI noise.

Abstract: A method for increasing a transition time period for an edge transition of a clock signal has been developed. The method includes detecting an edge transition of a clock signal of a computer system. Next, additional system power consumption is initiated upon detection of the edge transition. This additional power consumption will lengthen the edge transition time period of the clock signal.

Abstract: A clock generator having a deskewer is disclosed. The clock generator includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: The problem of undesired power consumption in an oscillator during “stop” periods of a device is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line communicating an oscillator “clock” signal. If the device enters a “stop” state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the “no-stop” state. In response to the relatively low current, the apparatus halts oscillation. Later, when the device exits the “stop” state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: A clock generator is provided which controls a leading edge and a trailing edge of a clock to come to an arbitrary position for every clock pulse. A base clock pulse is generated, and then at least first and second clock pulses are generated by delaying the base clock pulse, wherein phases of each of the base clock pulse, the first clock pulse, and the second clock pulse are different from each other. The first clock pulse and the second clock pulse are selected in order so as to synthesize an output clock pulse from the first clock pulse and the second clock pulse within one cycle period of the output clock pulse, so that a leading edge portion of the output clock pulse comprises the first clock pulse and a trailing edge portion of the output clock pulse comprises the second clock pulse within the one cycle period of the output clock pulse.

Abstract: An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

Abstract: A system and method are presented for multiplexing two or more clocking signals. In one embodiment, a first enable circuit is provided that receives a select signal, a first clocking signal, and an enable signal from a second enable circuit. The first enable circuit generates an enable signal in response to these signals. For example, the first enable circuit could include a flip-flop clocked by the first clocking signal that generates the enable signal when the first clocking signal has been selected (based on the select signal), when the enable signal from the second enable circuit is deasserted and the first clocking signal has reached a falling edge. The enable signal can then be used to filter the first clocking signal (e.g., using an AND gate) to provide the first clocking signal as an output signal. Using the system and method of the present invention, glitches and spikes seen when multiplexing two or more clocking signals can be avoided.

Abstract: An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.

Abstract: A frequency divider and method for dividing a clock signal. The frequency divider including a first configurable signal generator, a second configurable signal generator, a data source coupled to the signal generators providing configuration data based on instructions received at an instruction port, a sequencer generating the instructions coupled between the signal generators and the data source and passing the instructions to the instruction port of the data source, and combining logic coupled to the outputs of the signal generators to produce the reduced frequency signal.

Abstract: One embodiment of the present invention provides a system that uses a non-periodic signal to modulate the period of a clock signal. The system includes a latch with a latch input, a latch output and a clock input. Asserting the clock input of the latch causes a data value at the latch input to be stored into the latch, and to thereby appear at the latch output. The system also includes an inverting delay circuit that receives the clock signal from the latch output and generates an inverted and delayed clock signal, which feeds back into the input of the latch. The clock input of the latch is coupled to the non-periodic signal, so that the non-periodic signal is used to latch the inverted and delayed clock signal, so that the clock signal changes at a non-periodic interval. In one embodiment of the present invention, the inverting delay circuit includes a chain of an odd number of inverters.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: A signal generator (100) receives an input clock signal (X1) at a first frequency (F1) and derives an output clock signal (Y) at a second frequency (FY). An arrangement (110) using a first intermediate signal (Z) receives the input clock signal (X1) and provides a second intermediate signal (X2) by selectively providing transitions (119) of the second intermediate signal (X2) at time intervals (T2(n)) that are determined by a variable number (A+P(n)) of periods (TZ) of the first intermediate signal (Z). The second intermediate signal (X2) has a frequency (F2) that is in average (F′2) higher than the first frequency (F1). A phase-looked loop (PLL) circuit (180) locks at this average frequency (F′2) and provides the output clock signal (Y).