Abstract: A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed clock signals that are delayed relative to the input clock signal by various amounts of time. The clock signal selector randomly chooses one of the delayed signals based upon random numbers generated by the random number generator and produces a selector output signal based on its chosen delayed clock signal. A clock signal generator receives the selector output signal and produces an output clock signal.

Abstract: A CMOS low frequency oscillator circuit comprising an amplifier (10) and an interface for connecting a first and a second terminal of an external crystal oscillator (14) in a feedback path of the amplifier (10). In one aspect, the oscillator circuit further comprises a regulated current source (24) supplying a regulated current to the amplifier (10) controlled by the voltage swing across the external crystal oscillator (14); and a constant current source (32) supplying a minimum constant current to the amplifier (10) independent of the voltage swing across the external crystal oscillator (14).

Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

Abstract: A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: A clock generator and data driver for a liquid crystal display device in which the clock generator includes a bias voltage supply receiving a power supply voltage and generating a bias voltage, an internal clock generator converting differential clock signals into an internal clock signal in response to the bias voltage, a bias line electrically connecting the bias voltage supply and the internal clock generator to supply the bias voltage to the internal clock generator, and a shield line shielding the bias line and receiving a voltage having a level identical with a level of the bias voltage.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest-order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).

Abstract: A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: An internal clock generator according to the present invention includes a detector, an internal signal generator and a clock output unit. The detector detects a transition point of an external clock signal and outputting a detection signal. The internal signal generator generates an internal signal in response to the detection signal and a pulse width control signal. The clock output unit outputs an internal clock signal having a pulse width, which is set based on the internal signal. A transition point of an external clock signal is detected and an internal clock signal is generated based on the detection result. It is therefore possible to maintain the pulse width of the internal clock signal to a set value regardless of variation in the pulse width of the external clock signal.

Abstract: A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Abstract: The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: Clock regulation apparatus for preventing a logic switching mechanism from operating incorrectly. The apparatus has a supply voltage input that receives a supply voltage, which is also applied to the logic switching mechanism, a comparison unit that outputs an error signal if the supply voltage value drops below a reference value, a clock signal input that receives a clock signal from a clock generator, and a clock suppression unit, which is coupled to the clock signal input and to the comparison unit, that has a clock output for outputting the clock signal and that suppresses or delays the clock signal for a duration of at least one clock period if the error signal exists.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.

Abstract: A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Abstract: The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

Abstract: A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

Abstract: A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such.

Abstract: Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.

Abstract: The circuits and methods of the present invention relate to circuits for generating a multiplied clock signal based upon a reference clock signal, and circuits using the clock signal to deserialize data. According to one embodiment of the invention, a circuit comprising a counter is coupled to generate a count representative of the period of the input clock signal. A divider circuit coupled to the counter generates a divided count. Finally, a clock generator coupled to the divider circuit outputs an output clock signal having a period which is based upon the divided count. According to other embodiments, circuits and methods disclose receiving serial data using the output clock signal, and outputting the data as parallel data using the reference clock.

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract: Digital frequency synthesizer (DFS) circuits and methods use counters to define the positions of the output clock edges. A clock divider divides an input clock by a positive integer to provide a divided clock. A first counter circuit counts for one divided clock period, and the count is provided to a timing circuit that generates two or more sets of intermediate values. Each set represents a set of intermediate points within a period of the divided clock. Based on a specified multiplication value, one set of intermediate values is selected. Utilizing the divided clock, the selected set of intermediate values, and a second counter running at the same frequency as the first counter circuit, an output clock generator provides an output clock having an initial pulse at the beginning of each divided clock period, and a subsequent pulse at intermediate points represented by the selected set of intermediate values.

Abstract: A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate. The state machine includes state elements and associated logic. The associated logic is configured to allow said state elements to pass through a number of logic states for every same number of consecutive edges of the global clock when the associated logic is enabled. The number is a positive integer.

Abstract: A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.

Abstract: The phase-looked loop having spread spectrum clock generator of this invention comprises a phase-locked loop and a spread spectrum clock generator. The input signal of the phase-locked loop comes from a reference clock source. The output of the phase-locked loop is used as the standard clock signal and is also supplied to the spread spectrum clock generator, as its input. The spread spectrum clock generator comprises a clock frequency divider, a multiplexer and a counter. The clock frequency divider generates, based on the output of the phase-locked loop, at least tow of a divided-by-M frequency, a divided-by-M+1 frequency and a divided-by-M?1 frequency, which are supplied to the multiplexer. The phase selection of the multiplexer is supplied by the counter, which input is supplied by the output of the multiplexer. The output signal of the multiplexer is supplied to the phase-locked loop, as its feedback clock frequency.

Abstract: A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Abstract: Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

Abstract: A clock generating circuit includes a delay circuit which has input terminals and which delays a signal input from each of the input terminals by a different delay time, and outputs the delayed signal from at least one output terminal, a selective circuit which receives an input clock signal and selectively outputs the clock signal to one of the input terminals of the delay circuit, and a control circuit which switches selective operations of the selective circuit. A modulated clock signal in which the period of the clock signal is increased or decreased is output from the at least one output terminal of the delay circuit such that the control circuit sequentially switches the selective operations of the selective circuit.

Abstract: A circuit arrangement for generating a digital clock signal which manages without a crystal oscillator and has a low current consumption. The circuit arrangement includes: a transistor circuit having a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series, a comparator having a positive comparator input, a negative comparator input and a comparator output, a device for providing two switching thresholds to the negative input of the comparator, and a capacitance, which is alternately charged and discharged via the two FET transistors. The voltage present at the capacitance is fed to the positive comparator input, and the output voltage of the comparator, which represents a digital clock signal, is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors.

Abstract: A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract: A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.

Abstract: A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.

Abstract: The present invention relates to a circuit and method for generating an internal clock signal. According to the present invention, it is determined whether an external clock signal is a high frequency or a low frequency. Depending on the determination, the external clock signal is waveform-shaped to generate an internal clock signal or the external clock signal as the internal clock signal as it is. Therefore, rising edge timings of the external clock signal and the internal clock signal become coincident regardless of the frequency of the external clock signal. Reduction in an operating margin within the circuit due to reduction in the pulse width of the internal clock signal is prevented. Thus, the circuit of the present invention can be used in the high frequency and the low frequency at the same time and reliability of the circuit can be improved.

Abstract: A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Abstract: A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Abstract: Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.

Abstract: Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first combination of the phase selection signals, and further configured to switch from the first selected clock signal to a second selected clock signal in response to a second combination of the phase selection signal. The circuit disengages the first clock signal after the second phases selection signal is engaged.

Abstract: A clock shrink circuit has an inverting first matching stage which is responsive to an input clock signal to generate a first inverted signal having a first matching delay. The first matching delay is a difference between a first rise and a first fall propagation time of the first matching stage. An inverting first pull-up stage is coupled to the first matching stage and is responsive to the first inverted signal to generate a second inverted signal having a first pull-up delay which is substantially reduced by the first matching delay. The first pull-up delay is a difference between a second rise and a second fall propagation time of the first pull-up stage.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: Phase shifter circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and a delay value is determined based at least in part on the counted value. In some embodiments, the delay value has a maximum value that depends on the counted value. The delay value is provided to a second counter, which counts from zero to the delay value and generates a pulse one delay value after the beginning of the input clock period. A third counter running at the same clock rate generates a pulse after an additional delay. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle. Some circuits also perform a duty cycle correction.