Variable Attenuator Patents (Class 327/308)
  • Patent number: 10418973
    Abstract: A control circuit is disclosed for controlling operation of a radio frequency (RF) transistor. The control circuit has a first sub-circuit that accepts a reference voltage and a reference current. The control circuit has a second sub-circuit with a plurality of stacked transistors coupled between the first sub-circuit and ground, and a resistor ladder coupled between the first sub-circuit and an output port of the control circuit. The first sub-circuit provides the reference current to flow through the stacked transistors, and sets a total voltage drop across the stacked transistors equal to the reference voltage. The first sub-circuit also sets a total voltage drop across the resistor ladder equal to the reference voltage. Each rung of the resistor ladder is coupled to control an operating voltage of a stacked transistor, to cause each stacked transistor to operate with similar control conditions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 17, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Samuel Alfred Tiller, Kimia Taghizadeh Ansari, Tyler Neil Ross
  • Patent number: 10382003
    Abstract: An attenuation cell is provided for use in a switched attenuator. The attenuation cell includes an attenuation path that has an input, a first switch, a resistive network, a second switch, and an output. The resistive network provides a desired attenuation from the input to the output. The attenuation cell also includes a bypass path in parallel with the attenuation path with a bypass switch between the input and the output. The attenuation cell also has a shunt switch coupled between the resistive network and a reference node to selectively connect the resistive network to the reference node.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 13, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Adrian John Bergsma
  • Patent number: 10382010
    Abstract: A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Anokiwave, Inc.
    Inventors: Kristian N. Madsen, Robert J. McMorrow
  • Patent number: 10374602
    Abstract: Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 6, 2019
    Assignee: Analog Devices, Inc.
    Inventor: Omid Foroudi
  • Patent number: 10340892
    Abstract: A multi-channel digital step attenuator (DSA) architecture. One embodiment includes an array comprising N channels of B selectable attenuator cells series-connected. The overall impedance of a multi-channel DSA is a function of the parallel impedances of the N channels, and transition levels are reduced by 1/N since the transient effect of switching any one attenuator cell in or out of circuit in one channel is mitigated by all other in-circuit attenuator cells in the parallel channels. The multi-channel DSA architecture enables a great design flexibility, and allows a designer to vary one or more of at least the following design parameters: the number of attenuator cells B per channel; the number N of channels per DSA; the bit weighting of each attenuator cell per channel; the maximum attenuation per channel; and the characteristic impedance Zon of each channel.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: July 2, 2019
    Assignee: pSemi Corporation
    Inventors: Peter Bacon, Vikas Sharma
  • Patent number: 10333495
    Abstract: A programmable RF attenuator having a first connection node and a second connection node is disclosed. The programmable RF attenuator provides RF attenuation between the first connection node and the second connection node based on at least a first attenuation control signal. The programmable RF attenuator includes a first RF attenuator circuit and a first reactance compensation circuit, such that the first RF attenuator circuit includes a first shunt transistor element and a first shunt resistive element, which is coupled to the first shunt transistor element. The first shunt transistor element receives the first attenuation control signal. The first reactance compensation circuit is coupled to the first RF attenuator circuit and at least partially compensates for reactive characteristics of the programmable RF attenuator that affect an attenuation flatness of the programmable RF attenuator.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 25, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Donald L. Allen
  • Patent number: 10326443
    Abstract: A power amplifier module includes a transistor and transistor control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to control the transistor in a stand-by mode of operation.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 18, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Chu-hsiung Ho
  • Patent number: 10320379
    Abstract: Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Daniel Charles Kerr, Jinsung Choi, Baker Scott, George Maxim, Hideya Oshima
  • Patent number: 10277200
    Abstract: An attenuator includes a first high frequency signal input-output terminal and a second high frequency signal input-output terminal, a switch circuit, a plurality of resistors, and a variable capacitor. The plurality of resistors are respectively connected to the first high frequency signal input-output terminal while the resistors being parallel to each other. The switch circuit includes a plurality of selection target terminals respectively connected to the resistors and a shared terminal to which the plurality of selection target terminals are selectively connected and which is connected to the second high frequency signal input-output terminal. The variable capacitor is connected to one of the resistors in series and is so constituted as to have not a diode structure.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: April 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Atsushi Horita
  • Patent number: 10277201
    Abstract: Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (RON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 30, 2019
    Assignee: pSemi Corporation
    Inventor: Fleming Lam
  • Patent number: 10236863
    Abstract: A programmable voltage variable attenuator (VVA) that enables selection among multiple analog, continuous attenuation ranges. Some embodiments include a dual-mode interface to enable digitally programming a DAC and provide the analog output to control the attenuation level of the VVA, or alternatively apply an externally provided analog voltage to directly control the VVA attenuation level. A VVA may be used in conjunction with a digital step attenuator (DSA). Some embodiments include circuitry for changing the VVA reference impedance. The attenuator architecture of the VVA includes one or more variable resistance shunt elements and/or series elements which may be a resistor and FET circuit controlled by a provided variable analog voltage. The multiple resistance element architecture may be implemented with stacked FET devices. Embodiments for the VVA may be based, for example, on T-type, Bridged-T type, Pi-type, L-pad type, reflection type, or balanced coupler type attenuators.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 19, 2019
    Assignee: pSemi Corporation
    Inventor: Peter Bacon
  • Patent number: 10218347
    Abstract: A high frequency switch includes a first signal transferring unit configured to transfer a high frequency signal from a first port to a common port, and a second signal transferring unit configured to transfer the high frequency signal from the common port to a second port. The high frequency switch also includes an electrostatic discharge (ESD) protecting unit including a protective transistor positioned between the common port and a ground and a diode element positioned between a control terminal of the protective transistor and the first port.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 26, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Sang Wook Park
  • Patent number: 10211789
    Abstract: pHEMT-based circuits and methods of improving the linearity thereof. One example pHEMT circuit includes a pHEMT connected between an input terminal and a load and a non-linear resistance connected to the pHEMT. The pHEMT produces a first harmonic signal at the load responsive to being driven by an input signal of a fundamental frequency received at the input terminal, the first harmonic signal having a first phase. The non-linear resistance has a resistance selected to produce a second harmonic signal at the load having a second phase opposite to the first phase. Methods can include determining a first amplitude and a first phase of a first harmonic signal produced at the load by a pHEMT in an ON state, and tuning the non-linear resistance to produce at the load a second harmonic signal having a second amplitude and a second phase that minimizes a net harmonic signal at the load.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 19, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Fikret Altunkilic, Haki Cebi, Yu Zhu, Cejun Wei, Jerod F. Mason
  • Patent number: 10205439
    Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 12, 2019
    Assignee: pSemi Corporation
    Inventors: Ravindranath Shrivastava, Kristian Madsen
  • Patent number: 10193299
    Abstract: A system and method for an active Q-switched fiber laser cavity may include a pump source for emitting a laser beam at a wavelength along an optical path including an active optical medium. A modulation device may be configured to introduce tunable losses into the optical path. The tunable losses may be achieved through modulation of the transmissivity of an optical element within the optical path, the modulation of said optical element being performed over (i) a first period of time in which a cavity Q curve increases from a first percentage value to a second percentage value of a maximum Q value and (ii) a second period of time in which the cavity Q curve increases from a third percentage value to a fourth percentage value of the maximum Q value. The cavity Q curve may non-linearly and smoothly transition between (i) the first and second percentage values and (ii) the third and fourth percentage values.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 29, 2019
    Assignee: Datalogic IP Tech S.R.L.
    Inventors: Andrea Arcangeli, Mihamed Hammouda
  • Patent number: 10193531
    Abstract: Digital step attenuator (DSA) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (IC) die (or “chip”), and provide flexibility of design for various applications. Embodiments utilize one or more architectural features and/or design techniques to achieve such characteristics, including reduced resistor and FET switch sizes, reduced series stack sizes, unidirectional input power configurations, capacitor compensation to match bandwidth characteristics, activating low-power thermometer-weighted attenuator cells only after activating higher power thermometer-weighted attenuator cells, and reducing signal transients (glitches) using a thermometer-weighted configuration of attenuator cells.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 29, 2019
    Assignee: pSemi Corporation
    Inventor: Ravindranath Shrivastava
  • Patent number: 10177851
    Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: January 8, 2019
    Assignee: INPHI CORPORATION
    Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio Del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro Marcelo Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
  • Patent number: 10128823
    Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mazhareddin Taghivand, Yashar Rajavi, Alireza Khalili
  • Patent number: 10069492
    Abstract: A radio-frequency switch includes a series field-effect transistor, a shunt field-effect transistor having a gate node, and shunt arm control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to the gate node of the shunt field-effect transistor when the radio-frequency switch is in a stand-by mode of operation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 4, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Chu-hsiung Ho
  • Patent number: 10050593
    Abstract: A power amplifier module includes a first bipolar transistor configured to amplify a radio frequency signal and output an amplified signal and a second bipolar transistor. A base of the second bipolar transistor is supplied with a control voltage for controlling attenuation of the radio frequency signal, and a collector the second bipolar transistor is supplied with a source voltage. The power amplifier module also includes a first resistor, where one end of the first resistor is connected to a supply path of the radio frequency signal to the first bipolar transistor, and a capacitor, where one end of the capacitor is connected to the other end of the first resistor and the other end of the capacitor is connected to the collector of the second bipolar transistor.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 14, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji Saito
  • Patent number: 10020798
    Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: July 10, 2018
    Assignee: pSemi Corporation
    Inventor: Vikas Sharma
  • Patent number: 9973173
    Abstract: This disclosure relates to radio frequency (RF) front end circuitry used to route RF signals. In one embodiment, the RF front end circuitry has a filter circuit and a switch device. The switch device includes a common port, an RF port, and switchable path connected in series between the common port and the RF port. The switch device is configured to present approximately the filter capacitance of the filter circuit at the common port when the switchable path is closed. However, when the switchable path is open, the switch device is configured to present a device capacitance at the common port that is approximately equal to the filter capacitance of the filter circuit. In this manner, if the common port is connected to an antenna, the capacitance seen by the antenna from the common port remains substantially unchanged regardless of which of the switchable path is opened or closed.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 15, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Marcus Granger-Jones
  • Patent number: 9966946
    Abstract: In accordance with an embodiment, a radio frequency (RF) switching circuit includes a plurality of series connected RF switch cells having a load path and a control node, and a switch driver coupled to the control node. Each of the plurality of series connected RF switch cells includes a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the control node. The switch driver includes a variable output impedance that varies with a voltage of the control node.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 8, 2018
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Anthony Thomas
  • Patent number: 9954629
    Abstract: A repeater including an analog attenuator configured to attenuate an analog signal in response to a first control signal; an analog to digital converter (ADC) configured to convert the attenuated analog signal into a digital signal; a digital attenuator configured to attenuate the digital signal in response to a second control signal; and an attenuation controller configured to calculate average power and peak power of the attenuated digital signal, determine an attenuation value for each value of the calculated average power and peak power, and generate at least one of the first and second control signals based on the determined attenuation values.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 24, 2018
    Assignee: SOLiD, INC.
    Inventors: Nagwon Kwon, Hyunchae Kim
  • Patent number: 9929720
    Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 27, 2018
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Thomas Quemerais, Alice Bossuet, Daniel Gloria
  • Patent number: 9893722
    Abstract: RF switching circuitry includes one or more RF switching elements, a control signal input node, a common resistor, and common resistor bypass circuitry. The one or more RF switching elements are coupled in series between a switch input node and a switch output node. A state of each one of the one or more switching elements is determined based on a control signal. The control signal input node is configured to receive the control signal. The common resistor is coupled between the control signal input node and the one or more RF switching elements. The common resistor bypass circuitry is configured to receive the switching control signal and bypass the common resistor for a predetermined time period following one or more of a leading edge of the switching control signal and a falling edge of the switching control signal.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 13, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Mehra Mokalla
  • Patent number: 9882549
    Abstract: Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 30, 2018
    Assignee: Analog Devices Global
    Inventor: Ahmed Mohammad Ashry Othman
  • Patent number: 9871512
    Abstract: Systems, apparatuses and methods are disclosed providing a semiconductor die comprising a semiconductor substrate and a radio-frequency (RF) switch including one or more series field-effect transistors (FETs) and one or more shunt FETs, each of the one or more series FETs and one or more shunt FETs having a respective gate node, the RF switch being configured to receive an RF signal from a power amplifier module and provide the RF signal to an antenna. The semiconductor die may further comprise an internal regulator voltage source configured to provide an internal regulator voltage when the RF switch is in a stand-by mode and shunt arm control circuitry configured to provide the internal regulator voltage to the gate nodes of the one or more shunt FETs when the RF switch is in the stand-by mode.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 16, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Chu-hsiung Ho
  • Patent number: 9793893
    Abstract: A termination circuit includes a first transistor coupled to a first pad, a first resistor coupled between the first transistor and a second pad, and an operational amplifier circuit. The termination circuit provides termination impedance to input signals received at the first and second pads. The first transistor generates a first common mode voltage of the input signals at a first node between the first resistor and the first transistor in response to an output signal of the operational amplifier circuit. The operational amplifier circuit generates the output signal based on the first common mode voltage of the input signals and based on a second common mode voltage of the input signals. The termination circuit generates the second common mode voltage at a second node that is a different node than the first node.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 17, 2017
    Assignee: Altera Corporation
    Inventor: Hoong Chin Ng
  • Patent number: 9787286
    Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 10, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9762048
    Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9735881
    Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 15, 2017
    Assignee: INPHI CORPORATION
    Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Adrián Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, María Laura Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
  • Patent number: 9628059
    Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
  • Patent number: 9602091
    Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: March 21, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9496849
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Patent number: 9479141
    Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 25, 2016
    Assignee: NXP B.V.
    Inventors: Andreas Johannes Köllmann, Steffen Rode, Joachim Utzig, Joerg Syré
  • Patent number: 9467151
    Abstract: Provided herein are apparatus and methods for using tuning information to adaptively and dynamically modify the parameters of an RF signal chain. The tuning information from an oscillator core, having multiple oscillators, adaptively tunes parameters of system components within a signal chain. In this way the system components are tuned to operate within a band tailored to the signal and to the oscillator core. In addition, RF impedances can be matched and power added efficiency can be enhanced in an area efficient monolithic integrated circuit.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 11, 2016
    Assignee: Analog Devices Global
    Inventor: James Breslin
  • Patent number: 9444432
    Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: September 13, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ravindranath Shrivastava, Kristian Madsen
  • Patent number: 9418756
    Abstract: Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage compensation circuit includes an input terminal, an output terminal connected to the source of the thin film transistor, a first resistor to a Kth resistor connected in series, and Kth connectable link and at least one first connectable link. Since a voltage dividing circuit having connectable links divides the voltage input to the source of the thin film transistor, such that the gate-source voltage of the thin film transistor can be changed by changing the voltage of the source of the thin film transistor when the voltage of the gate of the thin film transistor is maintained unchanged, so as to control a leakage current of the thin film transistor under a turn-off state, such that the thin film transistor can be turned off normally.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 16, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yinan Liang, Lifei Ma, Lujiang Huangfu
  • Patent number: 9337934
    Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: May 10, 2016
    Assignee: ClariPhy Communications, Inc.
    Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Paul Voois, Ramiro Rogelio Lopez, Jorge Manuel Finochietto, Norman L. Swenson, Mario Rafael Hueda, Hugo Santiago Carrer, Vadim Gutnik, Ulises Morales, Martin Ignacio del Barco, Martin Carlos Asinari, Federico Nicolas Paredes, Alfredo Javier Taddei, Mauro M. Bruni, Damian Alfonso Morero, Facundo Abel Alcides Ramos, Laura Maria Ferster, Elvio Adrian Serrano, Pablo Gustavo Quiroga, Roman Antonio Arenas, Matias German Schnidrig, Alejandro Javier Schwoykoski
  • Patent number: 9331690
    Abstract: A switching circuit may include a switching circuit unit; a reference voltage unit connected between the switching circuit unit and a signal input terminal and providing a preset reference voltage; and a voltage generating unit dividing a first control voltage provided to the switching circuit unit by a preset magnitude to generate a second control voltage corresponding to the reference voltage, and providing the second control voltage to bodies of the plurality of respective switching devices.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyouck Choi, Kyu Jin Choi, Suk Chan Kang, Jeong Hoon Kim
  • Patent number: 9312853
    Abstract: A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: April 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atusi Sigetani, Takahito Miyazaki, Yusuke Nozaki, Masaru Fukusen
  • Patent number: 9159668
    Abstract: An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Min-Chia Wang
  • Patent number: 9111671
    Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: August 18, 2015
    Assignee: INVENSAS CORPORATION
    Inventors: Curtis Dicke, George Courville, David Fisch, Randall Sandusky, Kent Stalnaker
  • Publication number: 20150084681
    Abstract: A variable attenuator comprises a series resistance, and an adjustable shunt resistance, wherein the adjustable shunt resistance comprises a series circuit of a fixed resistor and a semiconductor element having an adjustable resistance.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Applicant: ADVANTEST (SINGAPORE) PTE. LTD.
    Inventor: Giovanni Bianchi
  • Patent number: 8988127
    Abstract: In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 24, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Marcus Granger-Jones, Brad Nelson, Ed Franzwa
  • Patent number: 8975938
    Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 10, 2015
    Assignees: STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Dimitri Soussan, Sylvain Majcherczak, Alexandre Valentian, Marc Belleville
  • Patent number: 8975940
    Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hayashi
  • Patent number: 8970278
    Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 3, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Marcus Granger-Jones, Christian Rye Iversen
  • Patent number: 8970279
    Abstract: There is provided a radio frequency switch circuit including a first switch circuit unit connected between a first node connected to a first signal port and a common node connected to a common port, and operated according to a first control signal, a second switch circuit unit connected between a second node connected to a second signal port and the common node and operated according to a second control signal having a phase opposite to that of the first control signal, a first shunt circuit unit connected between the second node and a common source node and operated according to the first control signal, a second shunt circuit unit connected between the first node and the common source node, and a source voltage generating unit generating a source voltage, wherein the source voltage is lower than a high level of the first control signal and higher than a ground potential.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Hoon Ha, Sung Hwan Park, Sang Hee Kim, Nam Heung Kim, Hyo Gun Bae