Abstract: A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

Abstract: Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Abstract: A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate the analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Abstract: A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

Abstract: Some applications require a noise filter to have a very low cutoff frequency. The low cutoff frequency can require the use of a large resistor that is not suitable for integration in an integrated circuit (IC) package. Smaller components can be used to provide a large resistance in a first direction but not in another. In other words, the resistance of these smaller components may be non-reciprocal. A non-reciprocal resistance can affect a response of the noise filter to disruptions at the input or the output. Additionally, these smaller components may not be suitable for low voltage operation. A noise filter is disclosed that provides a high resistance using components that can be included in an integrated circuit package. The noise filter has a reciprocal effective resistance and can utilize technology suitable for low voltage operation.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.

Abstract: A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

Abstract: A single-pole double-throw switch includes switching units which are set between a first port and a second port and between the first port and a third port, respectively, and are configured to perform complementarily. The each switching unit includes an antenna port, a circuit port, a transmission line configured to couple them, and a switching element connected between the transmission line and a ground. The switching element includes a parallel circuit including a transistor and an inductor connected in parallel, and a capacitor connected in series with the parallel circuit. The transmission line has a characteristic impedance different from a impedance seen inside the switching unit from the antenna port and a impedance seen inside the switching unit from the circuit port.

Abstract: A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Abstract: An apparatus including an electronic circuit. The apparatus includes a path unit configured to form a first impedance for controlling a gain of an input signal. The apparatus also includes a shunt unit configured to form a second impedance for performing attenuation between the path unit and a ground, wherein the path unit forms the first impedance using an on-resistance of at least one transistor.

Abstract: The disclosure relates to arrangements for antenna interfaces configurable to efficiently support different communication modes. This is achieved by an antenna connection circuit 10 for a communication device 1 wherein the antenna connection circuit 10 is configurable for communication modes. The antenna connection circuit comprises a first quarter-wave transformer qw1 coupled between an antenna port A and an transmitter port Tx, and a second quarter-wave transformer qw2 coupled between the antenna port A and a receiver port Rx. The antenna connection circuit further comprises a first ground switch s1 coupled between the receiver port Rx and a first ground connection g1, and a second ground switch s2 is coupled between the transmitter port Tx and a second ground connection g2.

Abstract: Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Abstract: An RF switch to controllably withstand an applied RF voltage VSW, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of VSW appearing across it may be controlled to approximately zero.

Abstract: A delay line includes one or more phase-shifting cells, where each phase-shifting cell includes a high-pass filter circuit that may be selectively coupled to or decoupled from a transmission line. The filter circuit is couplable in parallel with the transmission line and shifts a signal conveyed through the transmission line by a predetermined phase angle. The high-pass filter circuit includes one or more capacitors and one or more reactance elements (e.g., inductors). The selective coupling may be achieved using multi-gate transistors.

Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of ?100V to +100V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.

Abstract: A matching circuit comprising: an input-terminal configured to be connected to an active-circuit; an output-terminal configured to be connected to a downstream component; a current-source configured to provide a disabled-current; one or more diode-modules, each comprising a diode and a biasing-resistor in parallel with each other; and a reactive-matching-component that has a reactive impedance. The current source is configured to pass the disabled-current through the one or more diode-modules and the reactive-matching-component when the matching circuit is in a disabled-mode of operation such that they contribute to the impedance of the matching circuit between the input-terminal and the output-terminal.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A radio frequency switch is disclosed. The RF switch uses a combination of transistor technology and a topology to create an RF switch that has a high isolation and a high voltage breakdown at frequencies including those above a gigahertz.

Abstract: A semiconductor apparatus includes a termination voltage terminal, a first pin, a second pin, a first termination circuit and a second termination circuit. The first termination circuit is coupled between the termination voltage terminal and the first pin. The second termination circuit is coupled between the termination voltage terminal and a second pin. Resistance values of the first termination circuit and the second termination circuit may be determined on a basis of distances from the termination voltage terminal to the first pin and the second pin.

Abstract: The de-Qing loss and phase imbalance caused by the inherent capacitance of a switched resistance, such as a MOSFET with a resistor, can be reduced by using a shunting switch across the resistor that is in series with the resistor's switch. The shunting switch shorts across the resistor when the resistor's switch is open and in reference mode, thereby significantly reducing the resistance in series with the inherent capacitance of the open resistor's switch.

Abstract: In accordance with an embodiment, a radio frequency (RF) switching circuit includes a plurality of series connected RF switch cells having a load path and a control node, and a switch driver coupled to the control node. Each of the plurality of series connected RF switch cells includes a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the control node. The switch driver includes a variable output impedance that varies with a voltage of the control node.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A control circuit is disclosed for controlling operation of a radio frequency (RF) transistor. The control circuit has a first sub-circuit that accepts a reference voltage and a reference current. The control circuit has a second sub-circuit with a plurality of stacked transistors coupled between the first sub-circuit and ground, and a resistor ladder coupled between the first sub-circuit and an output port of the control circuit. The first sub-circuit provides the reference current to flow through the stacked transistors, and sets a total voltage drop across the stacked transistors equal to the reference voltage. The first sub-circuit also sets a total voltage drop across the resistor ladder equal to the reference voltage. Each rung of the resistor ladder is coupled to control an operating voltage of a stacked transistor, to cause each stacked transistor to operate with similar control conditions.

Abstract: An attenuation cell is provided for use in a switched attenuator. The attenuation cell includes an attenuation path that has an input, a first switch, a resistive network, a second switch, and an output. The resistive network provides a desired attenuation from the input to the output. The attenuation cell also includes a bypass path in parallel with the attenuation path with a bypass switch between the input and the output. The attenuation cell also has a shunt switch coupled between the resistive network and a reference node to selectively connect the resistive network to the reference node.

Abstract: A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.

Abstract: Techniques for linearizing a field effect transistor (FET) are provided. In an example, a method can include averaging a voltage at a drain node of the FET and a voltage at a source node of the FET to provide an average voltage, and applying the average voltage to a gate node of the FET.

Abstract: A multi-channel digital step attenuator (DSA) architecture. One embodiment includes an array comprising N channels of B selectable attenuator cells series-connected. The overall impedance of a multi-channel DSA is a function of the parallel impedances of the N channels, and transition levels are reduced by 1/N since the transient effect of switching any one attenuator cell in or out of circuit in one channel is mitigated by all other in-circuit attenuator cells in the parallel channels. The multi-channel DSA architecture enables a great design flexibility, and allows a designer to vary one or more of at least the following design parameters: the number of attenuator cells B per channel; the number N of channels per DSA; the bit weighting of each attenuator cell per channel; the maximum attenuation per channel; and the characteristic impedance Zon of each channel.

Abstract: A programmable RF attenuator having a first connection node and a second connection node is disclosed. The programmable RF attenuator provides RF attenuation between the first connection node and the second connection node based on at least a first attenuation control signal. The programmable RF attenuator includes a first RF attenuator circuit and a first reactance compensation circuit, such that the first RF attenuator circuit includes a first shunt transistor element and a first shunt resistive element, which is coupled to the first shunt transistor element. The first shunt transistor element receives the first attenuation control signal. The first reactance compensation circuit is coupled to the first RF attenuator circuit and at least partially compensates for reactive characteristics of the programmable RF attenuator that affect an attenuation flatness of the programmable RF attenuator.

Abstract: A power amplifier module includes a transistor and transistor control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to control the transistor in a stand-by mode of operation.

Abstract: Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.

Abstract: An attenuator includes a first high frequency signal input-output terminal and a second high frequency signal input-output terminal, a switch circuit, a plurality of resistors, and a variable capacitor. The plurality of resistors are respectively connected to the first high frequency signal input-output terminal while the resistors being parallel to each other. The switch circuit includes a plurality of selection target terminals respectively connected to the resistors and a shared terminal to which the plurality of selection target terminals are selectively connected and which is connected to the second high frequency signal input-output terminal. The variable capacitor is connected to one of the resistors in series and is so constituted as to have not a diode structure.

Abstract: Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (RON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.

Abstract: A programmable voltage variable attenuator (VVA) that enables selection among multiple analog, continuous attenuation ranges. Some embodiments include a dual-mode interface to enable digitally programming a DAC and provide the analog output to control the attenuation level of the VVA, or alternatively apply an externally provided analog voltage to directly control the VVA attenuation level. A VVA may be used in conjunction with a digital step attenuator (DSA). Some embodiments include circuitry for changing the VVA reference impedance. The attenuator architecture of the VVA includes one or more variable resistance shunt elements and/or series elements which may be a resistor and FET circuit controlled by a provided variable analog voltage. The multiple resistance element architecture may be implemented with stacked FET devices. Embodiments for the VVA may be based, for example, on T-type, Bridged-T type, Pi-type, L-pad type, reflection type, or balanced coupler type attenuators.

Abstract: A high frequency switch includes a first signal transferring unit configured to transfer a high frequency signal from a first port to a common port, and a second signal transferring unit configured to transfer the high frequency signal from the common port to a second port. The high frequency switch also includes an electrostatic discharge (ESD) protecting unit including a protective transistor positioned between the common port and a ground and a diode element positioned between a control terminal of the protective transistor and the first port.

Abstract: pHEMT-based circuits and methods of improving the linearity thereof. One example pHEMT circuit includes a pHEMT connected between an input terminal and a load and a non-linear resistance connected to the pHEMT. The pHEMT produces a first harmonic signal at the load responsive to being driven by an input signal of a fundamental frequency received at the input terminal, the first harmonic signal having a first phase. The non-linear resistance has a resistance selected to produce a second harmonic signal at the load having a second phase opposite to the first phase. Methods can include determining a first amplitude and a first phase of a first harmonic signal produced at the load by a pHEMT in an ON state, and tuning the non-linear resistance to produce at the load a second harmonic signal having a second amplitude and a second phase that minimizes a net harmonic signal at the load.

Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.

Abstract: Digital step attenuator (DSA) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (IC) die (or “chip”), and provide flexibility of design for various applications. Embodiments utilize one or more architectural features and/or design techniques to achieve such characteristics, including reduced resistor and FET switch sizes, reduced series stack sizes, unidirectional input power configurations, capacitor compensation to match bandwidth characteristics, activating low-power thermometer-weighted attenuator cells only after activating higher power thermometer-weighted attenuator cells, and reducing signal transients (glitches) using a thermometer-weighted configuration of attenuator cells.

Abstract: A system and method for an active Q-switched fiber laser cavity may include a pump source for emitting a laser beam at a wavelength along an optical path including an active optical medium. A modulation device may be configured to introduce tunable losses into the optical path. The tunable losses may be achieved through modulation of the transmissivity of an optical element within the optical path, the modulation of said optical element being performed over (i) a first period of time in which a cavity Q curve increases from a first percentage value to a second percentage value of a maximum Q value and (ii) a second period of time in which the cavity Q curve increases from a third percentage value to a fourth percentage value of the maximum Q value. The cavity Q curve may non-linearly and smoothly transition between (i) the first and second percentage values and (ii) the third and fourth percentage values.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

Abstract: A radio-frequency switch includes a series field-effect transistor, a shunt field-effect transistor having a gate node, and shunt arm control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to the gate node of the shunt field-effect transistor when the radio-frequency switch is in a stand-by mode of operation.

Abstract: A power amplifier module includes a first bipolar transistor configured to amplify a radio frequency signal and output an amplified signal and a second bipolar transistor. A base of the second bipolar transistor is supplied with a control voltage for controlling attenuation of the radio frequency signal, and a collector the second bipolar transistor is supplied with a source voltage. The power amplifier module also includes a first resistor, where one end of the first resistor is connected to a supply path of the radio frequency signal to the first bipolar transistor, and a capacitor, where one end of the capacitor is connected to the other end of the first resistor and the other end of the capacitor is connected to the collector of the second bipolar transistor.

Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.

Abstract: This disclosure relates to radio frequency (RF) front end circuitry used to route RF signals. In one embodiment, the RF front end circuitry has a filter circuit and a switch device. The switch device includes a common port, an RF port, and switchable path connected in series between the common port and the RF port. The switch device is configured to present approximately the filter capacitance of the filter circuit at the common port when the switchable path is closed. However, when the switchable path is open, the switch device is configured to present a device capacitance at the common port that is approximately equal to the filter capacitance of the filter circuit. In this manner, if the common port is connected to an antenna, the capacitance seen by the antenna from the common port remains substantially unchanged regardless of which of the switchable path is opened or closed.

Abstract: In accordance with an embodiment, a radio frequency (RF) switching circuit includes a plurality of series connected RF switch cells having a load path and a control node, and a switch driver coupled to the control node. Each of the plurality of series connected RF switch cells includes a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the control node. The switch driver includes a variable output impedance that varies with a voltage of the control node.

Abstract: A repeater including an analog attenuator configured to attenuate an analog signal in response to a first control signal; an analog to digital converter (ADC) configured to convert the attenuated analog signal into a digital signal; a digital attenuator configured to attenuate the digital signal in response to a second control signal; and an attenuation controller configured to calculate average power and peak power of the attenuated digital signal, determine an attenuation value for each value of the calculated average power and peak power, and generate at least one of the first and second control signals based on the determined attenuation values.

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.