Abstract: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Abstract: An IO driver circuit incorporates an output stage control circuit that selectively configures an output stage for the IO driver circuit to operate as a thevenin termination whenever the IO driver circuit is receiving a signal from an input/output node to which the IO driver circuit is coupled. The output stage may include a plurality of branches, with each branch having a pull-up device and a pull-down device, and the output stage control circuit selectively activates the pull-up devices in a first subset of branches in the output stage while concurrently activating the pull-down devices in a second subset of branches, as well as while leaving the pull-up devices in the second subset of branches and the pull-down devices in the first subset of branches deactivated.

Abstract: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

Abstract: In the existing technique in which the attenuation characteristic of an attenuator is adjusted by a voltage value, there are problems that a scale of a circuit of the attenuator increases because a new circuit for supplying voltage such as a step-down circuit becomes necessary, and that a thermal noise and a shot noise are mixed in an output signal of the attenuator. To solve the above-mentioned problems, provided is an attenuator comprising a T-type two terminal pair network including first and second circuits connected in series, and a third circuit connected in shunt between these first and second circuits. A shunt capacitor is connected between the first and second circuits independent from the third circuit.

Abstract: Provided is a digital attenuation apparatus having ultra broadband and excellent attenuation characteristics. The digital attenuation apparatus includes an input port, an output port, a first transmission line, a second transmission line, a first switching device, a third transmission line, a first resistive element, a second resistive element, a fourth transmission line, a second switching device, a fifth transmission line, and a third resistive element.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: There is provided a step attenuator having two Pi-type attenuators and one bridged-T type attenuator that share some resistors. The step attenuator is used to prevent a reduction in frequency range caused by use of MOS transistors and reduce attenuation of signal power and frequency band by the MOS transistors, thereby obtaining a low attenuation value and reducing input and output mismatch.

Abstract: A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit includes a first current source circuit for supplying a first current through a reference resistor. A second current source circuit supplies a second current through the first variable resistor. In operational amplifier has a first input coupled to a first conductor connecting the first current source to the reference resistor, a second input coupled to a second conductor connecting the current source to the first variable resistor, and an output applying the first resistance control signal to a control terminal of the first variable resistor, to force the resistance of the first variable resistor to be equal to a resistance of the reference resistor. The resistance of a second variable resistor of an attenuator is controlled in response to the resistance control signal.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit comprises an input node to receive an input signal to be attenuated, an output node to output an attenuated signal, a reference loss path between the input node and the output node, and an attenuation path between the input node and the output node. The reference loss path comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path and an effective phase length of the attenuation path may be equalized to provide a constant phase when the digital attenuator circuit is switched between states. Other embodiments are described and claimed.

Abstract: A data output driver that reduces signal skew includes a data multiplexer which reduces a load of a path through which a pull-up/pull-down control signal is generated by a logic-combination of a data signal. It also decreases the number of bits of a pull-up/pull-down resistance-adjusting code signal, and outputs a data signal in response to high impedance information. Furthermore, a path of an output circuit is simplified through which a pull-up/pull-down control is generated in response to the data signal output from the data multiplexer.

Abstract: There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.

Abstract: In an electronic high-frequency switch, comprising a field-effect transistor as the switching element, the size of the gate voltage may be switched between at least two values (?5.5 V and ?8 V), according to the desired linearity or switching speed. The switching device for the gate voltage is preferably coupled to a correction device in which different correcting values for the different gate voltage values corresponding to different correcting values for transmission or reflection by the high frequency switch are stored.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: A linearizer includes fifth diodes, a third resistor, sixth diodes, and a first npn heterojunction bipolar transistor. When a low-level voltage is applied to first and fourth control voltage terminals and a high-level voltage is applied to second and third control voltage terminals, a low-level voltage is applied to a fifth control voltage terminal, and when a high-level voltage is applied to the first and fourth control voltage terminals and a low-level voltage is applied to the second and third control voltage terminals, a high-level voltage is applied to the fifth control voltage terminal.

Abstract: An attenuator includes a first diode, a first control voltage terminal, a second diode, a first resistance, a second resistance, a third diode, a fourth diode, a fifth capacitance, a second control voltage terminal, a third control voltage terminal, a fourth control voltage terminal, and a linearizer provided between an input terminal and the anode of the first diode. The linearizer linearizes a signal input to the input terminal only when low level voltages are applied to the first and fourth control voltage terminals at the same time that high level voltages are applied to the second and third control voltage terminals.

Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

Abstract: A process independent voltage controlled logarithmic attenuator has an attenuator control stage block having a first input coupled to a controlled input and a second input coupled to an offset generator. An attenuator transistor is coupled to the attenuator controlled stage block. An output of the attenuator controlled stage block is both slope and maximum voltage definable for a process independent design.

Abstract: An attenuator circuit (10) having two or more branch circuits (12a to 12e) has inputs (14a to 14e) for the branch circuits (12a to 12e) being connected essentially in parallel arrangement to an input port (20) for the attenuator circuit (10). Each branch circuit (12a to 12e) includes one or more bipolar transistors (32a to 32e) having a collector element receiving a signal from a power supply (24) through at least one RF positive-intrinsic-negative (PIN) diode (50a-50d) that a control circuit (24) is controlling. At least one resistive element (16a) couples an input (14b) of a second (12b) of the plurality of branch circuits (12a to 12e) from the input port (20) to the branch circuits (12a to 12e). Thus, each branch (12a to 12e) of the attenuator circuit (10) draws current from a low voltage power supply (24) while still providing for sequential biasing of successive branches and linearization of overall control characteristics.

Abstract: Described are controllable termination impedances that may be adjusted collectively by a combination of digital and analog signals. Each adjustable impedance, responsive to the digital signals, establishes a gross termination resistance for one of a plurality of communication channels by enabling one or more of a plurality of parallel-coupled impedance legs. Each leg includes at least one transistor for controlling the impedance of the leg over a continuous range. An analog compensation voltage is level shifted and the resulting level-shifted signal is applied to the control terminals of the transistors of the selected impedance legs. The compensation voltage, and consequently the level-shifted signal, varies with supply-voltage and temperature fluctuations in a manner that causes the collective impedance of the selected legs for each channel to remain stable despite the fluctuations.

Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: Disclosed is a circuit to provide protection from an over voltage signal. The circuit protects against load dumps or positive transients applied to any electronic unit. The circuit isolates the protected circuitry from the transient voltage by two ways. The circuit limits the current flow and clamping the voltage using a small package zener diode. Additionally, the circuit causes a specific voltage drop between the applied transient and the protected circuit.

Abstract: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance and are controllable by a plurality of control signals different from one another and configured in such a way as to obtain a total impedance between said first and second terminals that is substantially variable in a continuous manner.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: Embodiments of the present invention include wideband attenuator circuits and methods. In one embodiment the present invention includes a first divider circuit coupled in series with two or more second divider circuits. The divider circuits include resistance and capacitance values that may be set according to particular relationships. In one embodiment, a wideband attenuator may include capacitors that are selectively coupled to each output node.

Abstract: A versatile attenuator. The versatile attenuator includes a first mechanism for receiving an input signal. A second mechanism measures the input signal and provides a signal-level indication in response thereto. A third mechanism selectively attenuates the input signal when the signal-level indication surpasses a predetermined threshold and provides an attenuated signal in response thereto. In a more specific embodiment, the third mechanism further provides attenuation information. An additional mechanism then employs the attenuation information and a computer to selectively adjust an output signal of a circuit connected between the computer and the third mechanism to accommodate effects that attenuation of the input signal by the third mechanism has on the output signal.

Abstract: An integrated step attenuator (“ISA”) monolithically integrated on a single chip for adjusting an input signal. The ISA may include a step attenuation network (“SAN”) that may include at least one switchable attenuation section, and at least one electronically switchable trimming network (“ESTN”). The SAN may be configured to adjust the input signal responsive to the state of a switch that bridges the attenuation sections of the SAN, and the ESTN may be configured to adjust the input signal responsive to the state of a switch in signal communication with one or more shunt resistors in the ESTN.

Abstract: A high-frequency switch circuit has a plurality of high-frequency switches for passing and blocking a high-frequency signal between an input terminal and an output terminal depending on a control potential applied as a control signal, a high-frequency detecting terminal for detecting high-frequency signal passing through the high-frequency switch which is in ON-state, and a voltage boosting circuit for generating a potential for increasing the control potential applied to the high-frequency switch which is in ON-state in order to increase difference between the control potential applied to the high-frequency switch which is in an ON-state and the control potential applied to the high-frequency switch which is in an OFF-state, depending on an intensity or amplitude of the detected high-frequency signal.

Abstract: A variable attenuation circuit includes an attenuation circuit which has a first semiconductor variable impedance element, and an attenuation control circuit of which the impedance is changed by a control voltage to be applied from the outside and which has a second semiconductor variable impedance element for controlling the impedance of the first semiconductor variable impedance element. The attenuation circuit and the attenuation control circuit are connected in cascade. Therefore, signals can be attenuated by the attenuation control circuit, in addition to the attenuation circuit.

Abstract: A circuit includes a first variable resistor having a resistance which is variable in response to a resistance control signal. A resistance control circuit includes a first current source circuit for supplying a first current through a reference resistor. A second current source circuit supplies a second current through the first variable resistor. In operational amplifier has a first input coupled to a first conductor connecting the first current source to the reference resistor, a second input coupled to a second conductor connecting the current source to the first variable resistor, and an output applying the first resistance control signal to a control terminal of the first variable resistor, to force the resistance of the first variable resistor to be equal to a resistance of the reference resistor. The resistance of a second variable resistor of an attenuator is controlled in response to the resistance control signal.

Abstract: An apparatus for controlling a voltage includes a reference voltage generator that generates reference voltage, and a bulk bias voltage generator that generates a bulk bias voltage using the reference voltage supplied by the reference voltage generator, and supplies the bulk bias voltage to the reference voltage generator to control the reference voltage.

Abstract: A signal processing system has a first, digitally controlled, gain element, a second, analogue controlled, gain element and a gain control unit configured to receive a gain request signal and to generate a first gain control signal to be input to the first gain element and a second gain control signal to be input to the second gain element such that the gain provided by the signal processing system corresponds to the gain request signal.

Abstract: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

Abstract: Embodiments of the present invention include wideband attenuator circuits and methods. In one embodiment the present invention includes a first divider circuit coupled in series with two or more second divider circuits. The divider circuits include resistance and capacitance values that may be set according to particular relationships. In one embodiment, a wideband attenuator may include capacitors that are selectively coupled to each output node.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: An electronic signal processing apparatus has a signal switch with a first and a second transistor of normally-on type, having main current channels coupled between an internal node and a switch input and output, respectively. A diode provides a switchable signal coupling between the internal node and ground. A switch control circuit has a control output that is DC coupled to the main current channel of the first and the second transistor via the internal node to control conduction of the main current channels. The diode is also DC-coupled to the internal node so that a DC potential of a terminal of the diode that controls whether the diode is on or off is determined by a potential of the internal node. The diode is preferably incorporated in the DC current path from the control output to the internal node, so that the diode is forward-biased when a control voltage that makes the main current channels non-conductive is applied.

Abstract: A circuit for a digitally operating linear-in-decibels attenuator circuit controlled using an analog control signal. The attenuator circuit includes a resistor ladder, digitally controlled switches, and a flash analog-to-digital converter. The resistive ladder includes resistances coupled in series between an input and output electrode. The resistive ladder also includes shunt resistances, each of which is coupled to a corresponding series resistance and to a corresponding digitally controlled switch that is controlled by a corresponding digital control signal. Each of the switches include a pole electrode coupled to a corresponding shunt resistance and to the input electrode, and a throw electrode coupled to the corresponding shunt resistance and to the common node for attenuating voltage from an input signal. The flash analog-to-digital converter is controlled by an analog control signal and outputs digital control signals in a thermometer code for controlling the digitally controlled switches.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: A passive terminator between a plurality of nodes includes a first voltage divider configured to passively set a differential voltage level between a first voltage level and a second voltage level. The first voltage divider has a Thevenin resistance and is electrically connectable to a first node. At least a second voltage divider is configured to passively set the differential voltage level between the first voltage level and the second voltage level. The second voltage divider has the Thevenin resistance and is electrically connectable to at least a second node. A transformer is electrically connected between the first voltage divider and the at least second voltage divider. The transformer has a reactance that is substantially greater than the Thevenin resistance of the first voltage divider and the at least second voltage divider.

Abstract: Analog control integrated FET based variable resistors and attenuators using the variable resistors having a wide range of monotonic and substantially linear attenuation with control voltage for use in circuits having AC signals of AC signal frequencies. The variable resistors comprise field effect devices (FETs) biased to operate in their linear region and having their bodies and gates coupled to a reference voltage and a control voltage, respectively, through impedances, typically resistors, having impedances that are higher than the impedances of parasitic capacitances at the signal frequencies. This allows the body and gate of each FET to vary in voltage with the signal to maintain the bias of the FETs in the presence of large signals. Various embodiments are disclosed.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: Described are controllable termination impedances that may be adjusted collectively by a combination of digital and analog signals. Each adjustable impedance, responsive to the digital signals, establishes a gross termination resistance for one of a plurality of communication channels by enabling one or more of a plurality of parallel-coupled impedance legs. Each leg includes at least one transistor for controlling the impedance of the leg over a continuous range. An analog compensation voltage is level shifted and the resulting level-shifted signal is applied to the control terminals of the transistors of the selected impedance legs. The compensation voltage, and consequently the level-shifted signal, varies with supply-voltage and temperature fluctuations in a manner that causes the collective impedance of the selected legs for each channel to remain stable despite the fluctuations.

Abstract: A variable attenuation device includes a resistive array having two or more input nodes, two or more output nodes, and two or more resistive devices for coupling the input nodes and the output nodes. A first switch has an input terminal and two or more selectable output terminals, such that the input terminal is configured to receive an input signal and the two or more selectable output terminals are coupled to the two or more input nodes of the resistive array. A second switch has two or more selectable input terminals and an output terminal, such that the output terminal is configured to provide an attenuated output signal and the two or more selectable input terminals are coupled to the two or more output nodes of the resistive array.

Abstract: Values of control signals 61, 62, 63, . . . , 6n, each inputted to an input terminal for operation control 6 of each of transistor elements 4 constituting a variable resistance portion 2, are controlled based upon an input signal 40 and offset signals 52, 53, . . . , 5n generated by an offset provision portion 3. Thus, a ratio of the maximum resistance value to the minimum resistance value can be made large, while using a limited power supply voltage range as a control range.