Abstract: Techniques are disclosed that allow for programmable attenuation using thermometer code steps. By thermometer coding the attenuator structure, monotonicity is guaranteed or otherwise greatly improved, which eliminates instability problems with automatic gain control loops and without the need for compensation or trimming. In addition, the thermometer coding technique also greatly reduces phase discontinuity between adjacent gain states.

Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.

Abstract: Provided is a semiconductor integrated circuit including a variable resistor circuit of the small layout area, which is free from an error in resistance caused by ON-state resistances of switch elements for trimming, and is also free from power supply voltage dependence and temperature dependence. The semiconductor integrated circuit including a variable resistor circuit includes: a resistor circuit including a plurality of series-connected resistors; a selection circuit including a plurality of switch elements for selecting a connected number of the plurality of series-connected resistors; and a control circuit for controlling ON-state resistances of the plurality of switch elements. The control circuit controls the ON-state resistances of the plurality of switch elements so as to obtain a predetermined ratio to a resistance of the plurality of series-connected resistors of the resistor circuit.

Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.

Abstract: Switches with improved biasing and having better isolation and reliability are described. In an exemplary design, a switch is implemented with a set of transistors, a set of resistors, and an additional resistor. The set of transistors is coupled in a stacked configuration, receives an input signal, and provides an output signal. The set of resistors is coupled to the gates of the set of transistors. The additional resistor is coupled to the set of resistors and receives a control signal for the set of transistors. The resistors reduce signal loss through parasitic capacitances of the transistors when they are turned on. The resistors also help split the signal swing of the input signal approximately evenly across the transistors when they are turned off, which may improve reliability of the transistors. The switch may be used in a switchplexer, a power amplifier (PA) module, etc.

Abstract: A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a second current at a second output terminal of the DAC, the first current being differential to the second current; a first circuit, coupled to the first output terminal of the DAC and to the second output terminal of the DAC, that generates a first voltage and a second voltage, the first voltage being non-linear with respect to the first current and the second voltage being non-linear with respect to the second current; and an attenuator coupled to the first circuit, and responsive to the first voltage and the second voltage to attenuate an input signal of the attenuator and to generate linear attenuation characteristics in decibels with respect to the first current and the second current.

Abstract: An attenuator circuit includes a high-frequency circuit path to produce an attenuated first signal; a low-frequency circuit path to produce an attenuated second signal, where the attenuated first signal has a higher frequency than the attenuated second signal; and a transistor that includes a control input. The control input is configured to receive the attenuated second signal to bias the transistor for passage of the attenuated first signal and the attenuated second signal.

Abstract: Variable attenuation systems having continuous input steering may be used to implement vector or quadrature modulators and vector multipliers. Discrete implementations of attenuators with continuous input steering may have two outputs which may be cross-connected to provide four-quadrant operation. A symmetrically driven center tap may provide improved zero-point accuracy.

Abstract: An RF attenuator circuit includes an anti-parallel PI structure having an input shunt arm comprising a single PIN diode, and an output shunt arm comprising a single PIN diode configured to have opposite polarity of the PIN diode of the input shunt arm.

Abstract: Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit (100) comprises an input node (102) to receive an input signal to be attenuated, an output node (104) to output an attenuated signal, a reference loss path (106) between the input node (102) and the output node (104), and an attenuation path (108) between the input node (102) and the output node (104). The reference loss path (106) comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path (108) comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit (100) is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path (106) and an effective phase length of the attenuation path (108) may be equalized to provide a constant phase when the digital attenuator circuit (100) is switched between states.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: In one embodiment, a temperature controlled attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. Furthermore, the temperature controlled attenuator includes a temperature controlled circuit that adjusts the attenuation level of the attenuation circuit in accordance to an operating temperature. In this manner, the attenuation level of the temperature controlled attenuator is temperature dependent.

Abstract: In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.

Abstract: In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator.

Abstract: An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.

Abstract: Disclosed herein is a digital attenuator, which can improve the variation in the pass phase of the digital attenuator because the difference between parasitic components caused by the turn-on and turn-off operations of the switching transistors of the digital attenuator causes the difference between the pass phases. The digital attenuator of the present invention includes an attenuation circuit unit configured to cause a variation in a pass phase due to a difference between parasitic components caused by turn-on and turn-off operations of switching transistors, and a phase correction unit connected in parallel with the attenuation circuit unit and provided with a series resistor and a low pass filter. Accordingly, variations in pass phase can be eliminated by connecting a low pass filter, connected to series resistors, in parallel with the series switch of an attenuation circuit unit, thus eliminating the influence of the parasitic components.

Abstract: An attenuator includes a T-type two terminal pair network including first and second terminals, first, second and third circuits, wherein the first terminal receives an input signal to be attenuated, wherein the first circuit is connected between the first and second terminals, wherein the second circuit is connected between the first circuit and the second terminal and is connected to the first circuit via a node, wherein the third circuit is connected to the node, and a capacitor connected to the node, wherein the capacitance value of the capacitor is variable.

Abstract: A voltage trimming circuit is provided. The voltage trimming circuit has an input stage, an up-trimming resistor ladder, a down-trimming resistor ladder and a control means. The input stage has a first input, a second input and an output, wherein the first output is to receive an input voltage, the second input is connected to a connection point and the output is to provide an output voltage based on a difference between the voltage of the first and the second input. The up-trimming resistor ladder is connected between the output of the input stage and the connection point and the down-trimming resistor ladder connected between a ground potential and the connection point. The control means controls the resistance of the up-trimming and the down-trimming resistor ladder to up-trim or down-trim the output voltage.

Abstract: Techniques are disclosed that allow for programmable attenuation using thermometer code steps. By thermometer coding the attenuator structure, monotonicity is guaranteed or otherwise greatly improved, which eliminates instability problems with automatic gain control loops and without the need for compensation or trimming. In addition, the thermometer coding technique also greatly reduces phase discontinuity between adjacent gain states.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current mirroring digital-to-analog voltage regulator. The voltage regulator operates by mirroring a reference current onto a selectable current level and controlling the selectable current level with a digital input to a plurality of switched CMOS devices connected in parallel. The switched CMOS devices generate the selectable current level responsive to the digital input and proportional to the reference current. The selectable current level is combined with an output of a voltage divider to generate a monitor signal. The monitor signal is compared to a reference voltage and the results of the comparison controls a charge pump to generate a pumped voltage. The pumped voltage is fed back to the voltage divider, which includes a feedback resistor and a reference resistor connected in series between the pumped voltage and ground.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A programmable gain circuit suitable for a programmable gain amplifier is described. In one design, the programmable gain circuit includes multiple attenuation circuits coupled in series. Each attenuation circuit operates in a first mode or a second mode, attenuates an input signal in the first mode, and passes the input signal in the second mode. The multiple attenuation circuits may provide the same or different amounts of attenuation. The multiple attenuation circuits may include binary decoded attenuation circuits and/or thermometer decoded attenuation circuits. In one design, each attenuation circuit includes a divider circuit and at least one switch. The switch(es) select the first mode or the second mode. The divider circuit attenuates an input signal in the first mode and passes the input signal in the second mode. The programmable gain circuit may have a predetermined input impedance and a predetermined output impedance for all gain settings.

Abstract: The present invention discloses a source follower attenuator circuit comprising a current source; an input transistor with a source connected to the current source and a drain connected to ground; a control transistor with a source connected to the current source and a drain connected to ground; wherein an attenuated output signal across the source and drain of the control transistor is controlled by transconductances, in an on-state, of the input transistor and of the control transistor respectively.

Abstract: A ?-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

Abstract: A semiconductor device, having a test circuit of a multivalued logic circuit without newly provision of an output terminal for a test signal, and with no increase in transmission delay in an output signal, includes an n-valued input terminal, and comparators that operate at different threshold voltages in response to input signals which have been input to the n-valued input terminal, respectively, and also includes an impedance control circuit that is connected to the n-valued input terminal and outputs of the comparators, respectively, and changes a combine resistance value in response to the output signals of the comparators to change a current flowing in the n-valued input terminal.

Abstract: A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on.

Abstract: A four-state digital attenuator for an RF signal includes a first external terminal adapted to receive a first control voltage; a second external terminal adapted to receive a second control voltage, and a third external terminal connected to a fixed supply voltage. The four-state digital attenuator receives no supply voltages other than the control voltages and the fixed supply voltage connected to the third external terminal. A plurality of series paths are provided from an RF input to an RF output, each of the series paths passing through a node. A plurality of shunt paths are provided from the node to the third external terminal. A driver selectively enables the series paths and shunt paths in response to the first and second control voltages to provide four attenuation levels for an RF signal from the RF input to the RF output.

Abstract: The present invention sets forth a controllable resistive circuit which comprises a transistor, a capacitor, a charging unit and a discharging unit. The transistor is capable of providing a variable resistance which is controlled to vary continuously and smoothly. The charging and discharging units are used to respectively charge and discharge the capacitor in different periods. As a result, the capacitor can provide a variable voltage which is controlled to vary continuously and smoothly to control the equivalent resistance of the transistor during the period the capacitor is discharging. Therefore, the controllable resistive circuit in accordance with the present invention is capable of being used in any kind of circuit which requires a variable resistance varied continuously and smoothly.

Abstract: Various embodiments are directed to providing constant phase digital attenuation. In one embodiment, a digital attenuator circuit (100) comprises an input node (102) to receive an input signal to be attenuated, an output node (104) to output an attenuated signal, a reference loss path (106) between the input node (102) and the output node (104), and an attenuation path (108) between the input node (102) and the output node (104). The reference loss path (106) comprises switching elements and matching circuitry to improve Voltage Standing Wave Ratio (VSWR), and the attenuation path (108) comprises switching elements and attenuating circuitry to attenuate the input signal when the digital attenuator circuit (100) is switched from a reference loss state to an attenuation state. An effective phase length of the reference loss path (106) and an effective phase length of the attenuation path (108) may be equalized to provide a constant phase when the digital attenuator circuit (100) is switched between states.

Abstract: A variable resistor formed on a silicon substrate, and changing a resistance value between an input terminal and an output terminal, includes a plurality of first resistors each having one end connected in common to the input terminal, and each having other end, a plurality of second resistors each having a resistance value smaller than the first resistors, and each having one end connected to the other end of any one of the first resistors, and a switch group interposed between the input terminal and the output terminal, and selecting one from the first resistors, and further, selecting at least one from the second resistors connected to the other end of the selected first resistor.

Abstract: The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.

Abstract: An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.

Abstract: A variable attenuator, used with high frequency, provides large variable attenuation per stage. The variable attenuator includes: a MOSFET having a gate, a drain, a source, and a body; an attenuation control circuit; and a temperature characteristics compensation circuit. The attenuation control circuit supplies a control voltage to the gate, the drain, and the source. The temperature characteristics compensation circuit supplies a temperature compensation voltage to the body. An input terminal and an output terminal are connected to the drain and the source of the MOSFET. The temperature characteristics compensation circuit, in accordance with an operating temperature of the MOSFET, controls a voltage to be supplied to the body and adjusts, based on a relation between a body voltage and a gate voltage, a resistance value of a current flowing between the input terminal and the output terminal.

Abstract: A level conversion circuit according to the present invention comprises: a first transistor having a gate thereof grounded, for inputting the input voltage to a source thereof and outputting an output voltage from a drain thereof; a second transistor having a drain thereof to which a power supply voltage is applied, for inputting the output voltage outputted from the drain of the first transistor to a gate thereof and outputting, from a source thereof, the output voltage determined by the power supply voltage; a level shift circuit for inputting the output voltage outputted from the source of the second transistor to an input end thereof and outputting, from an output end thereof, a voltage whose level is shifted by a predetermined amount; and a resistance inserted between the output end of the level shift circuit and a ground. Thus, it becomes possible to reduce a current Ii flowing to the gate of the first transistor to a level close to zero.

Abstract: An integrated switching device, such as an RF attenuator, can be controlled to be in various states according to control bits of a control signal. The integrated switching device can be gradually transitioned from one state to another by staggering the timing of changing the control bits. Latch-up problems in the integrated switching device can thereby be reduced or prevented.

Abstract: An attenuator includes one or more series attenuation branches including one or more series field effect transistors (FETs) each having a gate; one or more shunt attenuation branches including one or more shunt FETs each having a gate; and a bias control FET. The bias control FET receives at its gate a first bias control signal and in response thereto produces at one of its drain and source terminals a second bias control signal. Either the first bias control signal is coupled to the gates of one or more series FETs, and the second bias control signal is coupled to the gates of the one or more shunt FETs; or the first bias control signal is coupled to the gates of the one or more shunt FETs, and the second bias control signal is coupled to the gates of the one or more series FETs.

Abstract: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

Abstract: An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.

Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

Abstract: Operations as a variable resistor are favorably realized even when a drain-source voltage of a variable MOS resistor and that of a reference MOS resistor are not the same. A gate voltage of the variable MOS resistor is controlled with reference to a gate voltage which is controlled such that a voltage generated in the reference MOS resistor is controlled to be the same as a reference voltage. A resistor is connected in parallel with the reference MOS resistor between the drain and source thereof, the resistor including a pair of resistors having the same resistance connected in series. Half of a drain-source voltage of the reference MOS resistor is detected at an intermediate point of the pair of resistors. The gate voltage of the variable resistor is obtained by subtracting one-half of the drain-source voltage from the gate voltage of the reference MOS resistor.

Abstract: An apparatus for setting an attenuation of an attenuator includes a control transistor, which includes a drain connected to a gate of a shunt transistor of the attenuator. A channel resistance of the shunt transistor corresponds to a current density of the control transistor, and the channel resistance of the shunt transistor determines the attenuation of the attenuator. The current density of the control transistor is based at least in part on a control voltage input to the apparatus.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: An attenuator system includes a first adjustable impedance component on a first current path between a input component and a output component, and a second adjustable impedance component between the first current path and ground, wherein each of the first and second adjustable impedance components include a plurality of selectable, discrete legs, each leg having an impedance.

Abstract: A number of voltage-controlled resistance cells, each formed by a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance, are employed to form a voltage-controlled resistance structure. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.