By Feedback Limiting-clamping Patents (Class 327/312)
  • Patent number: 11005472
    Abstract: In accordance with an embodiment, a method includes operating a transistor device by a drive circuit in one of a first operating mode and a second operating mode based on an operating mode signal received by the drive circuit. Operating the transistor device in each of the first operating mode and the second operating mode includes switching on the transistor device based on a drive signal received by the drive circuit; monitoring at least one operating parameter of the transistor device; and switching off the transistor device independent of the drive signal when the at least one operating parameter reaches a respective predefined off-threshold. Switching on the transistor device in the second operating mode includes switching on the transistor with a second slew rate that is smaller than a first slew rate in the first operating mode.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 11, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Robert Illing, Christian Djelassi-Tscheck
  • Patent number: 10998839
    Abstract: A system and a method for driving a motor to rotate at a high speed are provided. The system includes a lookup table, a command detector, a pattern selector and a motor driver. The lookup table module is configured to store a reference waveform pattern and a modulated waveform pattern. An amplitude of the modulated waveform pattern is larger than an amplitude of the reference waveform pattern. The command detector is configured to receive a rotating speed command. The pattern selector is configured to receive the reference waveform pattern and the modulated waveform pattern, and select the reference waveform pattern or the modulated waveform pattern according to the rotating speed command. The motor driver is configured to output a driving signal to drive the motor according to the selected reference waveform pattern or modulated waveform pattern.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 4, 2021
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Ming-Jung Tsai
  • Patent number: 10958267
    Abstract: A power-on clear circuit includes a first inverter unit including a constant current transmission unit having one end supplied with a first power supply voltage, and a first transistor having a first terminal connected to a second line kept at a fixed potential, a second terminal connected to the other end of the constant current transmission unit, and a control terminal receiving application of a second power supply voltage which varies to follow the first power supply voltage; a second inverter unit that operates on the basis of the first power supply voltage, and to which a potential of a first node is input, the first node is connected between the other end of the constant current transmission unit and the first terminal of the first transistor; and a signal outputting unit that outputs a power-on clear signal in accordance with an output of the second inverter unit.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Seiichiro Sasaki
  • Patent number: 10693447
    Abstract: A comparator circuit includes: a comparator, coupled between a power voltage and a ground voltage, configured to perform a comparison according to a set of input signals to generate a comparison signal; a current source; and positive feedback circuits. The comparator circuit includes a set of input terminals and sets of transistors respectively coupled between a power voltage and a node or a ground voltage. The positive feedback circuits perform positive feedback operations on the node to generate instant currents on the node, to make the comparator switch the comparison signal in response to transition of the set of input signals in real time. Any of the positive feedback circuits includes: a first switch, configured to enable or disable said any positive feedback circuit in response to transition of the comparison signal; and a set of transistors, configured to generate a second current corresponding to the first current.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 23, 2020
    Assignee: Artery Technology Co., Ltd.
    Inventors: Baotian Hao, Weitie Wang, Chao Li
  • Patent number: 10614627
    Abstract: Disclosed are techniques that use mixed reality, e.g., augmented reality and virtual reality technologies to improve analysis of security situations. The techniques allow a guard (or other user in a facility) to observe persons in a facility and determine merely by looking at such persons through a mixed reality device whether those persons are authorized to be in the facility or not, irrespective of whether those persons are required or not required to publically display some credentials, such as a badge or the like.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 7, 2020
    Assignee: TYCO FIRE & SECURITY GMBH
    Inventors: Robert B. Locke, Paul B. Rasband, Rain Cui, Steve Schattmaier, Richard Campero
  • Patent number: 10571556
    Abstract: A device for detecting frequency modulated continuous wave radar includes an antenna connected to a bandpass filter. The antenna is configured to receive frequency modulated continuous wave (FMCW) pulses within a predetermined frequency range. A frequency mixer is connected to the bandpass filter and a synthesizer and is configured to mix a signal from the synthesizer with an output of the bandpass filter to produce basebanded data. A high-pass filter is configured to isolate short pulses pertaining to the basebanded data, and a low-pass filter is configured to isolate long pulses pertaining to the basebanded data. A microprocessor is configured to set thresholds for comparison with the outputs of the high-pass filter and the low-pass filter.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 25, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Gregory Knowles Fleizach, Barry Hunt
  • Patent number: 10498281
    Abstract: A motor control system includes a motor, a driving module and a control module. A first coil is electrically connected to a first node where a first control signal is provided, a second coil is electrically connected to a second node where a second control signal is provided, and a third coil is electrically connected to a third node where a third control signal is provided. An constant value of the first control signal is not zero, and a lower signal voltage limit of the first control signal is larger than or equal to zero.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 3, 2019
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Ming-Jung Tsai, Li-Wei Chen
  • Patent number: 10277106
    Abstract: A control circuit 2a for a switching power supply apparatus includes a comparator COMPa for comparing a voltage corresponding to a current flowing through a switching element PT1 with a voltage to be compared therewith, and outputting a comparison signal corresponding to a result of the comparison. To the comparator, a blanking pulse signal is also input. Here, the blanking pulse signal indicates whether or not it is currently in a predetermined period that is set for ensuring that the switching element is not turned off for the predetermined period after the switching element has been turned on. When the blanking pulse signal indicates that it is currently in the predetermined period, the comparison signal is set to low level independently of the voltage corresponding to the current and the voltage to be compared therewith.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenji Nakagomi
  • Patent number: 10147678
    Abstract: In a trimming device, a counter circuit generates n-bit setting data for n-bit trimming data used to trim the trimmed circuit. A trimming data generation circuit includes trimming elements whose conductive parts are blown when an electrical signal flows therein, pull-up resistors connected to high potential sides of the trimming elements, switches connected to the high potential sides of the trimming elements, and buffers. The trimming data generation circuit switches the switches in accordance with a level of the setting data, and generates the trimming data that is inputted to the trimmed circuit, via the buffers, from nodes at which the pull-up resistors and the trimming elements are connected to each other.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motomitsu Iwamoto
  • Patent number: 10044389
    Abstract: There is described a contactless communication device. The device comprises (a) a receiver unit (110, 610) having an antenna input (RXn, Vmid, RXp) for connecting to an antenna, the receiver unit (110, 610) being adapted to couple with a transmitting device and to receive an RF signal transmitted by the transmitting device, the receiver unit (110, 610) being further adapted to determine a point of time relating to a position of data within the RF signal, (b) a comparator (120) adapted to generate a comparator output signal (agc_comp) which is indicative of a relation between a voltage at the antenna input (RXn, Vmid, RXp) of the receiver unit (110, 610) and a reference voltage (Vref), and (c) a voltage regulation circuit coupled to the comparator (120) and to the antenna input (RXn, Vmid, RXp) of the receiver unit (110, 610), the voltage regulation circuit being adapted to repetitively regulate the voltage at the antenna input (RXn, Vmid, RXp) based on the comparator output signal (agc_comp).
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: August 7, 2018
    Assignee: NXP B.V.
    Inventors: Erich Merlin, Helmut Kranabenter, Stefan Mendel, Michael Pieber
  • Patent number: 9979388
    Abstract: The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 22, 2018
    Assignee: NXP USA, INC.
    Inventor: Youri Volokhine
  • Patent number: 9966909
    Abstract: In accordance with an embodiment, an amplification circuit includes an amplifier connected to a filter, wherein the amplifier has an input and an output and the filter has an input connected to the output of the amplifier. The amplification circuit includes a comparator that has an input connected to the output of the filter and an input coupled for receiving a reference voltage. The output of the comparator is connected to the input of the amplification circuit. In accordance with another embodiment, a method for generating an output signal is provided that includes generating an amplified signal by amplifying a signal that has an input portion and a feedback portion. A comparison signal is generated in response to comparing the signal with a reference signal and the comparison signal is used to set the output voltage to be substantially equal to the reference voltage.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 8, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Takashi Tokano
  • Patent number: 9628028
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
  • Patent number: 9378836
    Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Kilker, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 9368958
    Abstract: A circuit for protecting a transistor is disclosed. The circuit includes a temperature sensing device coupled to the transistor and a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage. A temperature controller coupled to the temperature sensing device and the tunable clamping circuit is also included. The temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: June 14, 2016
    Assignee: NXP B.V.
    Inventors: Alessandro Ferrara, Luc van Dijk, Peter Gerard Steeneken
  • Patent number: 9324704
    Abstract: A circuit comprises a plurality of electronic components integrated on a substrate, and a trim arrangement arranged to provide trim data to a respective electronic component of the plurality of electronic components. The electronic components are programmable such that the electronic components are enabled to be assigned desired properties. The trim arrangement comprises a first trim data source providing a first trim data set represented by a first number of bits, and at least one second trim data source providing a second trim data set representing an offset from the first trim data set. The second trim data set is represented by a second number of bits. The second number is less than the first number. At least one of the plurality of electronic components is provided with a trim data set formed from the first and second trim data sets such that the at least one of the plurality of electronic components is enabled to adjust its properties based on the trim data set.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 26, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Leif Klingström
  • Patent number: 8928388
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Patent number: 8890599
    Abstract: A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ming Xiao, Jian Wang
  • Patent number: 8884678
    Abstract: A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. The power line carrier communication reception circuit may include an amplifier which is connected to a power line and amplifies a received signal to be superimposed on the power line; two capacitors which are connected in series between both power sources of the amplifier; and a clipper circuit which connects connection points of these capacitors to the power line and limits the received signal in a predetermined range of a reference voltage between the capacitors, and in which the amplifier compares the signal limited by the clipper circuit and the reference voltage and amplifies the signal.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 11, 2014
    Assignees: RiB Laboratory, Inc., Honda Motor Co., Ltd.
    Inventors: Setsuro Mori, Shohei Terada, Motoki Kono
  • Patent number: 8836404
    Abstract: In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: September 16, 2014
    Assignee: Vishay-Siliconix
    Inventor: Trang Vu
  • Patent number: 8803563
    Abstract: Disclosed are driving control methods and circuits for quasi-resonant control of a main power switch of a switching power supply. In one embodiment, a driving control circuit can include: (i) a clamp circuit coupled to a gate of the main power switch, where the clamp circuit is configured to clamp a voltage of the gate to a clamping voltage that is greater than a threshold voltage of the main power switch; (ii) a valley voltage detection circuit configured to activate a valley control signal when a drain-source voltage of the main power switch is at a resonance valley level; and (iii) a source voltage control circuit configured to reduce a voltage of a source of the main power switch to turn on the main power switch in response to the valley control signal being activated.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 12, 2014
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Jian Deng, Chen Zhao, Qiukai Huang
  • Publication number: 20140210540
    Abstract: A power line carrier communication reception circuit which can precisely receive a signal to be superimposed at such a signal level that leakage of an electromagnetic wave does not cause a problem while employing a simplified configuration is provided. The power line carrier communication reception circuit may include an amplifier which is connected to a power line and amplifies a received signal to be superimposed on the power line; two capacitors which are connected in series between both power sources of the amplifier; and a clipper circuit which connects connection points of these capacitors to the power line and limits the received signal in a predetermined range of a reference voltage between the capacitors, and in which the amplifier compares the signal limited by the clipper circuit and the reference voltage and amplifies the signal.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 31, 2014
    Applicants: HONDA MOTOR CO., LTD., RiB Laboratory, Inc.
    Inventors: Setsuro MORI, Shohei TERADA, Motoki KONO
  • Patent number: 8766675
    Abstract: A circuit includes: a pull down circuit including a first PFET and a second PFET connected in series between a pad of a USB circuit and ground; and a pull up circuit including a first NFET and a second NFET connected in series between the pad and a supply voltage. The circuit includes: a third PFET connected to a gate of the first PFET and a gate of the second PFET; a third NFET connected to a gate of the first NFET and a gate of the second NFET; a fourth PFET connected to the first NFET and the second NFET; and a fourth NFET connected to the first PFET and the second PFET. A pad voltage has a nominal minimum and maximum. Each of the first PFET, the second PFET, the first NFET, and the second NFET has a nominal voltage less than the pad voltage nominal maximum.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 1, 2014
    Assignees: International Business Machines Corporation, VeriSilicon Holdings, Co. Ltd.
    Inventors: Daniel M. Dreps, Jian Guan, Yi Xiao, WuQuan Zhang
  • Publication number: 20140097881
    Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 10, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Brian Thomas Lynch, Joseph Maurice Khayat, Stefan Wlodzimierz Wiktor
  • Publication number: 20140062439
    Abstract: A switching power supply comprises a noise detecting circuit and a canceling signal generating circuit. The noise detecting circuit detects GND bounce noise developing on a ground line of the control circuit accompanying switching operation of a switching element. The canceling signal generating circuit generates a canceling signal corresponding to the GND bounce noise and in a reversed phase, and adds the canceling signal to the ground line when the noise detecting circuit detects the GND bounce noise. In an embodiment, the canceling signal generating circuit generates a canceling signal based on the current flowing through the switching element. In another embodiment, the canceling signal generating circuit generates a canceling signal of a pulse signal with a pulse height equal to a threshold level for detection determination of the GND bounce noise in the noise detecting circuit.
    Type: Application
    Filed: August 8, 2013
    Publication date: March 6, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Kenichi NISHIJIMA
  • Publication number: 20140028369
    Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 30, 2014
    Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
  • Patent number: 8629709
    Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: January 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoyuki Iraha, Tatsuhiko Maruyama
  • Patent number: 8610484
    Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Sudarshan Udayashankar, Jerry L. Doorenbos
  • Patent number: 8513983
    Abstract: A switch device comprised of a wide band gap semiconductor is provided. The switch device comprises a drain, a source, a gate and a gate voltage clamp circuit, which is connected between a signal terminal, to which a signal for driving the gate is input, and the gate through a series circuit of a capacitor and a resistance, and which comprises a diode and a voltage limiter circuit provided between the drain and the gate.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: August 20, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8466731
    Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: June 18, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nang Ping Tu, Chun Hao Liao
  • Patent number: 8390222
    Abstract: The present disclosure provides a brushless motor driving circuit capable of clamping an output voltage at a proper voltage, even when a power source voltage changes. Namely, a pre-driver circuit generates a voltage for driving a brushless motor from a source voltage by turning on/off first and second PMOS transistors and first and second NMOS transistors in an H bridge circuit of a drive voltage generating circuit, and applies the voltage to a coil of the brushless motor. A first clamp circuit turns on/off the first NMOS transistor on the ground side so that the output voltage at a first output terminal becomes equal to or lower than the source voltage. A second clamp circuit turns on/off the second NMOS transistor on the ground side so that output voltage at a second output terminal becomes equal to or lower than the source voltage.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: March 5, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Kunio Seki, Kazutaka Inoue, Hiroyuki Kikuta, Yuichi Ohkubo
  • Publication number: 20130028441
    Abstract: Disclosed are advances in the arts with novel and useful electronic circuitry with pop and click noise reduction. A load circuit is connected with a full or single-ended half-H bridge circuit and another circuit mechanism in a configuration by which a signal may be used to selectably bring the load circuit terminals to a selected voltage level when an externally applied signal is not present.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 31, 2013
    Inventors: Wayne T. Chen, Ross E. Teggatz, Brett Smith
  • Patent number: 8217821
    Abstract: A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 10, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Filippo David, Igino Padovani
  • Patent number: 7982522
    Abstract: An N-channel transistor is provided as a switch between a high potential power line and a low potential power line. A high-pass filter is constituted by a capacitor and a resistor. When a voltage between the high potential power line and the low potential power line is started to oscillate by a switching operation, the high-pass filter causes a high-pass component thereof to pass, thereby turning ON the N-channel transistor to reduce a ringing.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 19, 2011
    Assignee: Yamaha Corporation
    Inventors: Nobuaki Tsuji, Hirotaka Kawai
  • Patent number: 7944247
    Abstract: An operating circuit includes a differential amplifier stage, which has a first input node for receiving a first input signal of a differential input, a second input node for receiving a second input signal of the differential input, a first output node for outputting a first output signal of a differential output, and a second output node for outputting a second output signal of the differential output; an offset current stage coupled to the first output node and the second output node for inducing a first offset current at the first output node and a second offset current at the second output node; and a first clamping device coupled to the first output node for selectively clamping an output voltage at the first output node according to the first output signal at the first output node.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: May 17, 2011
    Assignee: Mediatek Inc.
    Inventors: Kun-Hsien Li, Chih-Pin Sun, Hao-Ping Hong, Yung-Yu Lin
  • Patent number: 7940107
    Abstract: An inrush voltage clamping circuit for an electronic device for clamping an inrush voltage induced by hot plugging is disclosed. The clamp circuit includes a buffer unit and a clamp unit. The buffer unit is coupled to an input power end for receiving an inrush current of the inrush voltage. The clamp unit is coupled to the input power end and the buffer unit for controlling the buffer unit to receive the inrush current according to an input voltage of the input power end.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: May 10, 2011
    Assignee: Anpec Electronics Corporation
    Inventors: Kun-Min Chen, Tzu-Cheng Teng, Ming-Jung Tsai, Ching-Sheng Li
  • Patent number: 7936202
    Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: May 3, 2011
    Assignee: Power Integrations, Inc.
    Inventor: Giao Minh Pham
  • Patent number: 7830196
    Abstract: When an insulated gate bipolar transistor turned on starts to transition to turn off, the insulated gate bipolar transistor has between the emitter and the collector a surge voltage caused in proportion to the magnitude of a current gradient provided when a current flowing through a coil in switching is interrupted and an electrode interconnect inductance internal to an inverter circuit. A MOS transistor is temporarily turned on within a period of time for which the insulated gate bipolar transistor turned on transitions to turn off. This can bypass a portion of the current to the MOS transistor. This can provide an alleviated apparent current gradient of the current and thus alleviate or prevent a surge voltage caused at the insulated gate bipolar transistor.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 9, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeshi Omaru
  • Patent number: 7800434
    Abstract: A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: September 21, 2010
    Assignee: Micrel, Inc.
    Inventors: Thomas S. Wong, Vincent Stueve
  • Patent number: 7733133
    Abstract: A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Yanagigawa, Masaki Kojima
  • Patent number: 7728888
    Abstract: A clamping circuit including: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from the A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from the potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from the potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from the D/A converter and an adjusting voltage outputted from the adjusting voltage generation circuit
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: June 1, 2010
    Assignee: Olympus Corporation
    Inventor: Makoto Ono
  • Publication number: 20100109741
    Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Applicant: Power Integrations, Inc.
    Inventor: Giao Minh Pham
  • Patent number: 7692468
    Abstract: An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: April 6, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: William F. Ellersick
  • Patent number: 7667518
    Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: February 23, 2010
    Assignee: Power Integrations, Inc.
    Inventor: Giao Minh Pham
  • Publication number: 20090267675
    Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.
    Type: Application
    Filed: April 2, 2009
    Publication date: October 29, 2009
    Applicant: Broadcom Corporation
    Inventor: Chun-Ying Chen
  • Patent number: 7579893
    Abstract: An NchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 25, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazuhiro Shimomura, Makoto Yamamoto
  • Patent number: 7528645
    Abstract: An apparatus, comprising a transistor having a source/drain node and a gate, and a circuit coupled between the source/drain node and the gate and configured to limit a voltage between the source/drain node and the gate to a clamping voltage such that the clamping voltage is reduced in response to a rising temperature of the transistor. Also, a method, comprising measuring a first temperature, measuring a second temperature, and reducing a clamped voltage between a source/drain node of a transistor and a gate of the transistor responsive to a difference between the first and second temperatures increasing.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: May 5, 2009
    Assignee: Infineon Technologies AG
    Inventors: Erich Scheikl, Heinz Zitta
  • Patent number: 7525366
    Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: April 28, 2009
    Assignee: Broadcom Corporation
    Inventor: Chun-Ying Chen
  • Patent number: 7471756
    Abstract: In a phase-locked loop (PLL), a phase detector receives a reference signal and a feedback oscillator signal, generates a phase-detect pulse having a first duration in response to one of the reference and feedback signals, and generates a phase-correction pulse having second, shorter duration in response to the phase-detect pulse. By shortening the phase-correction pulse, such a phase detector can reduce or eliminate the overcorrection period during which the phase-correction pulse is active after phase correction is achieved, and thus can reduce or eliminate the phase error that the overcorrection period may introduce into a PLL's oscillator signal.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: December 30, 2008
    Assignee: Intersil Americas Inc.
    Inventor: Mark William Dickmann
  • Patent number: 7436225
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second pads; an output transistor; and a current control circuit having first and second resistors, a control signal generation circuit, first and second switching circuits. The first or second resistor is disposed between the first or second pad and the output transistor. The control signal generation circuit generates a control signal to the output transistor based on a voltage of both ends of the first or second resistor. The first or second switching circuit is disposed between both ends of the first or second resistor and the control signal generation circuit. The first or second switching circuit is controlled to be in an on-state.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 14, 2008
    Assignee: Denso Corporation
    Inventors: Yoshinori Arashima, Shouichi Okuda