Abstract: A semiconductor device includes: a semiconductor substrate having first and second pads; an output transistor; and a current control circuit having first and second resistors, a control signal generation circuit, first and second switching circuits. The first or second resistor is disposed between the first or second pad and the output transistor. The control signal generation circuit generates a control signal to the output transistor based on a voltage of both ends of the first or second resistor. The first or second switching circuit is disposed between both ends of the first or second resistor and the control signal generation circuit. The first or second switching circuit is controlled to be in an on-state.

Abstract: A system including a single ended switching topology for high-speed bidirectional signaling includes a device coupled to a plurality of bidirectional signal paths. The device includes a plurality of voltage mode driver circuits, each coupled to a respective signal path. Each of the driver circuits may source a voltage when transmitting data and terminate a respective signal path to a ground reference when receiving data. The device also includes a shunt regulator circuit coupled to a voltage supply of the device. The shunt regulator may provide a current shunt from the voltage source to the ground reference in response to detecting a transition on the voltage supply in which the voltage increases above an average DC voltage.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: There is described a semiconductor Type Two phased locked loop filter having a passive capacitor part and a variable active resistor part, the variable active resistor part being integrated with the passive capacitor part. Integrating an active variable resistor will apply the same change to both poles and has no effect on the loop gain. The variable active resistor part is controlled by a resistor regulator circuit operating from a voltage that follows the type two phased locked loop voltage. The resistor regulator circuit is bootstrapped to the phased locked loop voltage using a voltage follower configured op-amp.

Abstract: An input stage includes a signal input (IN) for receiving an input signal s(t) and a digital input stage (15) designed for operation at a supply voltage (VDD). The input stage (15) includes CMOS transistors, which are sensitive to voltages across transistor nodes going beyond a voltage limit (Vmax) and an input (IINV). Voltage limiting circuitry (B) is arranged between the signal input (IN) and the input (IINV). The voltage limiting circuitry (B) includes an input switch (ns) controllable by the state of the input signal s(t), and limit voltages at the input (IINV) to the supply voltage (VDD). In addition, over-voltage protection (A) is provided between the signal input (IN) and the supply voltage (VDD). The circuitry for over-voltage protection (A) includes at least one active circuit element arranged so as to mimic part of a zener function.

Abstract: An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot.

Abstract: A gate drive integrated circuit for switching power transistors using an external controller includes a gate driving capability and low quiescent current and allows use of a bootstrap supply technique for providing the logic supply voltage. The gate driver integrated circuit detects power transistor desaturation, protecting a desaturated transistor from transient over voltages by smoothly turning off the desaturated transistor via a soft shutdown sequence. A fault control circuit of the gate driver integrated circuit manages protection of supply under-voltage and transistor desaturation and is capable of communicating with a plurality of gate driver integrated circuits in a multi-phase system using a dedicated local network.

Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from ?-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: An inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.

Abstract: An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

Abstract: A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first drive input for applying a first drive signal, and a first semiconductor switching element having a first load terminal connected to the first connecting terminal, a second load terminal connected to the second connecting terminal and a drive terminal coupled to the drive input. A voltage limiting circuit is provided and is connected between the first load terminal and the drive terminal of the first semiconductor switching element.

Abstract: In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.

Abstract: A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Abstract: An amplifier circuit includes a circuit input, and a circuit output. An inverter, including first and second MOS transistors is connected between first and second supply voltages, and has an inverter input connected to the circuit input, and an inverter output, which provides an inverter output current corresponding to a circuit input voltage. A first resistive element comprises a third MOS transistor and a fourth MOS transistor of opposite conductivity types, and each having their gate and drain terminals connected to the inverter output and the circuit output, and having their respective source terminals connected to respective ones of the first and second supply voltages. A second resistive element includes a fifth MOS transistor and a sixth MOS transistor of opposite conductivity types, and each having its drain-source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source.

Abstract: Circuits and methods for extending the input common mode voltage range of a JFET op-amp are provided. The circuits and methods consist of modifying the input stage of a JFET op-amp to include a BJT pair as the input differential pair and use a JFET pair as followers. Using the BJTs as the input differential pair enables the JFET followers to operate in the linear region of operation when the op-amp's input is approaching ground, thereby increasing the negative common mode voltage range. The positive common mode voltage range is increased by reducing the source current in the JFET pair and using a transistor pair as clamping transistors.

Abstract: An output buffer circuit includes first and second MOS transistors connected in series between a power supply and ground, a first pull up transistor coupled between the power supply and a gate of the first MOS transistor, a first pull down transistor coupled between ground and the gate of the first MOS transistor, a second pull up transistor coupled between the power supply and the gate of the second MOS transistor, a second pull down transistor coupled between ground and the gate of the second MOS transistor, a slew-rate control node, a third MOS transistor coupled between the power supply and the slew-rate control node, a fourth MOS transistor coupled between ground and the slew-rate control node, a first variable resistance provided between the first pull up and pull down transistors, and a second variable resistance provided between the second pull up and pull down transistors.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: Depletion mode pass transistor (38) accepts input voltage Vin and provides regulated output voltage Vout. The regulated output voltage is referenced to the threshold voltage of MOSFET (40) and is directly proportional to the ratio of resistors (50 and 52). MOSFET (58) provides enabling and disabling of voltage regulator (54). Multiple voltage regulators (FIG. 5) having multiple output potentials are realized on the same semiconductor die producing the same threshold potential for MOSFET's (40), whereby the output potentials are selectable using the ratio of resistors 50 and 52. Constant current source (56) reduces output voltage variation due to input voltage variation.

Abstract: A system for minimizing the effect of clock skew in a bit line write driver includes a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal. A method of minimizing the effect of clock skew in a bit line write driver includes outputting a first signal and a second signal from the bit line write driver; controlling the outputting of the second signal from the bit line write driver based on a feedback of the first signal; and controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected, respectively to the head nodes and the emitters of first and second upper drive transistors. The diodes increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium.

Abstract: An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock signal supplied from the first clock line, a second clock line formed on the insulating substrate to input a signal obtained from the clock buffer to a shift register serving as a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first clock line to remove electrostatic charge from the first clock line, and a second protection diode circuit connected to the second clock line to remove electrostatic charge from the second clock line.

Abstract: A delay circuit that is insensitive to variations in an input signal voltage level has a voltage clamp at its input terminal to fix the input voltage level so as to remove the sensitivity of the delay circuit to the variations in the input signal voltage level and the power supply voltage source. A voltage independent delay circuit is composed of a first inverter circuit, a voltage clamping circuit, a delay capacitor, and a second inverter circuit. The first inverter circuit has an input terminal and an output terminal. A first output signal at the output terminal is an inverse of an input signal at the input terminal. The voltage clamping circuit is connected between the output terminal and the input terminal of the first inverter circuit to fix a voltage swing of input signal to a first voltage level. The delay capacitor connected to the output terminal of the first inverter to establish a transition time of the first output signal.

Abstract: When PMOS transistors are successively turned off, the resistance between a PMOS transistor and a power supply VDD is changed, and the amplitude of a waveform at the junction between the last-mentioned PMOS transistor and an NMOS transistor is controlled based on the changed resistance. Thereafter, a waveform output unit outputs a waveform whose harmonic components are made smaller from the junction between the PMOS transistor and the NMOS transistor.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.

Abstract: An output buffer circuit is provided, which is capable of obtaining a large drive power when the level of an input signal changes, while allowing a through current to flow in suppressed amounts. A first P-channel MOS transistor and a first N-channel MOS transistor are connected in series with a power supply. The pair of transistors are exclusively switched on and off by an input signal such that the first and second switching elements are not simultaneously on or off, to deliver an output signal corresponding to the input signal, from a common junction between the first and second switching elements. A second P-channel MOS transistor is connected in parallel with the first P-channel MOS transistor as an auxiliary transistor. A second N-channel MOS transistor is connected in parallel with the first N-channel MOS transistor as an auxiliary transistor.

Abstract: A method and apparatus is disclosed for reducing ringing of a digital signal delivered over a transmission line. A clamping circuit implemented in accordance with one embodiment of the invention includes a delay circuit. The delay circuit receives an input signal delivered over a transmission line and delivers a second signal after a preselected delay. A driver circuit receives the second signal and the input signal and provides an enable signal to a transistor for a period of time corresponding to the preselected delay. The transistor is coupled between a supply voltage and the transmission line. An inverter having an input and an output is also included, with the input of the inverter electrically connected to the transmission line. An additional transistor is electrically coupled between the supply voltage and the transmission line.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A balanced transformer-less (BTL) power drive circuit comprises a push-pull type output transistor section connected with a main power supply PowVcc, and an input control section connected with an auxiliary power supply for providing the output transistor section with a control signal. The potential of the auxiliary power supply is selectively set equal to or above the supply potential of the main power supply, depending on the requirements for the dynamic range of the power chive circuit. In accord with the potential of the auxiliary power supply thus set, the output reference potential Vref is set to the medium of the dynamic range, thereby ensuring the linearity of the input-output characteristic of the drive circuit, irrespective of the selected level of the auxiliary power supply.

Abstract: In the current limiting circuit, which is provided with: the D/A converter 2A to output the voltage signal to supply the power source onto the load 11; reversal amplifier circuit to amplify the voltage signal; capacitor 10 to absorb the fluctuation of the power source supplied onto the load 11; operational amplifier 4B to set the amplification factor of the reversal amplifier circuit; transistor 5; and resistor 3E, the current detection circuit 7 detects the current value to be inputted into the load 11, and according to the detected current value, calculates the voltage at the current detection position, and the CPU 1 sets the predetermined voltage, the comparing circuit 8 compares the setting voltage value to the calculated voltage value, and according to the comparison result, by ON/OFF-controlling the switch 9, the setting of the amplification factor of the reversal amplifier is changed.

Abstract: An output buffer circuit is provided, which decreases a delay time of change of a digital output signal with respect to change of a digital input signal and which is capable of higher-speed switching operation. This output buffer circuit is comprised of a pair of a first p-channel MOSFET and a first n-channel MOSFET located in an output stage through which an output signal is derived; a first clamp circuit for clamping a gate voltage of the first p-channel MOSFET at a first clamp level for a first specific period, thereby increasing a rising rate of the output signal; and a second clamp circuit for clamping a gate voltage of the first n-channel MOSFET at a second clamp level for a second specific period, thereby increasing a falling rate of the output signal. A first resistor is connected to the first clamp circuit for suppressing a current flowing through the first clamp circuit. A second resistor is connected to the second clamp circuit for suppressing a current flowing through the second clamp circuit.

Abstract: A reference circuit contains a PTAT (Proportional To Absolute Temperature) core. In the PTAT core there is a difference between the currents densities flowing through a first and second transistor. This difference results in a difference in junction voltage in the first and second transistor. The currents are adjusted by a local feedback loop in proportion to one another until the difference in junction voltage equals a voltage drop across a resistor. According to the invention the currents to both transistors are supplied by current sources, and the currents are adjusted by deviating a fraction of the supplied current from the transistors. This makes it possible to reference all control voltages for the transistors and the local feedback loop to the same supply connection, which increases the stability and power supply rejection of the circuit.

Abstract: A deceleration circuit is operatively coupled to a first and second voltage to reduce noise on each of the voltage lines. For example, one voltage may be a supply voltage and the other voltage may be at a ground potential. The deceleration circuit may be coupled, for example, to each circuit that need not operate at a maximum or high operational speed within an integrated circuit that has other circuits that require high speed operation.

Abstract: An off-chip driver circuit having a set of input terminals and an output terminal, a pull-up transistor having a controllable path connected between a first power supply and the output terminal of the off-chip driver circuit, a pull-down transistor having a controllable path connected between a second power supply and the output terminal of the off-chip driver circuit, a first controllable path for applying a first voltage at one of the input terminals to a control terminal of the pull-up transistor, the first controllable path functioning in response to voltages at the output terminal below a first value, a second controllable path for applying a second voltage greater than the first voltage to the control terminal of the pull-up transistor, the second controllable path functioning in response to voltages at the output terminal above the first value.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A circuit for reducing the ground and power supply bounce of the output drivers in a group of I/O cells. A replica I/O cell is part of a delay locked loop which uses closed-loop feedback control to determine the magnitude of a bias current needed to cause the delay through the replica cell to be equal to a reference value. By forcing the delay through the replica cell to be equal to a desired reference value, the magnitude of bias current required to control the delay through each of the I/O cells in an I/O ring so that the delay approaches the reference value can be determined. As a result, by properly selecting the reference delay value, the magnitude of the bias current required to compensate for delay variations arising from multiple sources (e.g., PVT) can be determined. Since this reduces the rate of change of the current in the output drivers of the actual I/O cells, the induced voltage responsible for the ground and/or power supply bounce in those cells is reduced.

Abstract: The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Abstract: An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels is disclosed. The present invention uses various circuit techniques to ensure that no transistor in the input buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the input signal voltage may swing well beyond the tolerable voltage levels. This is accomplished without compromising the reliability of the input buffer circuit in detecting the logic levels of the input signal.

Abstract: An offset voltage correction circuit for an operational amplifier (1) includes an offset voltage varying device (16, 17, 20, 21-23) for varying an offset voltage in the operational amplifier (1) in response to an offset voltage control value. A comparing device (25) operates for comparing an output voltage from the operational amplifier (1) with a prescribed reference voltage. A control device (19, 300) operates for outputting the offset voltage control value to the offset voltage varying device, for changing the offset voltage control value, for storing, in response to a result of the comparing by the comparing device (25), a digital signal representative of the offset voltage control value at which the output voltage from the operational amplifier (1) and the prescribed reference voltage are equal, and for correcting the offset voltage in the operational amplifier (1) in response to the stored digital signal.

Abstract: Various methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions at an external terminal are disclosed. The present invention detects the level of the signal at the external terminal and adjusts the voltage at the gate terminals of the output transistors connecting to the external terminal in response thereto, such that oxide stress conditions are alleviated. In one embodiment, dynamic biasing techniques are developed by the present invention to ensure that the circuitry protecting the output devices is itself protected against voltage stress caused by overshoot and undershoot at the external terminal.

Abstract: A wideband level shift circuit (200) used with low voltage ECL or CML topologies includes a sub-Vbe voltage reference (201) whose output voltage is offset some fraction of a diode voltage drop below a supply voltage, where the fraction is held at a constant value as the diode voltage varies with temperature. A comparator circuit (203) is attached to the reference voltage circuit (201) as well as to a current sourcing transistor and differential buffer circuit (205). The comparator circuit (203) maintains the DC potential at the output of a current sourcing transistor so that the common-mode DC level of the output signal from a differential buffer is shifted down by a fraction of a diode drop from the common-mode DC level of a wideband AC input signal. The shift circuit (200) offers the advantages of a fraction of a diode DC voltage drop with little loss of AC signal bandwidth for circuits operating from low supply voltages.

Abstract: The present invention concerns a transmission circuit of an audio/video data bus that includes a clamp connected between first and second output terminals of the transmission circuit; biasing networks for respectively biasing the output terminals during one operational mode of the transmission circuit; and switched biasing networks for respectively biasing the output terminals during a second operational mode of the transmission circuit; the switched biasing networks being controlled by a digital input signal, wherein a circuit is provided for protecting the clamp from short circuit connections to the transmission circuits voltage supply rails.

Abstract: A clamping circuit (100) is provided for controlling an external switch, using a control signal, in response to monitoring a voltage at a first node. When the voltage at the first node exceeds a certain voltage, the clamping circuit (100) closes the external switch to complete a current path to reduce the voltage at the first node. The clamping circuit (100) includes a voltage divider circuit, a first device, a second device, a current mirror circuit, and a switch. The voltage divider circuit, which may be implemented using a resistor (30) and a resistor (32), is coupled between the first node and a fourth node and generates a divider voltage at a third node that is proportional to the voltage at the first node. The first device and the second device may be implemented using a first bipolar junction transistor (38) and a second bipolar junction transistor (40), respectively.

Abstract: A write driver, having a pair of head nodes for connection to a write head, includes two diodes connected respectively the head nodes and the emitters of first and second upper drive transistors. The diodes, which are preferably Schottky diodes, increase the voltage necessary to breakdown the emitter pn junctions of the upper drive transistors, thereby enabling a greater head swing voltage, higher switching rates, and ultimately closer spacing of data on a magnetic medium. Additionally, a preferred embodiment of the write driver includes two voltage clamps, each coupled between a respective head node and a first supply node, to limit the magnitude of voltage spikes resulting from self-inductance of the write head.

Abstract: A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S.sub.2 of a first CMOS inverter INV.sub.C1 and the node S.sub.1 at the gate of an MOS transistor PT.sub.3 for active pull-up. At the same time, a reference voltage V.sub.REF and a voltage level V.sub.OUT, which corresponds to the voltage level of the output line of the signal S.sub.OUT, are compared by a comparator CMP. When the voltage V.sub.OUT is lower than the reference voltage V.sub.REF, the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV.sub.C1 is sent to the gate of the transistor PT.sub.3 for active pull-up. The comparator CMP is installed so that when the voltage level V.sub.OUT is higher than the reference voltage V.sub.REF, the output of the first CMOS inverter INV.sub.C1 is prevented from reaching the gate of the transistor PT.sub.3 for active pull-up.

Abstract: In a buffering circuit, a CMOS inverter is connected between a node and a ground terminal. A source-follower-type MOS transistor is connected between a power supply terminal and the node, and a approximately definite voltage is applied to a gate of the source-follower-type MOS transistor. A MOS transistor is connected in parallel to the source-follower-type MOS transistor, and an inverted signal of an output signal of the CMOS inverter is applied to a gate of the MOS transistor.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: A low power current-to-frequency converter circuit provides an output frequency signal F.sub.OUT having a frequency that varies as a function of a low level analog input current signal. The analog input current signal is typically generated by an implantable sensor element, designed to sense a particular substance or parameter within body tissue or fluids to which the sensor is exposed, with the magnitude of the analog signal providing a measure of the sensed substance or parameter. Conversion of the low level analog current to the output frequency signal facilitates transmission of the data signal over a shared data bus and other digital processing of the data signal.

Abstract: A voltage-controlled transistor drive circuit includes a gate-voltage generating circuit for outputting on and off gate signal voltages in response to an input signal, switching a voltage-controlled transistor by applying the gate voltage to the gate of the voltage-controlled transistor; and a current limiting circuit limiting current flowing from the gate of the voltage-controlled transistor to the gate-voltage generating circuit when the gate-voltage generating circuit outputs an off gate signal voltage.

Abstract: A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback DC restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the DC restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the DC restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the DC restorer output signal in the absence of valid data transitions.