Abstract: An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prevents erroneous operation. After power is input, in a switching control part 110, a flip-flop X23 is reset, a level change of output signals s1-s5 of an input part 100 is detected by a NAND gate X21, and an output signal s9 of the flip-flop X23 is raised. In a switching part 120, when the signal s9 is at low level, output signals s10-s14 are held at high level, and when the signal s9 is at high level, the output signals s1-s5 of the input part 100 are output to an output part 130. Thus, the output signals are held after the power input, and after the input signal rises, the signal transfer function is started, so that the output of incorrect control signals can be prevented, and thereby erroneous operation of a printer can be prevented.

Abstract: An input interface circuit for a semiconductor integrated circuit device is provided which includes a pair of diodes, first, second, and third PMOSFETs, and first, second, and third NMOSFETs. The diodes serve to clamp a high positive or negative voltage input at a level that is the sum of the power supply voltage and the forward voltage of the diodes or the difference between the ground potential and the forward voltage. The first and second PMOSFETs are connected in series between the power supply and an inside input terminal coupled to an internal circuit element of the semiconductor integrated circuit device. The first and second NMOSFETs are connected in series between ground and the inside input terminal. The third PMOSFET is connected in series between the outside input terminal and a gate of the first PMOSFET. The third NMOSFET is connected in series between the outside input terminal and a gate of the second NMOSFET.

Abstract: A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting an output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor between the first and second electrodes for inputting the first node obtained based on the output data signal, and outputting the output node.

Abstract: Cascoded transistors can be used to allow circuits to operate at higher operating voltages than the voltages at which individual transistors (formed by a given process) can function. However, common techniques for cascading transistors result in circuits being unable to operate at lower operating voltages. The present invention dynamically biases cascoded transistors in response to the level of the operating voltage, which can vary. Providing separate dynamic bias voltages for N-type and P-type CMOS devices allows circuits using this technique to achieve a wider operating voltage. The wider operating range makes circuits using this technique readily adaptable to a range of power supplies (e.g., different battery configurations) and applications (e.g., driving displays).

Abstract: A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level.

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract: A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: A level adjustment circuit of the present invention includes a MOS transistor for pulling up an output node, a first inverter for inputting an output data signal and outputting a gate control signal for controlling a gate electrode of the MOS transistor, and a second inverter connected to the MOS transistor between the first and second electrodes for imputing the first node obtained based on the output data signal, and outputting the output node.

Abstract: A high voltage level shifter utilizing only low voltage PMOS and low voltage NMOS devices. The high voltage level shifter is used to distribute the high voltage almost equally among the PMOS devices and almost equally among the NMOS devices to meet the device electrical specification of low voltage MOS devices for various breakdown mechanisms. A layout technique is also used to achieve a much higher junction breakdown of N+ drain to P-substrate and a better gated diode breakdown of NMOS devices.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: A CMOS bus switch (20) having undershoot protection circuitry (22) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator (30) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN1) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: A signal is transmitted to/from an analog circuit portion and a digital circuit portion through an interface circuit portion. Analog circuit portion, digital circuit portion and interface circuit portion are externally supplied with power from different power supplies and provided in different well regions.

Abstract: Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different power supply in a closed loop feedback servo system. A clamping network connected to the higher gain amplifier to avoid hard saturation due to transient feedback signals from a reactive load, especially an inductive load, also prevents hard saturation of the high voltage, high current amplifier. An adjustable feedback circuit connected to the higher gain amplifier allows adjustment to obtain critical damping of a second order system and faster response to achieve proportionality of output current to input voltage with an accuracy of very few parts per million error and with minimum settling time.

Abstract: A regulated-cascode amplifier circuit comprising a positive sub-line, a negative sub-line, a first auxiliary amplifier, a second auxiliary amplifier and a clamping circuit. The positive sub-line has a positive output terminal and the negative sub-line has a negative output terminal. The positive and negative sub-line each has a cascode transistor structure. Each auxiliary amplifier includes a positive input terminal, a negative input terminal, a positive-bias output terminal and a negative-bias output terminal. The clamping circuit includes a first diode and a second diode. The front terminal of the first diode is electrically connected to the end terminal of the second diode. The front terminal of the second diode is electrically connected to the end terminal of the first diode. In addition, each auxiliary diode is connected to a clamping circuit such that the positive-bias output terminal and the negative-bias output terminal are connected to the two terminals of the diode clamping circuit respectively.

Abstract: An input interface circuit for a semiconductor integrated circuit device is provided which includes a pair of diodes, first, second, and third PMOSFETs, and first, second, and third NMOSFETs. The diodes serve to clamp a high positive or negative voltage input at a level that is the sum of the power supply voltage and the forward voltage of the diodes or the difference between the ground potential and the forward voltage. The first and second PMOSFETs are connected in series between the power supply and an inside input terminal coupled to an internal circuit element of the semiconductor integrated circuit device. The first and second NMOSFETs are connected in series between ground and the inside input terminal. The third PMOSFET is connected in series between the outside input terminal and a gate of the first PMOSFET. The third NMOSFET is connected in series between the outside input terminal and a gate of the second NMOSFET.

Abstract: A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.

Abstract: A low voltage CMOS bus switch (20) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (30) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref2, Dref3) when the supply (Vcc) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN1,MP1) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR1) turns off and a gate voltage of a N-channel pass transistor (MN1) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.

Abstract: A high-speed bus includes a bus line to be connected with a bus driver and a bus receiver. Pull-up resistors are connected to both ends of the bus line for feeding a given pull-up electric potential thereto. A series resistor is further connected between the bus line and each of the bus driver and the bus receiver. The bus driver includes a series resistor and a capacitive component which are connected in series between the bus line and the ground. The bus receiver includes a waveform shaping component connected to the bus line for shaping a waveform of an inputted signal, and a receiver circuit receiving as an input thereof an output of the waveform shaping component.

Abstract: An input/output (I/O) circuit is provided for selectively sinking current from an I/O pin. The I/O circuit includes: an output driver; a well bias circuit coupled to the I/O pin, the output driver, and an internal supply voltage; and a voltage clamping circuit coupled to the I/O pin and the output driver, the voltage clamping circuit selectively sinking current from the I/O pin to a voltage potential other than the internal supply voltage.

Abstract: A signal-transmission system includes signal-transmission lines connected to a terminal voltage via terminal resistances, open-drain-type transistors outputting signals to the signal-transmission lines, branch lines stemming from the signal-transmission lines to connect the open-drain-type transistors with the signal-transmission lines, and insertion resistances inserted in the branch lines in proximity of the signal-transmission lines.

Abstract: A semiconductor device comprises a level shifting circuit that can be achieved without using an extra charge pump and using low voltage transistors. The level shifting circuit 10 controls the on/off state of a transfer gate, which is an n-channel transistor N1. The level shifting circuit 10 has a NAND gate 11 to which the voltage mode selection signal HVON and input signal IN are given; the p-channel transistor P2, the n-channel transistor N4, and the n-channel transistor N6 series connected between the NAND gate 11 output and the −9V charge pump output Vncp; a NAND gate 13 to which the voltage mode selection signal HVON is input, and input signal IN is input through inverter 12; and the p-channel transistor P3, the n-channel transistor N5, and the n-channel transistor N7 series connected between the NAND gate 13 output and the charge pump output Vncp.

Abstract: A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.

Abstract: An apparatus and method for interconnecting digital and analog circuitry on separate substrates within a single integrated chip package attenuates logic level signals on one substrate, transmits the attenuated signals to another substrate, and amplifies the attenuated signals back to logic level signals.

Abstract: The present invention is generally directed to a PVT compensated variable impedance output driver for driving a signal through a signal pad on a semiconductor device. In accordance with one aspect of the present invention, the output driver includes a plurality of p-channel field effect transistors (PFETs) electrically connected in parallel. A source node of each of the plurality of PFETs are electrically connected together, and a drain node of each of the plurality of PFETs are electrically connected together. The driver further includes a plurality of n-channel field effect transistors (NFETs) electrically connected in parallel. A source node of each of the plurality of NFETs are electrically connected together and a drain node of each of the plurality of NFETs are electrically connected together.

Abstract: An output drive circuit within a semiconductor integrated circuit is formed into a push-pull configuration by field effect transistors, the bias of which is controlled to establish the output impedance of the driver at a desired value.

Abstract: The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Abstract: An interface in accordance with IEEE 1284 has a signal output stage which is a totem pole circuit. The totem pole circuit may be damaged if its output signal line is left grounded for an extended period of time or if outputs are being delivered at both ends of the signal line. Drive by the totem pole circuit is limited to a case where a signal to be output is at a low level and to a length of time equivalent to, say, one clock period from the moment the signal makes a transition from the low to a high level. A high impedance is established at all other times during which the high level is in effect, with the high level being maintained by a pull-up resistor connected to the output signal line. As a result, the totem pole circuit will not be damaged even if the output line is grounded while at the high level.

Abstract: An output amplitude regulating circuit comprises a first MOS differential circuit, with a first MOS transistor connected between an output terminal of the first MOS differential circuit and a power supply. The circuit also includes a second MOS differential circuit having a first input terminal that receives a reference electric potential, and a second MOS transistor that is connected between the power supply and a second input terminal of the second MOS differential circuit, and is connected to a reference electric potential via a third MOS transistor and a current source. In the circuit, output terminals of the first and second MOS transistors are used to regulate an output amplitude from the output terminal of the first MOS differential circuit.

Abstract: An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels is disclosed. The present invention uses various circuit techniques to ensure that no transistor in the input buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the input signal voltage may swing well beyond the tolerable voltage levels. This is accomplished without compromising the reliability of the input buffer circuit in detecting the logic levels of the input signal.

Abstract: An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.

Abstract: An input circuit provided in a semiconductor integrated circuit, comprises an nMOS transistor having a source connected to an input node receiving a transmission signal, a drain connected to a first node and a gate connected to a reference potential, and a pMOS transistor having a source connected to a power supply voltage, a drain connected to the first node, a first inverter having an input connected to the first node and an output connected to an output terminal, and a second inverter having an input connected to the first node and an output connected to a gate of the pMOS transistor, so that when the nMOS transistor is turned on, the pMOS transistor is rendered off, whereby no steady input current flows.

Abstract: An apparatus and method for interconnecting digital and analog circuitry on separate substrates within a single integrated chip package attenuates logic level signals on one substrate, transmits the attenuated signals to another substrate, and amplifies the attenuated signals back to logic level signals.

Abstract: A translation circuit for mixed logic voltage signals is comprised of a first pair of self-biasing common-mode level shifters for receiving positive and negative polarity input signals respectively of a balanced input signal, each level shifter having a control input for receiving a ratio control signal, and having first level shifter nodes for providing the same polarity output signals, a second pair of self-biasing common-mode level shifters, each connected in parallel with a corresponding variable ratio level shifter, the second pair of level shifters having fixed level shift ratios, a circuit connected to level shifter nodes of the second pair of level shifters for providing and storing a signal which is a sum of voltages appearing at the level shifter nodes, and a circuit for applying the stored signal to the control inputs.

Abstract: A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: An I/O current containment circuit capable of protecting a semiconductor device from input current that may cause latchup includes a MOS drive circuit and a parasitic sensing circuit having multiple terminals. When the parasitic sensing circuit senses that a voltage level at an input/output transcends a particular voltage potential, the terminal generates a control signal which activates the drive circuit. The drive circuit then absorbs substantially all of the output current that could otherwise flow into the substrate of the semiconductor device.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: An electrostatic protection circuit in a internal circuit isolated from a substrate bias which protects the internal circuit from static electricity with regard to any of three different sources of bias voltage. An electrostatic protection circuit is constructed for each source of bias voltage so that the internal circuit is protected from static electricity flowing through bonding pads of the isolated circuit. The protective circuit comprises a plurality of NMOS or PMOS transistors for protecting input/output buffers and drivers from the static electricity flowing through the bonding pads. The respective NMOS or PMOS transistors are connected to the respective source voltage terminals and the input/output drivers.

Abstract: A differential amplifier circuit includes a differential amplifier having inversion and non-inversion input terminals and input amplifiers each individually connected to one of these input terminals, serving to receive an input voltage within a certain range and output it as another voltage in a smaller range. The differential amplifier is of a kind using n-type and p-type MOS transistors with threshold voltages given respectively by V.sub.thn and V.sub.thp, and connected to a source voltage V.sub.DD and a reference voltage V.sub.ref. Input voltages to the input amplifiers within the range between V.sub.ref and V.sub.DD, are outputted within the range between (V.sub.DD -V.sub.thp) and (V.sub.ref +V.sub.thn), or preferably between (V.sub.DD -1.5V.sub.thp) and (V.sub.ref +1.5V.sub.thn).

Abstract: A reference potential difference canceling circuit is provided in a circuit system of a transmitter side to remove noise caused by impedance Z between circuit systems having different reference potentials from a signal, and to transmit the signal. The reference potential of the circuit system of a receiver side is supplied to an input terminal of the reference potential difference canceling circuit, and its output terminal is connected to an input terminal of an output amplifier to which a transmitting signal is input. A gain of the reference potential difference canceling circuit is set to a reciprocal number of a gain of the output amplifier.

Abstract: A bus line termination circuit for limiting signal swing on a bus line to a reduced CMOS-swing. The termination circuit includes a switch and a first resistor connected in series between the bus line and a first voltage supply, and a second resistor connected in series between the bus line and a second voltage supply. The values of the first and second resistors are selected such that a termination voltage equal to the average of the first and second supply voltages exists on the bus line. The bus line is further connected to a receiver circuit having a threshold voltage equal to the average of the first and second supply voltages. The switch is controlled to disconnect the bus line from the first voltage supply when the bus line is in an inactive state. In an alternative embodiment, a termination circuit includes one or more voltage regulator circuits, each being coupled to the first and second voltage supplies. A clamping resistor coupled each voltage regulator circuit to the bus line.

Abstract: Low quiescent power, high output power, rail-to-rail output stage circuits and methods are provided. The output stages are capable of providing output voltages that are substantially equal to the supply voltages (i.e., within one V.sub.CE SAT of both supply voltages) without a substantial increase in output circuit complexity and without a substantial increase in quiescent current. The output stages operate by providing a direct path for the drive signal to the output sinking transistor, and an additional, separate path for the drive signal to the output sourcing transistor. The sinking and sourcing paths are separated by a PNP transistor that gradually turns off during sinking to isolate that portion of the circuit so that the drive current to the sinking transistor is not reduced. Additional embodiments are provided where additional components are utilized to further increase the maximum sink and source currents without a significant increase in quiescent current or reduction in output swing.

Abstract: A level shifting circuit includes first and second load, gain and reference transistors. The first and second load transistors each have a source-drain path arranged between Vdd and Vss power supply voltages, and a gate coupled to the Vss power supply voltage. The first and second gain transistors each have a source-drain path arranged between the respective source-drain paths of the first and second load transistors and the Vss power supply voltage, and gates serving as respective differential input nodes. The first and second reference transistors each have a source-drain path arranged between the Vdd and Vss power supply voltages, and a gate coupled to respective first and second nodes serving as respective differential output nodes, the first node connecting the source-drain path of the first load transistor with the source-drain path of the first gain transistor, and the second node connecting the source-drain path of the second load transistor with the source-drain path of the second gain transistor.

Abstract: A universal input circuit which responds to a wider range of input voltages by eliminating the problem of heat dissipation in the input section of the circuit. The universal input circuit includes an input section and an output section connected by an opto-isolator for electrically isolating the input section from the output section. The input section of the universal input circuit is configured to turn on in response to an in-range DC input voltage activating the opto-isolator to produce a signal which drives the output section of the universal input circuit. A retriggerable, monostable, multivibrator is included in the output section of the universal input circuit which supplies an output in response to an in-range AC input voltage.

Abstract: An ASIC (5) has four driver circuits (19a-19d), each with different output power. One of those driver circuits is selected from the content of register (13) on the ASIC. The register content being decoded by a decoder (15) on the ASIC to a signal which activates a single one of the drivers. The register is loaded from an external microprocessor during each initialization of a printer (1) in which the ASIC is a component. The ASIC is designed with the range of the powers of the drivers bracketing the estimated needs of the load to be attached to the ASIC. This permits the ASIC to be completed only once, while the most suitable driver for the final load is determined subsequently and selected by the entry of data to activate that driver into the register with each initialization of the printer. The ASIC need not have nonvolatile memory and only a single set of ASIC masks and other design aspects need be completed.

Abstract: An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are "ON.

Abstract: A circuit that includes a series arrangement of a capacitive element (C) and an active component (M10) forming an equivalent resistor. A DC current source (120 is connected to the active component, and a transistor (M11, 11) is provided for altering the conductance of the active component and fixing the mean level of a AC voltage (U.sub.ac). Such a voltage is applied to the terminals of the series arrangement, and the biased voltage having the desired mean level (U.sub.out) is tapped off the node (10) between the capacitive element (C) and the active component. A capacitive voltage divider (13) is also provided for modulating the DC current (i) passing through the active component (M10), with a fraction of the AC voltage to be biased. The circuit is particularly applicable to the determination of the mean level of the voltage produced by a quartz oscillator.