Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Abstract: A device configured to emulate a binary correlithm object logic function gate comprises a memory and a logic engine. The memory stores a logical operator truth table that includes first and second groups of input logical values and a group of output logical values. These logical values are represented by correlithm objects. The logic engine receives first and second inputs and determines the Hamming distance between the correlithm objects of the inputs and the correlithm objects of the truth table to determine the appropriate output.

Abstract: In order to enable to estimate whether the bit error occurs steadily or instantaneously, an error monitoring method according to an exemplary aspect of the invention includes: detecting number of error bits of received data per bits whose number is predetermined, comparing the number of error bits with a threshold value which is predetermined, and counting and outputting number of times of continuous occurrence of the comparison result's indicating being large, and number of times of continuous occurrence of the comparison result's indicating being small.

Abstract: A method includes forming a coating that covers at least part of a conduction substrate, where the conduction substrate is configured to transport thermal energy. The method also includes forming at least part of an optical waveguide on the coating. The optical waveguide includes multiple cladding layers and a core, and the optical waveguide is configured to transport optical signals. The conduction substrate, the coating, and the optical waveguide form an integrated monolithic waveguide structure.

Abstract: Provided is a Digital Pre-Distortion (DPD) apparatus and method for processing a signal that is input to a power amplifier in a wireless communication system. The DPD apparatus includes a DPD unit configured to pre-distort an input signal that is input to the power amplifier, using DPD information; and a signal processor configured to capture signals for estimation of the DPD information from each of an input terminal and an output terminal of the power amplifier, detect peak signals of the captured signals, separate the detected peak signals into a plurality of intervals depending on a power level, separately store the detected peak signals, estimate the DPD information using the peak signals stored for each interval, and provide the estimated DPD information to the DPD unit.

Abstract: One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each signal channel includes: a column III-V semiconductor sampler coupled the input signal and being responsive to sampling signals; and a column IV semiconductor controllable time delay for producing the train of sampling signals in response to a train of pulses produced on the column IV semiconductor, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: A sampling circuit for current transformer includes a current sensing unit, a rectification unit, a sampling unit and a switching unit. The rectification unit is electrically connected to the current sensing unit. The sampling unit is electrically connected to the rectification unit and outputs a first signal. The sampling unit includes an energy leakage device and a switching device. The switching device is electrically connected to the energy leakage device in parallel, and is turned on or off according to a second signal and a third signal. The switching unit is electrically connected to the sampling unit, and is turned on or off according to the second signal.

Abstract: The present invention provides a level translator circuit, a driving circuit for driving a high-voltage device and a corresponding method. The driving circuit for driving a high-voltage device comprises: a zener diode whose cathode is connected to a high-voltage power supply voltage and whose anode is connected to a ground potential of a low-voltage domain through a resistor; a high-voltage PMOS transistor whose gate is connected to an anode of the resistor, whose drain is connected to the ground potential of the low-voltage domain, and whose source is operable to supply a ground potential of a high-voltage domain; a level translator operable to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain and output the second signal; and a low-voltage driving circuit operable to receive the second signal and adapt the second signal as a third signal which can drive the high-voltage device.

Abstract: A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.

Abstract: A phase adjuster 2a receives a trigger clock synchronized with a data signal to be measured as input, and controls the phase of the trigger clock such that the trigger period of samples of the data signal to be measured becomes one sample per bit. An adjustable frequency divider 2b has a frequency division ratio which is set such that a trigger pulse is generated at the fixed timing of the waveform pattern of the data signal to be measured. An interleaving unit 4d uses a discrete value which is in prime relation to the measured pattern length of the data signal to be measured, and acquires data for the number of samples corresponding to the measured pattern length from a sampler 3 by the trigger pulse from the adjustable frequency divider 2b.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: System and method for detecting a glitch is disclosed. An embodiment comprises increasing a bias voltage of a first capacitor, sampling an input signal of a first plate of the first capacitor with a time period, mixing the input signal with the sampled input signal, and comparing the mixed signal with a reference signal.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: Techniques are disclosed relating to tracking edges of a signal of a buffer circuit. In one embodiment, an apparatus is disclosed that includes a sampling circuit configured to sample a pulse width modulation (PWM) signal to generate a threshold voltage based on an average of the high and low voltage levels of the PWM signal and to provide the threshold voltage to an input of a comparator of the apparatus. The comparator is configured receive the threshold voltage and the PWM voltage and perform edge detection on the threshold voltage and PWM signal.

Abstract: A diode-laser having an elongated diode-laser emitter is mounted on a relatively massive heat-sink. Two parallel grooves are machined into the heat-sink to leave a relatively narrow elongated ridge of the heat-sink between the grooves. The ridge has a width about equal to or narrower that the width of the emitter. The diode-laser is mounted on the heat-sink such that thermal communication between the emitter and heat-sink is essentially limited to thermal communication with the ridge.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: A power-receiving-side control circuit of a power reception device performs intermittent load modulation by causing an NMOS transistor to be turned ON/OFF during normal power transmission. A power-transmission-side control circuit included in a power transmission control device of a power transmission device monitors, an intermittent change in the load of the power reception device during normal power transmission. The power-transmission-side control circuit determines that a foreign object has been inserted between a primary coil and a secondary coil and stops power transmission when an intermittent change in load cannot be detected. The amount of power supplied to the load may be compulsorily reduced when the load state of the load is heavy.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: An apparatus includes a first sequential circuit which captures an input signal according to a first clock signal, a second sequential circuit which captures the input signal according to a second clock signal and outputs the captured input signal to a logic circuit, the second clock signal being modulated so that a period of the second clock signal is shorter than that of the first clock signal, a third sequential circuit which captures an output signal of the logic circuit according to the second clock signal, and a verification circuit which verifies whether an output signal of the first sequential circuit and an output signal of the third sequential circuit match with each other.

Abstract: A high voltage power supply and a high voltage power control method thereof. The high voltage power supply includes a high voltage generation part to generate a high voltage, and a pulse width modulation (PWM) generation part to generate a pulse width modulation signal according to an output control value and to control the high voltage generation part to generate the high voltage using the generated pulse width modulation signal, when a high voltage output setting signal having the output control value is received by the PWM generation part to indicate the high voltage to be generated. Therefore, it is possible to automatically output a high voltage as desired without requiring an offline setting. In addition, although a voltage set and/or an output load are changed, the changed voltage set and/or the output load are automatically compensated so that a constant high voltage output can be output with a variety of different devices having different loads and power requirements.

Abstract: An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.

Abstract: An apparatus includes a first sequential circuit which captures an input signal according to a first clock signal, a second sequential circuit which captures the input signal according to a second clock signal and outputs the captured input signal to a logic circuit, the second clock signal being modulated so that a period of the second clock signal is shorter than that of the first clock signal, a third sequential circuit which captures an output signal of the logic circuit according to the second clock signal, and a verification circuit which verifies whether an output signal of the first sequential circuit and an output signal of the third sequential circuit match with each other.

Abstract: A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal.

Abstract: A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C1 based on a constant bias current in the opposite direction while changing the voltage of a second integration circuit C2 during the second period T2, and changes the voltage of the second integration circuit C2 based on the bias current during the third period T3. The amount of time from the start of the second period T2 until the voltage of the first integration circuit C1 reaches the reference voltage Vth is detected, and the amount of time from the start of the third period T3 until the voltage of the second integration circuit C2 reaches the reference voltage Vth is detected.

Abstract: Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: Determining a predistortion function includes sampling a signal to obtain a plurality of capture sets within a single sampling window. Each of the capture sets is analyzed to determine whether it satisfies preselected criteria. Example criteria include desired characteristics of a capture set average power, capture set peak power and a number of peaks within a capture set. If any capture set within the sampling window satisfies all of the preselected criteria and has the highest number of peaks, that capture set will be used for determining a predistortion function. A multiple capture set selection module applies the preselected criteria for selecting an appropriate capture set for determining the predistortion function. The predistortion function is used for applying predistortion to a signal before that signal is processed by a distorting component that introduces distortion so that the predistortion can compensate for or cancel out such distortion.

Abstract: A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.

Abstract: A circuit arrangement for the correction of periodic signals from an incremental position measuring system that includes a first assembly comprising a multiplexer having an input to which a periodic signal is supplied and an output out of which an output signal is transmitted, a second assembly that receives the output signal and compares the output signal with at least one preset threshold value and, the second assembly selects a manipulated variable as a function of an actual position of a signal parameter in relation to the at least one preset threshold value from at least two preset, different manipulated variables and an actuating member that performs an action on the signal parameter in order to adjust the signal parameter in a direction toward a preset setpoint value.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: A space-efficient broadband balun (20). The balun (20) includes a first mechanism (44, 80, 82, 94, 96) for receiving an input signal (52, 54) having an undesirable component. A second mechanism (50) rejects the undesirable component via a waveguide transition (50). In a specific embodiment, the undesirable component is a common mode component. The first mechanism (44) includes an input microstrip waveguide (44). The waveguide transition (50) is a single microstrip-to-slotline transition (50) from the input microstrip waveguide (44) and to a slotline (32) in a ground plane (34, 36) of the microstrip waveguide (44). The slotline (32) is terminated at a first end (38) via a wedge (40) in the ground plane (34, 46). A second end (42) of the slotline (32) provides an output of the balun (20). The input signal (52, 54) includes a first input signal (52) and a second input signal (54), which are input at opposite ends (38, 42) of the input microstrip waveguide (44).

Abstract: A systems and method generate a progressively corrected scan signal, the progressively corrected scan signal having a magnitude independent of spectral reflectance from a background near a target. One of the methods involves generating a baseline signal by sampling light reflected from the target and background before transmitting a light scan at the target, generating a detected signal by receiving light reflected from the target and background while transmitting the light scan at the target, and subtracting the baseline signal from the detected signal to form the progressively corrected scan signal. One circuit embodiment produces an average level independent output signal from an input signal subject to fluctuations in average level.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

Abstract: An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided in each memory cell. One sample of an analog signal is stored in one memory device, and one sample of that signal that is out of phase is stored in the other memory device.

Abstract: Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.

Abstract: Duty measuring circuitry of the present invention includes a pulse detecting circuit for detecting at least one of a convex pulse width and a concave pulse width included in an input data signal. A duty decision circuit determines whether or not the convex pulse width or the concave pulse width detected is smaller than a preselected value. If the detected pulse width is smaller than the preselected, the duty decision circuit determines that the pulse width is valid, and feeds it to an averaging circuit. The circuitry obviates the need for an exclusive fixed pattern, e.g., ONEs and ZEROs alternating with each other customarily used for the measurement of a duty. In addition, the circuitry is capable of accurately measuring a duty even with a random pattern based on RZ (Return-to-Zero) code or NRZ (Non-Return-to-Zero) code.

Abstract: A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. At least three data capturing circuits operate to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.

Abstract: Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.

Abstract: A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32&pgr; radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2&pgr; radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected.

Abstract: A digital pulse filtering circuit for filtering out pulses of specific pulse widths in a composite signal is provided. The digital pulse filtering circuit includes a sampling circuit for sampling the input composite signal based on a periodic clock signal to thereby generate a plurality of sampled signals of the input composite signal. In response to these sampled signals, a detection circuit outputs a low-frequency composite signal which is a filtered version of the input composite signal. The digital pulse filtering circuit is completely based on digital circuitry which can be built in integrated circuits. The cutoff frequency of the digital pulse filtering circuit is dependent on the frequency of the clock signal, which is very easy and accurate to adjust.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.