Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic ?1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic ?1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A high voltage power control system comprises a microcontroller unit, an embedded non-volatile memory, and a high voltage driver. The micro controller unit is configured to control high voltage outputs of the high voltage power control system. The embedded non-volatile memory is electrically connected to the micro controller. The high voltage driver is electrically connected to the micro controller and is configured to output the high voltage outputs of the high voltage power control system. The high voltage power control system is compatible with a logic process while the embedded non-volatile memory and the high voltage power control system can still support operations of high voltage.

Abstract: The present invention provides a level shift circuit having low possibility of malfunction by noise, and can operate with low power.

Abstract: Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Abstract: A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.

Abstract: A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals.

Abstract: A source driver and a method to reduce peak current of the source driver are provided. The source driver includes a latch circuit, a level shifter and a digital-to-analog converter (DAC) circuit. The latch circuit latches current bit-data. The latch circuit is coupled to an input terminal of the level shifter. The DAC circuit is coupled to an output terminal of the level shifter. When the current bit-data is not a complement of previous bit-data, the latch circuit selects and outputs the current bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the output data of the level shifter. When the current bit-data is the complement of the previous bit-data, the latch circuit selects and outputs the previous bit-data to the input terminal of the level shifter, and the DAC circuit outputs a voltage corresponding to the current bit-data.

Abstract: A level shifter includes high breakdown voltage first and second PMOS transistors, high breakdown voltage first and second depression NMOS transistors having gates respectively supplied with first and second control signals, low breakdown voltage first and second NMOS transistors having gates respectively supplied with third and fourth control signals, and a timing control unit that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal.

Abstract: A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals.

Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.

Abstract: This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state.

Abstract: A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal. Said third and fourth transistors have respective control terminals controlled by drain terminals of said first and second transistors, respectively. The shifter includes a bidirectional battery coupled between said drain terminals of said first and second transistors to supply first and second voltages having the same magnitude and different polarities. Said fourth transistor is controlled according to the first voltage when said first transistor is turned on and said third transistor is controlled according to the second voltage when said second transistor is turned on.

Abstract: In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 ?m, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.

Abstract: A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal.

Abstract: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit.

Abstract: A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line.

Abstract: A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal. A second transistor of the transistors of the second pair of transistors is coupled with an inverted input signal terminal. The transistors of the second pair of transistors are cross-coupled with the transistors of the first pair of transistors. The voltage level shift circuit also comprises a third pair of transistors. The transistors of the third pair of transistors are coupled with the transistors of the first pair of transistors and the transistors of the second pair of transistors. A first transistor of the third pair of transistors is directly coupled with an output signal terminal and second transistor of the third pair of transistors is directly coupled with an inverted output signal terminal.

Abstract: Disclosed herein is a device includes; a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and output ting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and output ting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.

Abstract: The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.

Abstract: A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.

Abstract: Disclosed is a level shift circuit that includes a first transistor of a first conductivity type connected between a first power supply line and a first node, and second and third transistors of a second conductivity type connected in series between a second power supply line and the first node. A first control signal is supplied in common to a gate of the first transistor and a gate of one of the second and third transistors. A gate of the other of the second and third transistors is connected to an input terminal to which an input signal with an amplitude lower than a power supply amplitude of the first and second power supplies is supplied.

Abstract: A level shifter circuit, wherein a first and a second transistor circuit are connected serially, a third and a fourth transistor circuit are connected serially; a first input voltage is applied to the second transistor circuit and a second input voltage is applied to the fourth transistor circuit; an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits; two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and the level shifter circuit has a switch element for applying a voltage to a common connection node.

Abstract: An apparatus includes a number of current steering switches and a power controller. A current source is coupled to the current steering switches and to the power controller. The current source is controlled to provide a first voltage to the current steering switches. The apparatus also includes a number of pre-drivers. The power controller is configured to provide a second voltage to the plurality of pre-drivers. The second voltage is dependent on the first voltage.

Abstract: There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

Abstract: A semiconductor device according to an embodiment is provided with a normally-off transistor which includes a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal, and a normally-on transistor which includes a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the gate terminal.

Abstract: The invention provides a bidirectional level shifter which includes: a first signal terminal; a second signal terminal; a first switch, coupled between the first signal terminal and ground; an inverter receiving a signal from the first signal terminal; a Schottky diode including an anode and a cathode, the anode receiving a signal from the second signal terminal; a second switch, coupled between the cathode of the Schottky diode and the ground; a comparing circuit, comparing a reference voltage and a voltage at the second signal terminal to control the first switch, wherein the reference voltage is lower than a forward bias voltage of the Schottky diode; a first voltage source coupled to the first common node; and a second voltage source coupled to the second common node.

Abstract: A level conversion circuit including a first level shifter and a second level shifter is provided. The first level shifter converts a first control voltage into a second control voltage during a voltage conversion period. The second level shifter is coupled to the first level shifter. The second level shifter converts the second control voltage into a third control voltage during the voltage conversion period to control a next stage circuit. The first level shifter is configured to detect a voltage level of a power domain where the third control voltage operates and generate a plurality of middle voltages based on the detection result. The second level shifter is configured to generate the third control voltage based on the middle voltages. Furthermore, a voltage level conversion method is also provided.

Abstract: A switching circuit (100, 200) for switching a voltage at an output node (120), comprises a first switch element (T1) coupled between a first supply node (110) and the output node (120), the first supply node (110) being at a first supply voltage (VDD), and a second switch element (T2) coupled between a second supply node (130) and the output node (120), the second supply node (130) being at a second supply voltage (Vss)- A switch controller (140) is arranged to, dependent on an input signal (VIN), switch the switching circuit (100, 200) between a first state, in which the first switch element (T1) is in a conducting state and the second switch element (T2) is in a non-conducting state, and a second state, in which the first switch element (T1) is in a non-conducting state and the second switch element (T2) is in a conducting state, through an intermediate state in which both the first switch element (T1) and the second switch element (T2) are in the non-conducting state.

Abstract: According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal. The level shifter adjusts a voltage level between a first terminal and a second terminal. The switch circuit includes a first switch selectively connecting the third terminal of the regulator to a first potential, a second switch selectively connecting the third terminal of the regulator to the first terminal of the level shifter, and a third switch selectively connecting the third terminal of the regulator to a second potential.

Abstract: A level conversion circuit includes level conversion portions which are connected in series. The level conversion portion includes circuit blocks. The circuit block inverts an input signal. The circuit block includes a transistor connected between a power supply and a node, a transistor connected between the node and a power supply, a transistor connected between a gate of the transistor and the power supply, and a capacitor connected between an output node and the gate of the transistor. The circuit block carried out level conversion in step with operation of the transistor in accordance with a signal applied from an input node to a gate thereof and operation of the transistor an ON/OFF state of which is switched by application of an output of the circuit block to a gate thereof, to thereby output potential change at the node.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A level shifter circuit includes a level shifter unit and a first controlling unit. The level shifter unit has an input node for receiving an input signal having a predetermined level, an output node for outputting an output signal having a desired level and a complementary output node for outputting a complementary output signal complementary to the output signal. The first controlling unit is coupled to the level shifter unit and has a first transistor coupled between the complementary output node and a first control node for receiving a first control signal and a second transistor coupled between the input node for receiving the input signal and a ground.

Abstract: Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-FET coupled to a high reference voltage, and an n-FET coupled to a low reference voltage. The device also includes two latches. The first latch has a first latch output that drives a gate of the p-FET via an inverting circuit element. The second latch has a second latch output that drives a gate of the n-FET via a non-inverting circuit element. The device also includes a reset signal pulse generator that receives the input signal and generates a reset signal pulse in response to a transition in the input signal. Both of the latches are placed in a reset state by the reset signal pulse.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.

Abstract: A level shift circuit of an embodiment includes first and second MOSFETs using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second MOSFETs; and a current control circuit that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.

Abstract: A voltage level translator includes an inverter circuit configured to switch an output of the inverter circuit between a first voltage level and a second voltage level. The voltage level translator also includes a capacitor connected to the output of the inverter circuit. The voltage level translator also includes a load connected to the capacitor. The capacitance of the capacitor is approximately 10 times larger than a capacitance of the load. An output signal of the voltage level translator has at least one of a different voltage swing and a different voltage domain than an input signal to the inverter circuit.

Abstract: A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.

Abstract: A circuit includes an input stage, a comparison stage, and a calibration stage. The input stage is configured to receive a first input signal, to generate a first reference signal, and to generate a second reference signal. The comparison stage is configured to generate a first comparison output signal in response to the first reference signal and a third reference signal and to generate a second comparison output signal in response to the second reference signal and a fourth reference signal. The calibration stage is configured to generate a detection signal responsive to the presence of the first comparison output signal and the second comparison output signal having a signal frequency within a predetermined frequency band.

Abstract: A level shifter does not require any DC (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors. The input-output power voltages domains are unrestricted and flexible. DC isolation is deployed between power domains. Symmetrical rise/fall times are without duty cycle distortion. Over voltage stress is reduced by using metal capacitors. Finally the level shifter does not use high-voltage devices for level shifting purpose. Embodiments of level shifters provide one-way level shifting and bi-directional level shifting.

Abstract: According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.

Abstract: Circuits and methods for fast detection of a low voltage in the range of few ?Volts have been achieved. In a preferred embodiment the low voltage represents a current via a shunt resistor and the circuit is used to generate a digital wake-up signal. In regard of the wake-up application the circuit invented is activated periodically and in case of a certain level of the voltage drop, e.g. 50 ?V, at the shunt resistor. The time required for a measurement of the voltage drop is inclusive calibration and integration time far below 1 ms. It is obvious that the circuit invented can be used for any measurements of very small voltages.

Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

Abstract: An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type. Furthermore, a capacitor is provided in the level-shift circuit, and a signal to be boosted is supplied to the capacitor and is boosted using capacitive coupling of the capacitor. Furthermore, a structure can be employed in which the signal is boosted in such a manner that, in the level-shift circuit, a capacitor is provided between a wiring for supplying a low power source potential and a wiring for supplying a potential to boost the signal so that a power transistor can be driven.

Abstract: In a signal electric potential conversion circuit, a capacitor has one end receiving an input signal CIN, and the other end connected to a termination node N1. A conversion circuit receives a potential IN of the termination node N1. A connection element is provided between a power supply VDDH and the termination node N1, and an impedance of the connection element is reduced when the potential IN is lower than a first potential. Another connection element is provided between the termination node N1 and a ground power supply, and an impedance of the connection element is reduced when the potential IN is higher than a second potential.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: An interface circuit for driving a fully-differential circuit has a first circuit configured to decrease the voltage at its output in response to an increase in an average value of first and second input voltages. A first network receives the first input voltage and the output voltage of the first circuit to provide a first output voltage for driving the fully-differential circuit. A second network receives the second input voltage and the output voltage of the first circuit to provide a second output voltage for driving the fully-differential circuit. An impedance ratio of the first network is substantially matched to an impedance ratio of the second network.

Abstract: A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates.