Abstract: Methods and related systems are described for determining the casing attenuation factor for various frequencies from measurements of the impedance of the transmitting or receiving coil of wire of. The compensation is based on two relationships. The first relationship is between one or more measured impedance parameters and the product of casing conductivity, casing thickness and electromagnetic frequency. The second relationship is between the casing correction factor and the product of casing conductivity, casing thickness and electromagnetic frequency.

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Abstract: Systems and methods are provided for power measurement of signals such that the power measurement is insensitive to PVT variations of the measurement systems. A power measurement system includes an analog squarer circuitry, an integrating ADC, and a controller. The squarer circuitry calculates the power of a signal whose power is to be measured while the integrating ADC integrates the calculated power over a runup interval to generate an integrated power. The squarer circuitry also calculates the power of a reference for the integrating ADC to de-integrate the integrated power over a rundown interval. The power measurements are independent of PVT variations of the analog squarer circuitry and integrating ADC. The controller digitally controls the runup interval and measures the rundown interval to provide digitized power measurements. The analog squarer circuitry have replica squarer circuits. Process dependent mismatches between the replica analog circuitry may be removed through a calibration process.

Abstract: A precision current reference or a precision oscillator includes a circuit that precisely controls the cyclic charging of a switched capacitor. The voltage across the switched capacitor is ramped up to a desired voltage during the charge phase. The circuit comprises a network of switched capacitors around a transconductance amplifier. An error voltage between a predetermined voltage and a voltage across the switched capacitor is amplified by a transconductance amplifier to give an error current, which is integrated over time to give an integrated error voltage. The error voltage can be minimized such that the circuit produces a precise output current whose value depends on the switched capacitor capacitance, the predetermined reference voltage and a frequency used to switch the switched capacitors. Alternatively, an embodiment may be part of a frequency locked loop to provide a precise oscillator whose frequency depends on a predetermined resistance and the switched capacitor capacitance.

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.

Abstract: Configurable analog input circuits are provided. An analog input circuit may include a plurality of configurable input channels, at least one analog-to-digital converter, and at least one processor. Each input channel may include a plurality of switches utilized to select a type of input signal received via the input channel and a set of input terminals selectively utilized to correspond with the selected type of input signal. The at least one analog-to-digital converter may be configured to convert, for each of the plurality of input channels, the selected type of input signal into a digital output. The at least one processor may be configured to control operation of the plurality of switches associated with each of the plurality of configurable input channels.

Abstract: Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset.

Abstract: A current-mode filter includes a first, a second, and a third transistor having the same channel polarity. The drain of the first transistor is connected to the source of the second transistor functioning as a gate grounded circuit. The drain of the second transistor is connected to the gates of the first and third transistors. A first and a second capacitive element are connected to the gate and drain of the first transistor. The current source supplies a bias current to each of the first and second transistors. The drain of the first transistor is used as an input terminal. An output signal is extracted from a drain current of the third transistor. Therefore, only one transconductance adjustment circuit is enough.

Abstract: The invention relates to a device comprising a photosensitive element producing an electric charge as a function of the radiation incident thereon and a charge integrator connected to the photosensitive element and converting the charge to a voltage. According to the invention, the device comprises a comparator capable of comparing the voltage delivered by the integrator with a threshold voltage, and a memory unit for storing the instant when the voltage delivered by the integrator exceeds the threshold voltage.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp.

Abstract: The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).

Abstract: A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description.

Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Abstract: A low-pass filter includes an integrator having an adjustable unity frequency. The integrator includes a first input, first output and feedback loop between the first input and output of the integrator. The first input is connected to a branch that includes a first impedance, to which is applied a first input voltage of the low-pass filter. The feedback loop includes a second impedance and the first output of the integrator is the first output of the low-pass filter.

Abstract: A pseudo-differential switched-capacitor circuit, which can be applied to various signal processing circuits, employs a floating sampling technique and an integrator feedback loop for isolating a common mode voltage disturbance and restraining a charge injection effect. The pseudo-differential switched-capacitor circuit includes a differential floating sampling circuit that has a pseudo-differential architecture, and an integrator for reducing the charge injection effect within the differential floating sampling circuit.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

Abstract: A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Abstract: A touch apparatus including a touch capacitor and a touch control unit is provided. The touch control unit includes a signal sampling and saving unit, a switch unit, and a signal processing unit. The signal sampling and saving unit samples and saves a voltage on the touch capacitor during enable periods of a sample signal and a charge reset signal, so as to generate a touch voltage and a reset voltage respectively, and further generate an average voltage of the touch voltage and the reset voltage according to an equalization signal. The switch unit receives and transmits the touch voltage, the reset voltage, and the average voltage according to a first control signal. The signal processing unit couples the touch voltage, the reset voltage, the average voltage, and a common voltage according to a second control signal, so as to generate a first coupling voltage and a second coupling voltage.

Abstract: An active integrator for sensing capacitance of a touch sense array is disclosed. The active integrator is configured to receive from the touch sense array a response signal having a positive portion and a negative portion. The response signal is representative of a presence or an absence of a conductive object on the touch sense array. The active integrator is configured to continuously integrate the response signal.

Abstract: The invention relates to controlling a device for converting charge into voltage comprising an amplifier and at least one capacitor mounted in inverse feedback between an input and an output of said amplifier, whereby said amplifier can be connected between at least one input stage, to receive a charge therefrom, and at least one output stage to deliver voltage thereto, said voltage being representative of the charge received at the input, said method comprising at least one phase comprising the voltage conversion of a charge received at the input. According to the invention the conversion phase comprises at least: one first sub-phase during which the amplifier is connected to the input stage and the amplifier is disconnected from the output stage; followed, by a second sub-phase during which the amplifier is disconnected from the input stage and the amplifier is connected to the output stage.

Abstract: The invention relates to controlling a device for converting charge into voltage comprising an amplifier and at least one capacitor mounted in inverse feedback between an input and an output of said amplifier, whereby said amplifier can be connected between at least one input stage, to receive a charge therefrom, and at least one output stage to deliver voltage thereto, said voltage being representative of the charge received at the input, said method comprising at least one phase comprising the voltage conversion of a charge received at the input. According to the invention the conversion phase comprises at least: one first sub-phase during which the amplifier is connected to the input stage and the amplifier is disconnected from the output stage; followed, by a second sub-phase during which the amplifier is disconnected from the input stage and the amplifier is connected to the output stage.

Abstract: An integrator circuit is provided in the present invention, which utilizes a first capacitor and a first switching unit to sample an input signal and carries out distribution of charges between the first capacitor and a second capacitor. The second capacitor is larger than the first capacitor in capacitance. The integrator circuit transmits the charges stored in the second capacitor to a node of the first capacitor which is coupled to a ground previously. Accordingly, a direct current voltage level of the first capacitor may increase, facilitating an increase in a direct current voltage level at the second capacitor. Thereby, the accuracy and linearity of the integrator circuit may improve.

Abstract: A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a compensation digital filter providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

Abstract: A general-purpose Analog Signal Processing System (ASPS) is disclosed. An ASPS can be realized though an array of Configurable Integrator Blocks (CIBs). The CIBs can be identical to each other, and arranged in rows and columns. A CIB can merge multiplication, integration, and sample-and-hold functions into a single programmable circuit block. Within the ASPS, CIBs are interconnected in a manner that allows CIB inputs to be a combination of external signals and outputs of other CIBs, and allows CIB outputs to be combined to produce system (external) outputs or inputs to other CIBs. This networked architecture combined with the basic functionality of each CIB, enables implementation of a broad range of analog signal processing operations. The ASPS can be field programmable. The field programmability permits end users to be able to quickly and inexpensively fabricate customized analog integrated circuits.

Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating circuit to integrate a difference between the input signal and the reference signal.

Abstract: An analog front end circuit utilizes coherent detection within a capacitance measurement application. The analog front end circuit uses coherent detection to measure capacitance of a touch screen display. An analog excitation signal is modulated by a capacitor to be measured. The modulated signal is synchronously demodulated using a correlator, which includes an integrated mixing and integration circuit. The correlator includes a programmable impedance element that generates a time-varying conductance according to a controlling digitized waveform.

Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

Abstract: An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. In an embodiment, the integrated circuit includes a bias circuit, an amplifier circuit and two feedback circuits. The amplifier circuit includes a first input, a second input, and an output. The first input receives either the input signal or a feedback signal, depending upon mode control signals. The second input receives either the feedback signal or the input signal depending upon the mode control signals. The first feedback circuit is in communication with the output and the first input of the amplifier and includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit and provides the feedback signal. The mode control signals can be set in a programmable mode control register.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: A configurable switched capacitor block includes a switched-capacitor (SC) sampling circuit, a fully differential amplifier, an SC feedback circuit, and a comparator. The SC sampling circuit is coupled to receive an input signal and to selectively generate a sampled signal to a differential input of the amplifier. The SC feedback circuit is coupled between the differential inputs and the differential outputs of the amplifier to selectively control a feedback of the amplifier. The comparator is coupled to the differential outputs of the amplifier to generate an output signal. The configurable switched capacitor block has multiple modes of operation which are selectable by programming the SC sampling circuit and the SC feedback circuit.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance interface circuit is provided. An external inductive capacitor is divided into a variable portion and an invariable portion. The capacitance of an internal adjustable capacitor is designed to be equal or close to the fixed capacitance of the external inductive capacitor. The internal adjustable capacitor is used for storing charges having a polarity opposite to that of the invariable portion of the external inductive capacitor in order to neutralize the effect of the invariable portion of the external inductive capacitor. Thus, a charge converter composed of a fully-differential amplifier and feedback capacitors needs only work on the variable portion of the external inductive capacitor, and accordingly the accuracy in subsequent data processing is increased.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: The present invention provides a circuit for driving a display panel using a driving capacitor, comprising an analog-to-digital converter receiving an analog input signal to generate a digital signal, a driving capacitor receiving the digital signal to generate a driving signal for the display panel, and a switching circuit in response to a switching signal, selectively coupling the analog-to-digital converter to the driving capacitor for transmission of the digital signal and coupling the driving capacitor to the display panel for transmission of the driving signal. Thus, the circuit area needed for a source driver processing images of large bit number is reduced, which decreases the cost. Further, the power system of the display having a large dynamic range of voltage can be also simplified.

Abstract: The invention provides a capacitive touching apparatus, which includes at least an equivalent capacitor module, a first comparator, a first reference current generator, a first detection capacitor module and a selection switch module. The equivalent capacitor module receives a periodic driving signal and produces an output voltage according to the driving signal. The first comparator compares the output voltage with a first reference voltage and thereby produces a first comparison result. The first reference current generator produces a first reference current and a second reference current according to a base current, in which the first reference current generator decides whether to respectively output the first reference current and the second reference current according to the first comparison result, and the first reference current is output to the equivalent capacitor module. The first detection capacitor module produces a first detection output signal according to the second reference current.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to oscillate at an oscillation frequency higher than the frequencies of interest in the input signal. The loop includes a filter (160) for attenuating the oscillation signal to ensure that the amplification and phase shifting element (170) can provide amplification for the input signal. The input signal is integrated and the integrated signal perturbs the zero crossings of the oscillation signal.

Abstract: A common mode control circuit (400) for generating a control signal indicative of a common mode signal in first and second signals of a differential signal pair comprises a first charge control means (300) for varying, dependent on polarity of the first and second signals with respect to a threshold, charge on a capacitive element (250, 260, 270). The first charge control means (300) is operable to, in response to the first and second signals both switching polarity simultaneously from opposite polarities, maintain a direction of flow of the charge. The first charge control means (300) can be operable to, in response to the first and second signals both switching polarity simultaneously from opposite polarities and the flow of charge being zero, maintain the flow at zero.

Abstract: A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal.

Abstract: An arrangement for charge integration comprises an input (1) for the provision of a charge-dependent signal and an integrator (30) to integrate a signal present at its input. In addition, a coupling circuit (20) that can adopt at least two operating states is provided to couple the input (1) to the integrator (30) which has a temperature-dependent coupling characteristic. A correction circuit (10) that can be operated by a clock signal is coupled to the input (1) in order to transfer a quantity of charge, and has a temperature characteristic that is derived from the coupling characteristic of the coupling circuit (20).

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: A capacitor interface circuit is provided. A capacitor under test (CUT) is divided into a variable portion and an invariable portion, and the capacitance of an offset capacitor is designed to equal to or close to the fixed capacitance of the CUT. The offset capacitor is used to store the charges opposite to the invariable portion of the CUT for neutralizing the effect of the invariable portion of the CUT. Thereupon, the charge converter composed by the fully-differential amplifier and the feedback capacitors only responses for the variable portion of the CUT so as to increase the accuracy of the follow-up data processing.

Abstract: An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.

Abstract: A control circuit and a conversion circuit. The control circuit may be configured to generate an analog control signal in response to a digital control signal. The conversion circuit may be configured to generate a capacitance signal in response to the analog control signal.

Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.

Abstract: A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator.