Abstract: In order to reduce capacitance of a feedback section of an operational amplifier provided in a semiconductor integrated device, an active filter includes an operational amplifier in which a plurality of capacitive elements are connected between (i) an output terminal and (ii) an inverting input terminal or an input terminal. This arrangement does not require any special technique and amendment of an ordinary integrated circuit process. Further, this arrangement ensures small capacitance in the feedback section of the operational amplifier, while preventing deterioration in S/N ratio, and increases in switching noise and power consumption.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: An adjustable filter, particularly for use as an antialiasing filter in digital telecommunications networks, includes adjustable capacitors which determine frequency response for the purpose of accurate alignment with a particular cut-off frequency. The active filter includes, in line with the invention, a control device with a measuring device for ascertaining the actual cut-off frequency of the filter. On the basis of the ascertained actual cut-off frequency of the filter and the information about the nominal cut-off frequency which is to be set, an adjustment parameter for the adjustable capacitor is selected from a memory arrangement. This adjustment parameter is used to adjust the adjustable capacitor such that the desired nominal cut-off frequency is obtained and, at the same time, the alignment is performed to achieve the nominal cut-off frequency with sufficient accuracy.

Abstract: The present invention relates to digital to analog converters, and especially but not exclusively to switched capacitor digital to analog converters (DACs) for digital audio signals. The present invention provides a switched capacitor DAC for converting a digital signal and comprising a feedback capacitor coupled between an input and an output of an operational amplifier; a charging capacitor and a switching arrangement arranged during a charging period to couple a first side of said charging capacitor to a first reference voltage or a second reference voltage dependent on said digital signal, the switching arrangement further arranged during said charging period to couple a second side of the charging capacitor to the second reference voltage or the first reference voltage in anti-phase to the reference voltage coupled to said first side of the charging capacitor; the switching arrangement further arranged during a settling period to couple said charging capacitor to said feedback capacitor.

Abstract: A resampler filter for use in an analog phase-locked loop has a charge pump and one or more switched capacitors switched by signals derived from a voltage controlled oscillator in the phase locked loop.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. In one embodiment, the modulation system includes a switched excitation source for exciting the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the input voltage step to the integrator to form an input charge. A reference charge packet is generated in a data dependent manner and coupled to the integrator simultaneously with the input charge. The integrator integrates charge associated with the sum of the input charge and the reference charge, when applied. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: An offset correction analogic circuit capable of compensating the offset of a digital baseband is described. The circuit comprises analog means to receive an output differential signal issued from a differential signal path. The differential signal path may be a baseband filter as used in digital communication systems. The baseband filter inputs an input differential signal having an offset to be compensated. The output differential signal is fed into an analog integrator to generate a pulsed signal either on a first output line or on a second output line according to the polarity of the output differential signal. The pulsed signal is then integrated into a switched capacitor and a differential compensation offset signal is issued. The frequency of the pulsed signal is preferably proportional to the voltage value of the output differential signal. The compensation offset signal may be summed with the input differential signal into a summing circuit.

Abstract: In a high-pass (mirrored) integrator structure that employs chopper modulation, the input and output of the mirrored integrator are connected to the input and output ports of the operational amplifier, bypassing the chopper stabilization modulators. The mirrored integrator can be used in sigma-delta analog-to-digital converters.

Abstract: Differential processing systems are provided that reduce even-order harmonic energy. The reduction may be selectively converted to, for example, random noise. This effects a tradeoff for processing systems that can afford to accept some increase in noise to thereby gain the benefits of reduction in even-order harmonic energy. In one system embodiment, first and second signal portions of a differential signal are respectively processed along first and second signal paths in a first processing mode and along the second and first signal paths in a second processing mode. The modes are selected to perform the desired conversion of even-order harmonic energy. In another system embodiment, first and second signal portions of a differential signal are processed along first and second signal paths in a first processing mode and inverted versions of these signals are processed along the first and second signal paths in a second processing mode. In addition, output signals are inverted in the second processing mode.

Abstract: A method of self-calibrating a modulator includes at least one integrator likely to incur a phase error may include reading a pulse response of the modulator, calculating a phase error parameter of the at least one integrator, and calibrating the phase error parameter. In addition, the calibration may provide a count of pulse response samples above suitable threshold values, as well as a change in the value of a capacitor associated with the integrator based upon the sample count.

Abstract: A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.

Abstract: A circuit is provided which is adapted to compensate for the inherent parasitic capacitance which is implicit in switched capacitor circuits. By shielding the parasitic capacitance to a common node of the circuit and then connecting this shield to a voltage source that tracks the voltage change at the input to an amplifier, the present invention provides a bootstrapping effect that enables a minimization of the effect of the parasitic capacitance. The invention also provides a circuit that is adapted to compensate for curvature in the output of a switched capacitor bandgap reference.

Abstract: A switched capacitor circuit includes a capacitor; a switch element for selectively coupling a first node to a second node according to a control signal, wherein the first node is coupled to the capacitor; and a charge circuit coupled to the first node for coupling the first node to a third node and for controlling a first voltage difference across the first switch element in the off-state to be greater than a charge voltage. By ensuring the charge voltage is large enough to minimize a parasitic capacitance of the switch element, the clock feedthrough effect is eliminated, the locking period of the VCO is shortened, and the phase noise of the VCO is minimized.

Abstract: A switched-capacitor sample/hold circuit and method having reduced slew-rate and settling time requirements provides for lower-cost and/or lower-power implementation of sample/hold circuits and/or reduced error due to amplifier characteristics. The switched-capacitor sample/hold circuit incorporates a pair of capacitors that are alternatively and mutually-exclusively switched between an input sample position and an amplifier hold position, providing a dual sampled amplifier output signal that has reduced transitions at each sample interval. An alternative embodiment of the sample/hold circuit incorporates a fully-differential amplifier having a differential input and a differential output. Four capacitors are employed forming two of the dual sampled switched-capacitor circuits, one in each negative feedback path (inverted output to non-inverting input, non-inverted output to inverting input) of the amplifier.

Abstract: A first switch element selectively connects a first node being connected to a capacitor to a second node according to a first control signal. A precharge circuit is connected to the first node for precharging the first node to a precharge voltage for a predetermined time period when the switched capacitor circuit is switched off. The precharge circuit includes a second switch element for selectively connecting a third node to the first node according to a second control signal; a precharge switch element for selectively connecting the precharge voltage to the third node according to the first control signal; and a delay unit for delaying the first control signal to generate the second control signal. In this way, the clock feedthrough effect is minimized and the capacitance of a varactor formed by the first switch element in the off-state is stabilized during the VCO locking period.

Abstract: A transmit and receive protection circuit for use in a communication system is disclosed. The protection circuit uses a four-diode gate in which the currents through an input portion and an output portion of the diode gate are individually controlled by resistors located in their respective portions. This arrangement allows the DC currents through each portion to be independently controlled. By using resistors to independently control the DC currents through each portion of the diode gate, better control over the individual DC currents can be achieved, leading to effective AC resistances which are more predictable. This arrangement results in a predictable low loss protection circuit at a minimal expense.

Abstract: A switch capacitor amplifier using a “bottom plate sampling” type arrangement in the feedback network to mitigate the reduction in linearity due to feedback switch charge injection. The switch (18A) connecting the feedback capacitor (Cf) to the opamp (15) input is opened prior to the switch (19A) connecting the feedback capacitor (Cf) to the output such that the charge injected into the opamp input nodes come from the switch connected to the opamp input, and is independent of the signal value to the first order as the switches are at the opamp input common mode voltage.

Abstract: A method for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. A synchronized clock signal is supplied to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The frequency of the clock signal can be changed dynamically depending on the analog function to be achieved.

Abstract: A bit-and-one-half analog to digital converter comprises a switched capacitor circuit, including an opamp, that receives an analog input voltage and generates a residual analog output voltage. The switched capacitor circuit samples the analog input voltage during a sampling phase and generates the residual analog output voltage during an integration phase. A comparator generates a digital output based on the analog output voltage generated by the switched capacitor circuit. A current source communicates with the opamp and is operable to supply a first bias current to the opamp during the sampling phase and a second bias current that is greater than the first bias current to the opamp during the integration phase.

Abstract: One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.

Abstract: A new method to reduce switching noise on an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a power supply, a ground, and a plurality of switchable capacitors. Each switchable capacitor is connected from the power supply to ground. The operating mode of the integrated circuit device is tracked. An optimal capacitance value is selected based on the operating mode. A set of switchable capacitors from the plurality of switchable capacitors is selected to thereby connect the optimal capacitance value from the power supply to ground.

Abstract: A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

Abstract: A calibrated RC filter (4) includes a fully differential calibration circuit (10) and finite state machine (8) for determining processing variations in the resistive and capacitive components of a RC filter (6). The finite state machine controls tunable capacitors (7) in the RC filter (6) according to the results of the calibration. In order to provide a symmetrical coverage range, an asymmetrical correction code is used for the nominal case.

Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

Abstract: Embodiments of the present invention relate to a switched-capacitor filter which comprises a first stage which itself comprises a first switched capacitor, a second stage which itself comprises a second switched capacitor, a switched capacitive element that couples the output of the first stage to the input of the second stage, and a non-switched capacitive element coupled from the output of the second stage to the input of the first stage to provide damping of the switched-capacitor filter. Both stages are implemented as inverting analog amplifiers and the filter is especially well suited to semiconductor manufacture. The switched capacitor filter is implemented as part of a user module in a programmable system on a chip, or PSoC.

Abstract: A system for measuring output voltage from a photodetector. The system includes a photodetector that generates a photodetector output signal, a ramp generator that generates a ramp signal and a comparator that outputs a signal level based on which of the two signals is larger. The voltage level of the output of the phototransistor determines how long it will take for the ramp voltage to catch up and cross over the phototransistor voltage. The crossover time determines the width of an output signal and is directly proportional to the voltage level. A microcontroller can then determine the pulse width by multiple samplings and therefore determine photodetector voltage.

Abstract: A switched capacitor circuit having an integrator, a switch, a capacitor, a field effect transistor, and a network. The switch is connected to the integrator. The capacitor is connected to the switch. The field effect transistor is connected to the capacitor. The network is connected to a gate terminal of the field effect transistor. The network is configured to control a resistance of the field effect transistor in response to variations in an input signal voltage received at the field effect transistor.

Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.

Abstract: A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Abstract: An integration circuit includes an input node for receiving an input charge, an integrator having an input terminal coupled to the input node, an output terminal and a first charge storage device coupled between the input and output terminals, an intermediate node coupled between the input terminal and ground, a second charge storage device having a first terminal coupled to the intermediate node and a second terminal coupled to an output node of the integration circuit and an isolation device coupled between the integrator and the second charge storage device for selectively isolating the integrator from the second charge storage device. During a first phase of operation, the isolation device is activated and isolates the integrator from the second charge storage device, and the input charge received on the input terminal of the integrator is stored on the first charge storage device.

Abstract: A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in an order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect. The subthreshold and leakage currents passing through the largest switch elements are blocked by the use of an additional switch element to isolate the largest switch element.

Abstract: A sample-and-hold amplifier circuit has a switch, provided between an operational amplifier stage and an inverting amplifier stage, for connecting or cutting off the connection of the operational amplifier stage and the inverting amplifier stage. During the first operation phase (&phgr;1), the first and second switches are switched to the &phgr;1 side, the third switch is conductive, and the switch for connecting or cutting off the connection is nonconductive. Thus, sampling can be carried out so that first and second capacitors are charged by predetermined electrical charges. During the second operation phase (&phgr;2), the first and second switches are switched to the &phgr;2 side, the third switch is nonconductive, and the switch for connecting or cutting off the connection is conductive.

Abstract: A switched-capacitor integrator eliminates noise caused by the switching of an input signal. For this purpose, the integrator includes a switched-capacitor unit for providing a capacitor with one of a first and a second input voltage in response to clock signals, a reference voltage providing unit for receiving a reference voltage and outputting an amplified reference voltage, a switching noise eliminating unit for maintaining an output of the reference voltage providing unit at a stabilized voltage level, an operational amplifying unit for receiving an output of the switched-capacitor unit as its negative input and the output of the reference voltage providing unit passed through the switching noise eliminating unit as its positive input and a feedback capacitor for feeding back an output of the operational amplifying unit to the negative input.

Abstract: A signal processing circuit outputs an output signal corresponding to a pulse width of an input pulse signal. This signal processing circuit comprises means for accumulating pulse widths of the input pulse signal for a predetermined period of time, and means for outputting the output signal corresponding to the accumulated pulse width. Each of these pulse widths has one of positive and negative polarities.

Abstract: A switched capacitor current reference circuit generates an almost constant reference current across the parameters of process, voltage and temperature. A reference voltage is generated within the circuit, which eliminates the need for an external reference voltage. The reference current is generated by applying the reference voltage across a resistor emulated with a pair of switched capacitor circuits.

Abstract: A first operational amplifier receives a reference voltage at one input terminal, a first transistor is connected between a first power source line and the first operational amplifier, a second transistor is connected between the first power source line and the first operational amplifier, a resistor is connected between the first transistor and a second power source line, a first switch is connected to the second transistor, a variable capacitor connected between the first switch and the second power source line, a second switch is connected the variable capacitor and the second power source line, a second operational amplifier is connected to the variable capacitor and the reference voltage, a third switch is connected to the second transistor, a load is connected between the third switch and the second power source line, and a control circuit is connected to the first to third switches.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of the first and second capacitors. In operation, the attack path is activated by alternately closing the first and second switches to sample the input signal and generate an output voltage at the third capacitor indicative of the peak voltage value of the input signal. The second circuit path is activated by alternately closing the third and fourth switches to decrease the output voltage at the third capacitor.

Abstract: A switched capacitor amplifier circuit includes an operational amplifier; a plurality of switch circuits; a plurality of capacitors; and two input terminals; in which a standard voltage and a reference voltage are provided, and noise components of the standard voltage and the reference voltage are made in phase to reduce noises caused by offset voltage adjustment.

Abstract: A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. The modulation system also implements correlated double sampling to provide low noise and highly accurate analog-to-digital conversions. In one embodiment, the modulation system includes an excitation source for providing a switched current to the input sensor and generating an input voltage step in response, and an integrator including an input capacitor, an amplifier and an accumulation capacitor. The input capacitor AC couples the analog input signal to the integrator. The integrator is controlled by switches operating in complementary state for enabling correlated double sampling operation or enabling data dependent charge accumulation operation. The modulation system generates an output data stream exhibiting a ones density proportional to the magnitude of the average input voltage step.

Abstract: A buffered bootstrapped input switch employs cancelled charge sharing for use in high performance sample and hold switched capacitor circuits especially useful for implementing, for example, an analog-to-digital converter (ADC) or amplifier circuit front end sampling network, among others. A scheme is employed for estimating the charge loss from the bootstrapping capacitor to the gate of the bootstrapped input switch, storing the estimated charge loss on a small capacitor, buffering the small capacitor, and then adding the estimated charge loss in series to the bootstrap capacitor, to provide an almost ideal bootstrap network.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.

Abstract: A filter circuit. In one embodiment, the filter circuit includes a continuous time (CT) filter, a switched capacitor (SWC) filter, and an SWC integrator. The CT filter is coupled to receive an input signal from an external source. The CT filter may be a low-pass filter. The SWC filter is coupled to receive an output signal from the CT filter, and provide an output information signal. The SWC filter may also be a low pass filter. A feedback loop may be present between the output of the SWC filter and the input of the CT filter. The SWC integrator samples the output signal from the SWC filter and provides an output signal to the CT filter. The output signal is combined with the input signal to the CT filter. A D.C. offset may be substantially removed from the information signal provided by the output of the SWC filter.

Abstract: Tuning of a filter circuit is accomplished by determining a real RC time constant value for the filter circuit, then comparing the real RC vale to a predetermined RC value. If the real RC value does not match the predetermined RC value, the real RC value is varied (e.g.

Abstract: Power available to an amplifier is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing could normally occur and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in particular interval. A control circuit provides switching of the current mirrors in a way which minimizes disruption of amplifier operation.