Abstract: An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects.

Abstract: An integrator circuit is provided in the present invention, which utilizes a first capacitor and a first switching unit to sample an input signal and carries out distribution of charges between the first capacitor and a second capacitor. The second capacitor is larger than the first capacitor in capacitance. The integrator circuit transmits the charges stored in the second capacitor to a node of the first capacitor which is coupled to a ground previously. Accordingly, a direct current voltage level of the first capacitor may increase, facilitating an increase in a direct current voltage level at the second capacitor. Thereby, the accuracy and linearity of the integrator circuit may improve.

Abstract: An integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window. The circuit includes a plurality of integration paths each corresponding to an integration operation. The integration paths share a same voltage/current converter and a same first switching mechanism for switching a signal to be integrated at an input of the converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving a resulting current via a second switching mechanism for selecting the path.

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).

Abstract: A filter circuit includes a voltage-current conversion portion that converts a voltage signal input to an input terminal to a current signal, a first capacitor unit formed by a plurality of capacitors, and in which a current signal output from the voltage-current conversion portion is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, a second capacitor unit formed by a plurality of capacitors, and in which a current signal output from the first capacitor unit is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, and a plurality of connection nodes that respectively connect a given capacitor in the first capacitor unit and a capacitor in the second capacitor unit.

Abstract: A switched capacitor integrator circuit is disclosed. The switched capacitor integrator circuit comprises an inverting switched capacitor integrator circuit, and a non-inverting switched capacitor integrator circuit connected to the inverting switched capacitor integrator circuit. A sampling capacitor of the inverting switched capacitor integrator circuit is shared by the non-inverting switched capacitor integrator circuit.

Abstract: The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.

Abstract: A capacitance switching element includes first and second capacitors connected in series by transistors. The gates of the transistors are biased by a first signal through one set of resistors, and the sources and drains are biased by a second signal through a second set of resistors. The signals are level-shifted and may be complimentary. To turn the element ON, the first signal may be set to VDD and the second signal may be set to zero. To turn the element OFF, the first signal may be set to a multiple of VDD/2 and the second signal may be set to the multiple plus one of VDD/2. When the element is used in an oscillator tuning circuit, the voltage stress on the transistors is reduced and the transistors may be fabricated with thin oxide. The oscillator may be used in a transceiver of a cellular access terminal.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or to the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. An input terminal of the unit-gain amplifier is coupled to the second selecting terminal of the input selector.

Abstract: A low-pass filter of the present invention comprises a plurality of filter units and a regulation unit. The filter units are coupled in series with each other and receive an input signal to filter the input signal for generating an output signal. The regulation unit is coupled to the filter units to regulate voltage levels of the filter units. The low-pass filter of the present invention can be integrated within the integrated circuit and reduce the prime cost.

Abstract: A configurable switched capacitor block includes a switched-capacitor (SC) sampling circuit, a fully differential amplifier, an SC feedback circuit, and a comparator. The SC sampling circuit is coupled to receive an input signal and to selectively generate a sampled signal to a differential input of the amplifier. The SC feedback circuit is coupled between the differential inputs and the differential outputs of the amplifier to selectively control a feedback of the amplifier. The comparator is coupled to the differential outputs of the amplifier to generate an output signal. The configurable switched capacitor block has multiple modes of operation which are selectable by programming the SC sampling circuit and the SC feedback circuit.

Abstract: A semiconductor integrated circuit includes an integrating circuit comprising a variable resistance, an integration capacitance and an amplifier; a switched capacitor connected with the amplifier in parallel to the variable resistance; and an adjusting circuit configured to adjust a resistance value of the variable resistance. The integrating circuit generates a control signal of a voltage based on a first time constant determined based on the resistance value of the variable resistance and a capacitance value of the integration capacitance, and a second time constant determined based on a capacitance value of the switched capacitor and the capacitance value of the integration capacitance. The adjusting circuit adjusts the resistance value of the variable resistance based on the control signal.

Abstract: A photodetecting device 1 includes a photodiode PDm,n, a switch SWm,n for the photodiode, an integrating circuit 12m, and a noise removing circuit 13m. The integrating circuit 12m accumulates in a capacitor Cfk an electric charge input from the photodiode PDm,n through the switch SWm,n for the photodiode, and outputs a voltage value according to the amount of the accumulated electric charge. The noise removing circuit 13m includes an amplifier A3, five switches SW31 to SW35, four capacitors C31 to C34, and a power supply V3. The noise removing circuit 13m takes in a voltage value that is output from the integrating circuit 12m at a time where the switch SW31 is first turned from a closed state to an open state, and after the time, outputs a voltage value according to a difference between the voltage value that is output from the integrating circuit 12m and the voltage value previously taken in.

Abstract: An arrangement for charge integration comprises a charge-generating circuit (2) that provides a charge-dependent signal, and a coupling circuit (20) comprising a first and a second transistor (T1, T2). The first transistor (T1) can be controlled in dependence on the charge-dependent signal. The second transistor (T2) is configured to forward the charge-dependent signal in dependence on a control signal provided by the first transistor (T1). The forwarded charge-dependent signal is integrated by an integrator (30).

Abstract: A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.

Abstract: A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (Vref, Vcm,ref) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

Abstract: A switched capacitor circuit includes: an operational amplifier; a first capacitor; a first switch that charges the first capacitor by connecting the first capacitor between an inverting input terminal and an output terminal of the operational amplifier, and discharges the first capacitor by disconnecting the inverting input terminal and the output terminal of the operational amplifier in a predetermined period; and a first output terminal that outputs an output voltage of the switched capacitor circuit, wherein after a predetermined period from a time when the first switch connects the first capacitor between the inverting input terminal and the output terminal of the operational amplifier, the first output terminal and the output terminal of the operational amplifier are connected to each other.

Abstract: A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps.

Abstract: The invention allows for the realization of a precision current reference or a fully integrated crystal-less precision oscillator by providing a circuit that precisely controls the cyclic charging operation of a switched capacitor. The voltage across the switched capacitor is ramped up and stops at the end of the charge phase at precisely a desired voltage. By using an appropriate network of switches based around a transconductance amplifier, the error voltage between the desired voltage and the voltage across the switched capacitor is amplified by the transconductance amplifier to give an error current. The error current is integrated over time to give an integrated amplified error voltage. By using appropriate feedback, the error voltage can be minimised to give a precise output current whose value depends on a capacitance, a voltage and a frequency.

Abstract: Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.

Abstract: A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

Abstract: Methods and systems for a DC offset correction loop for a mobile digital cellular television environment are disclosed. Aspects of one method may include removing at least a portion of a DC offset from output of an amplifier. The DC offset may be removed from a single stage amplifier, or from each stage of a N stage amplifier, where N may be an integer. The DC offset may be removed by using second differential signals generated from first differential signals, where the second differential signals may be communicated to inputs of the amplifier. The first differential signals may by a first circuit that integrates outputs of the amplifier. The first circuit may perform the integration using a variable corner frequency that may be adjusted by changing a resistance of at least one variable resistor in the first circuit.

Abstract: A switched-capacitor (SC) circuit relating to summing and integration algorithms is provided. The SC circuit submitted by the present invention benefits from better closed-loop bandwidth performance because of combining positive and negative feedback loops of a high gain amplifier. In addition, the SC circuit submitted by the present invention not only provides differential output signal obtained by a summing (or integration) algorithm of input voltage signals and reference voltage signals and forward drives such differential output signal to a next stage SC circuit, but also provides flexible and accurate coefficient design for every individual input and reference voltage signals in the said algorithm. Besides, if the circuit manner of alternate resetting is disabled or removed, the SC summing circuit submitted by the present invention can serve as an SC integration circuit.

Abstract: A configurable switched capacitor block includes a switched-capacitor (SC) sampling circuit, a fully differential amplifier, an SC feedback circuit, and a comparator. The SC sampling circuit is coupled to receive an input signal and to selectively generate a sampled signal to a differential input of the amplifier. The SC feedback circuit is coupled between the differential inputs and the differential outputs of the amplifier to selectively control a feedback of the amplifier. The comparator is coupled to the differential outputs of the amplifier to generate an output signal. The configurable switched capacitor block has multiple modes of operation which are selectable by programming the SC sampling circuit and the SC feedback circuit.

Abstract: A correlated double sampling circuit has a sampling capacitor equally divided into a plurality of portions. In the correlated double sampling circuit, an input signal is sampled at a plurality of sampling points and an averaging switch is closed to obtain an average value of a plurality of sampling values obtained by sampling. High frequency noise superimposed on the input signal is thus reduced and a difference between the average values of the plurality of sampling values obtained by sampling is output.

Abstract: A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.

Abstract: A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter.

Abstract: A circuit arrangement having a signal input configured to be supplied with a voltage signal; a first operational transconductance amplifier (OTA) having a voltage input that may be coupled to the signal input; at least one second OTA having a voltage input that may be coupled to the signal input; and at least one output capacitor which may be coupled to an output of the first OTA and to an output of the at least one second OTA, wherein an identical potential is set at the outputs of the first OTA and of the at least one second OTA.

Abstract: An apparatus for generating an oscillating signal that includes a circuit to accelerate the time in which an oscillating signal reaches a defined steady-state condition from a cold start. The apparatus includes an oscillating circuit to generate an oscillating signal; a first circuit to supply a first current to the oscillating circuit; and a second circuit to supply a second current to the oscillating circuit, wherein the first and second currents are adapted to reduce the time duration for the oscillating signal to reach a defined steady-state condition. The apparatus may be useful in communication systems that use low duty cycle pulse modulation to establish one or more communications channels, whereby the apparatus begins generating an oscillating signal at approximately the beginning of the pulse and terminates the oscillating signal at approximately the end of the pulse.

Abstract: An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n?1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n?1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.

Abstract: An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects.

Abstract: Provided is voltage/current conversion circuit including: first and second capacitors; first and second resistors each connected to input terminal; first and second current sources; third and fourth resistors connected to current sources; differential amplifier for controlling the current sources; control unit for performing control, in first state, the input terminal is connected to the first and second capacitors; one input of the differential amplifier is connected to the first resistor and output of the first current source; the other input of the differential amplifier is connected to the second resistor and output of the second current source, and in second state, the second capacitor is connected between the output of the first current source and the one input of the differential amplifier, the first capacitor is connected between the output of the second current source and the other input of the differential amplifier.

Abstract: A multi-channel integrator includes a first switch, a second switch, and a plurality of integration units. First terminals of the first and second switches receive a first reference voltage. Each of the integration units includes an operational amplifier (OP-AMP), a feedback switch, a third switch, a fourth switch, and a feedback capacitor. A second input terminal of the OP-AMP receives a second reference voltage. Two terminals of the feedback switch are respectively coupled to a first input terminal and an output terminal of the OP-AMP. First terminals of the third switch and the fourth switch are respectively coupled to the first input terminal and the output terminal of the OP-AMP. A first terminal of the feedback capacitor is coupled to the second terminals of the first and the third switches. A second terminal of the feedback capacitor is coupled to the second terminals of the second and the fourth switches.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.

Abstract: An integrated circuit for a charge pump with a charge stage and a pump stage and a single High-Voltage PMOS (HVPMOS) transistor as the main switch for each stage and two times two minimum HVPMOS transistors in series as a bulk switch with fixed bulk connections, where the minimum HVPMOS transistors are smaller sized transistors than the transistors of the main switch. The bulk of the main switch is switched synchronously to the voltage node of the HVPMOS transistor of the main switch to force the bulk voltage (VB) to be equal or larger than either the source voltage (VS) or the drain voltage (VD). Two non-overlapping clock signals are used to trigger the HVPMOS transistors of the charge and pump stage.

Abstract: The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.

Abstract: An integrated circuit includes a storage component, a voltage stabilizer circuit with an input configured to receive an input voltage and an output configured to provide an output voltage, and a load. The load is coupled to the output of the voltage stabilizer circuit. The integrated circuit is operable in a first and second operating state. In the first operating state, the storage component receives an input voltage and in the second operating state the input voltage is provided to the input of the voltage stabilizer circuit.

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract: An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

Abstract: A second order analog filter based on transconductance amplifiers and capacitors (gmC) has good linearity at low operating voltage by using linear active transconductance amplifiers with gains determined by physical resistors and output current mirrors in a positive feedback configuration to allow the implementation of complex poles in the transfer function.

Abstract: Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit. When the comparator circuit samples the input voltage, the second amplifier circuit conducts feedback and increases a gain to cancel the offset. Also, when the gain of the amplifier circuit is made lower than the gain of the second amplifier circuit, and the comparator circuit compares the input voltage, the comparing operation can be conducted at high speed by separating the amplifier circuit from the feedback of the second amplifier circuit.

Abstract: A sample-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. A multiple segment ramp waveform generator is used in the sample-data analog circuits. The ramp waveform generator includes an amplifier, a variable current source, and a voltage detection circuit coupled to the current source to control the change in the amplitude of the current. The ramp generator produces constant slope within each segment regardless of the load condition. The sample-data analog circuit also utilizes variable bandwidths and thresholds.

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout?), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout?) at a desirable level.

Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout?), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout?) at a desirable level.

Abstract: A filter device is disclosed that includes a switched capacitor circuit.

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.