Abstract: A method and apparatus for recovering from an unstable oscillating condition in a delta-sigma A/D converter modulator circuit. A modulator circuit is disclosed having integrator stages, each having a first switch across the input terminals of the integrator stage and a second switch across the output terminals of the integrator stage. In another embodiment of the invention, the integrator stage comprises a differentially structured operational amplifier having a first restore switch coupled across the input terminals, a second restore switch across the output terminals, and four disconnect switches, one each coupled between the operational amplifier inputs and ends of the first restore switch and between the operational amplifier outputs and ends of the second restore switch. In operation, an unstable condition detector monitors an output of the A/D modulator circuit and generates a restore signal to the integrator stages upon detection of an unstable condition.

Abstract: Power available to an integrator circuit is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. The techniques are particularly useful when applied to clocked integrator circuits.

Abstract: An electronically trimable capacitor (10) having a plurality of branch circuits (30) each including a capacitor (32) which may be selectively controlled by a switch (34) to contribute or not to the net capacitance exhibited by the trimable capacitor (10). Operation of the switches (34) is under direction of an interface (36), which can receive a program signal containing digital instruction for programming via a program terminal (22). An optional memory (38) permits storing a program of states for the switches (34), so that the interface (36) maybe instructed to reset the switches (34) and thus cause the trimable capacitor (10) again provide a previously programmed net capacitance, say, in the event of power on or a power loss. An optional enable terminal (24) provides protection against inadvertent programming.

Abstract: A switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a chopper stabilized amplified filter circuit which amplifies and low pass filters its input data signal to produce an output signal with an out of band signal frequency component which is at the chop signal frequency and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. An output switched capacitor filter circuit which is synchronized with the chopper stabilized amplified filter circuit filters this signal with a stopband filter frequency response that virtually eliminates such out of band signal frequency component. When used in a closed feedback loop, this filtered signal is used to generate an offset compensation signal that corresponds to the residual offset within the output signal resulting from the amplifying and filtering of the input data signal.

Abstract: A switched capacitor circuit is described that uses two switchable operational amplifiers that operate in parallel and in alternate clock phases. In a preferred embodiment of the invention, the two operational amplifiers may be implemented by a single two-stage operational amplifier having a common input stage and two switchable output pairs. The novel switched capacitor circuit may be used in any application that uses a conventional switched capacitor circuit, such as an integrator and a filter means.

Abstract: An amplifier for measuring the charge stored on a source capacitor having a capacitance Cpd. The amplifier includes an opamp having a signal input, reference input and output; the first terminal of the source capacitor is connected to the signal input. The amplifier includes a reset switch for shorting the signal input and the output of the opamp, and a capacitive network. The capacitive network connects the signal input and the output of the opamp, and provides a capacitance of CT between the signal input and the output of the opamp wherein CT<Cpd. The capacitive network is constructed from a plurality of component capacitors. Preferably each component capacitor has a capacitance greater than or equal to Cpd. In one embodiment of the invention, the capacitive network includes first, second, and third component capacitors, each capacitor having first and second terminals.

Abstract: A sample and hold in a switched capacitor circuit with frequency shaping. The sample and hold does not require a pair of large area, power-consuming operational amplifiers and, as such, consumes less power and less area. Preferably, the sample and hold is operable in four different states wherein a different set of switches are closed in each of the four states. The switches are controlled by two clock signals and a plurality of signals derived from the two clock signals, such as four signals derived from the two clock signals. Desirably, the sample and hold with frequency shaping is configured to sample a voltage across a first capacitor while a second capacitor is disconnected from said first capacitor, and is configured to thereafter connect the second capacitor to the first capacitor and possibly discharge at least a portion of a charge held in the first capacitor into the second capacitor.

Abstract: In accordance with a specific embodiment of the present invention, a system is disclosed having an analog to digital converter and control module. The analog-to-digital converter includes an analog input, digital output, and control input. The control input of the analog-to-digital converter is connected to a pulse width modulated output of the control module which provides an offset pulse width modulated signal. During a first portion of the offset pulse width modulated signal a sampling capacitor is charged. During a second portion of the offset pulse width modulated signal an integration capacitor is charged.

Abstract: A digitally programmable switched capacitor gain and attenuation circuit that uses the same switched capacitor array for a multitude of different gain and/or attenuation settings with a single operational amplifier is disclosed. With the top plates of the capacitors connected to the operational amplifier input, the unique switching of the bottom plates of the capacitor array elements between three voltages—the circuit output, the circuit input, or a chosen reference voltage such as a power supply midpoint voltage or a ground voltage of the circuit, makes this circuit arrangement's component area smaller and the operational amplifier's design specification less demanding for applications such as a digital camera front end analog processor.

Abstract: With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.

Abstract: Power control for a laser is performed on at least a per-packet basis, rather than a per-pulse basis, and that end-of-life detection may similarly be performed. This is achieved by accumulating the current generated by a photodiode in response to the light signal generated by the laser, subtracting therefrom a preset threshold current which is similarly modulated in response to the data signal used to drive the laser, and comparing the resulting difference to the value prior to having begun accumulating and subtracting. The result of the comparison, which may be filtered, is used to control the driver of the laser or as an indicator, e.g., for use in end-of-life detection.

Abstract: Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maximum delay times without signal attenuation and with delay-to-risetime ratios of up to 102 to 103. A vector array of switched capacitor analog storage elements may be arranged in a ring-buffer topology, with the number of switched capacitor elements ranging from between about 10 and about 105. Two internal counters incremented by a common clock keep track of the variable delay between an input signal and an output signal.

Abstract: Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required.

Abstract: Capacitor voltage coefficient errors are reduced in a lossy integrator by providing oppositely oriented first and second feedback capacitors in a switched capacitor feedback circuit coupled between the output and a summing conductor connected to an inverting input of an operational amplifier. During a first clock signal, terminals of the first feedback capacitor are coupled to a reference voltage by closing first and second reset switches and the second feedback capacitor is coupled between the inverting input and the output conductor by closing first and second sampling switches. Then, during a second clock signal the terminals of the second feedback capacitor are coupled to the first reference voltage by closing third and fourth reset switches, and the second feedback capacitor is coupled between the inverting input and the output by closing third and fourth sampling switches.

Abstract: An integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency. A current mirror circuit generates a primary current and a mirrored current. Under the control of a clock signal, a switched capacitor circuit uses the mirrored current to constantly accumulate charges on primary capacitor while also alternately sharing such charges with and then discharging one of two additional capacitors. The magnitude of the current drawn by the switched capacitor circuit is a factor of the junction area of a diode and absolute temperature. To maintain equality of the primary and mirrored currents, a node voltage within the current mirror circuit is monitored by a bias circuit which provides a bias signal for controlling the current mirror circuit.

Abstract: A switched-capacitor cosine filter circuit includes a differential amplifier and a switched-capacitor circuit. A set of control signals cause the switched-capacitor circuit to selectively couple the inputs and output of the differential amplifier thereby producing a switched input signal for the differential amplifier. During alternating states of the control signals, the switched-capacitor cosine filter circuit samples the input signal as a noninverting and inverting integrator circuit.

Abstract: An integrator and a filter having offset compensated switched-opamp are implemented in the present invention. In the present invention, offset voltages caused by amplifiers used in a integrator or a filter can be compensated and such circuits can be operated under a low power voltage.

Abstract: Disclosed is a fully differential switched-capacitor integrator which accepts a single-ended or unbalanced input signal and compensates the offset and finite gain of the operational amplifier without an extra converter circuit. The proposed circuit utilizes a special input structure which adds special capacitors to store the offset and the low frequency noise of the operational amplifier. One preferred embodiment implements the switching means as transmission gates using CMOS transistors. Clock feedthrough is prevented by providing two non-overlapping clock phases with a delayed clock each, thus avoiding clock feed-through. The invention provides a good alternative for applications such as low noise filters and sigma delta modulators.

Abstract: A chopper type comparator has one terminal of a first capacitor C1 connected to a connecting point P of a first switch SW1 and a second switch SW2, and an analog input signal A.sub.IN and a reference voltage V.sub.REF are supplied in an alternating fashion. The first capacitor C1, first inverter INV1, second capacitor C2, second inverter INV2, and third inverter INV3 are connected in series in this order. The input and output terminals of the first inverter INV1 are connected via a third switch SW3, and both terminals of the second capacitor C2 are connected via a fifth switch SW5. The input and output terminals of the second inverter INV2 are connected via a fourth switch SW4. The second capacitor 2 can be reset in a short time by the fourth and fifth switches SW4 and SW5.

Abstract: Charge transfer amplifier circuit which is capable of canceling fluctuations in the element characteristics thereof and which conducts highly accurate voltage amplification without the use of a stationary current, and provides a voltage comparator which may be applied to a highly accurate A/D converter which has low power consumption. The charge transfer amplifier circuit is provided with a MOS transistor, a first capacity and a second capacity which are effectively connected to, respectively, the source electrode and the drain electrode of the MOS transistor, a mechanism for setting the region between the terminals of the first capacity and the region between the terminals of the second capacity, respectively, to appropriate predetermined potential differences, and for releasing these, and a mechanism for appropriately externally altering the potential difference between the gate and the source of the MOS transistor. The first capacity is set so as to be larger than the second capacity.

Abstract: With regard to a significant reduction in the tolerance range or margin to be taken into account in the design of a switched-capacitor circuit which is monolithically integrated by means of enhancement-mode insulated-gate field-effect transistors there is provided at least one opamp. This opamp contains a resistor which determines its quiescent current and is realized as a transistor operated in the permanently current-conducting state. An on-chip clock oscillator generates a clock signal. This oscillator is either an RC clock oscillator, whose frequency is determined by an oscillator resistor, which is realized as a transistor operated in the permanently current-conducting state, and an oscillator capacitor, or a current-controlled clock oscillator, whose frequency is determined by the quiescent current of the opamp. At least one capacitor is charged or discharged during operation by the opam via at least one switch in the form of a transistor clocked by the clock signal.

Abstract: A highspeed voltage comparing operation by a voltage comparing circuit is realized while input sampling timing can be made constant. This voltage comparing circuit is mainly arranged by a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a eighth switch, a first capacitor, a second capacitor, a first inverter, a second inverter, a third capacitor, and a fourth capacitor. In this voltage comparing circuit, an input signal voltage is held in the first capacitor and also a reference voltage is held in the second capacitor in an input sampling mode. Then, electron charges stored in these capacitors are redistributed, and the difference voltage between the input voltage and the reference voltage is amplified by two sets of inverters in an amplifying mode. In a latch mode, these first and second inverters are operated as a flip-flop circuit.

Abstract: A switched capacitor wherein one of the plates of the capacitor to be switched is fed with the input signal via a transistor switch receiving as control signal at the gate thereof a pulse train with predetermined frequency. For compensating the parasitic capacitance of the transistor switch, a compensation component is located between the transistor switch and the capacitor to be switched. This compensation component is formed as an incomplete transistor structure, such as only 1/2 of a transistor, has a drain region in common with transistor switch and has an insulated gate. The parasitic capacitance of the compensation component thus is established mainly by the capacitance between the insulated gate and the drain region and thus corresponds to the parasitic capacitance of the transistor switch, whereby complete compensation with optimized charge transfer is achieved.

Abstract: An input switch for use in a switch-capacitor circuit having unified architecture, and a switch-capacitor circuit including such an input switch, an amplifier, a capacitor between the amplifier and switch, and at least one NMOS transistor. The input switch samples an input potential in a sampling mode, receives a reference potential, and includes a transmission gate having a first NMOS transistor. The switch is configured to prevent the transmission gate from passing the reference to the capacitor when the reference is so low that the difference between the sampled input and reference is below an overdrive-causing level, thereby preventing capacitor charge loss which would otherwise lead to overdrive while the switch-capacitor circuit compares the reference with the sampled input.

Abstract: An integrated circuit having a passive circuit component that can be adjusted following the manufacturing process to provide a precise absolute value for resistance or capacitance. A plurality of passive elements are selectively combinable using logic gates to include or exclude each element from a network, wherein the combined value of the included passive elements equals the value of the passive circuit component. The logic gates are set by outputs from a decoder to reduce the required inputs to the chip.

Abstract: A switched capacitor amplifier useful in integrated circuits and capable of low power operation, wherein the amplifier comprises at least one first hold capacitor, at least one second hold capacitor, a transconductance amplifier, first switching circuit for either (a) allowing the first hold capacitor to retain an input voltage, or (b) outputting retained input voltage through the transconductance amplifier, and a second switching circuit for either (a) feeding a voltage obtained by reversing the polarity of voltage retained by the second hold capacitor back to the transconductance amplifier for outputting as output voltage, or (b) allowing voltage retained by the first hold capacitor to be held by the second hold capacitor.

Abstract: A low pass filter includes an input, an output, a storage means, a switching means and a control means. The input receives an input signal. An output signal is generated on the output. The storage means is a sample storage element, for example, a capacitance. A first end of the storage means is connected to the output. The switching means is connected between the first end of the storage means and the input. The switching means, when closed, electrically connects the input to the first end of the storage means. When open, the switching means electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. The capacitance provided by the capacitance means and a pulse width of the switching control signal are selected so that a maximum cutoff frequency of the low pass filter is less than the sampling frequency divided by two.

Abstract: A high-speed regeneration comparator is disclosed in the present invention. The high-speed comparator is consisted of two capacitors and two inverters. A first terminal of a first capacitor is coupled with a reference voltage through a first switch and with an inputting voltage through a second switch. The inputting terminal of a first inverter is coupled with a second terminal of the first capacitor and the inputting terminal of the first inverter is coupled with the outputting terminal of the first inverter through a third switch for feedback signals from the outputting terminal of the first inverter to the inputting terminal of the first inverter. A first terminal of a second capacitor is coupled with the outputting terminal of the first inverter.

Abstract: A logarithmic amplifier is provided with a calibration circuit to allow for current measurement over a wide-dynamic range that includes extremely low current levels in a manner which mitigates or eliminates sensitivity to temperature. Calibration currents are generated by application of a series of voltage ramps of selectable slope to a capacitor. This provides a set of known current levels, selectable over a range of decades, for periodic calibration of the logarithmic amplifier. The selectable calibration currents can also be advantageously used to provide a fixed, known bias current to the input of the logarithmic amplifier to improve the response time of the amplifier for measurement of small sensor currents on the order of 10-100 fA.

Abstract: In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.

Abstract: A technique for resetting state variables of a delta-sigma modulator of an analog-to-digital converter. A switched capacitor impedance is placed in the reset feedback path of an integrator to ensure that the integrator tracks to the proper reset voltage, when reset is initiated in a third-order or higher delta-sigma modulator.

Abstract: A transmitter system having an adjustable monolithic frequency stabilization and tuning internal capacitor circuit. The transmitter system has a transmitter for generating and transmitting a transmitter oscillator frequency signal. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. A variable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The variable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.

Abstract: A comparator circuit and method for comparing first and second inputs. First and second input capacitors are provided for storing first and second voltages indicative of the first and second inputs when the circuit is in a sample phase. A comparator stage coupled to the first and second input capacitors switches from a measure state to one of first and second output states when the comparator circuit is in a hold phase based upon the relative magnitudes of the first and second inputs. Reset circuitry operates to discharge the input capacitors when the comparator stage switches to one of the output states. During a subsequent sample phase, the discharged input capacitors can be rapidly charged to new voltages thereby increasing the operating speed of the comparator circuit.

Abstract: A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit.

Abstract: In a signal input circuit, an input signal integrating circuit integrates an input signal in only a predetermined integration period. A reference voltage integrating circuit integrates a reference voltage in only the predetermined integration period. A differential amplifier circuit amplifies a difference between an output signal of the input signal integrating circuit and an output signal of the reference voltage integrating circuit. The input signal integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the input signal in only the predetermined integration period and thereafter releases the stored charges before the next integration period. The reference voltage integrating circuit may be a charge/discharge type integrating circuit which stores charges corresponding to the reference voltage in only the predetermined integration period and thereafter releases the stored charges before the next integration period.

Abstract: The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

Abstract: A level detector detects an input signal level. A rectifier (210) receives the input signal and provides a rectified signal. A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefiltered signal is decimated (230) and low pass filtered by a lowpass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit (935, 1010) which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.

Abstract: Circuits having switched capacitors that are implemented with T-structures in which one of the three capacitors in the T-structure is implemented with a buffer amplifier configured to receive a control signal (e.g., a control voltage) and to apply a buffered control signal to an active device having a capacitance that is dependent on the control signal level. In one embodiment, the control signal is a control voltage, the active device is a varactor diode, and the circuit is a ladder filter having one or more switched capacitors, each of which is implemented using the T-structure of the present invention. Under the present invention, continuously tunable circuits can be implemented with discrete elements where the circuits can be tuned by changing the control signal in one or more of the switched capacitors, without having to provide a continuously tunable clock.

Abstract: A switchable active filter circuit is formed which employs a ground based switch to direct a portion of a feedback current away from a virtual ground terminal of an operational amplifier, thereby providing enhanced circuit Q and greater phase control at frequencies approaching an octave from the unity gain crossover frequency of an operational amplifier used to form the filter. The circuit employs a switchable feedback tee which includes a first capacitor, a second capacitor, a third capacitor and a switch. The first capacitor and the second capacitor form a first series circuit which is connected from the output terminal to the input terminal of the operational amplifier. The third capacitor and the first switch are connected as a second series circuit which is coupled from circuit ground potential to a junction of the first capacitor and the second capacitor.

Abstract: In an interface circuit connected to a capacitance type sensor having two sets of capacitors C1 and C2 whose capacitances are varied, this interface circuit is equipped with an OP amplifier A1 where a feedback/sampling capacitor C3 is connected between its output terminal and its inverting input terminal; and a holding capacitor C4 connected between a non-inverting terminal of the OP-amplifier A1 and a reference voltage source; one ends of the respective capacitors C1, C2, C3 are connected to the inverting input terminal of the OP amplifier A1; at timing .phi.1 of a switching cycle, the other ends of the respective capacitors C1, C2 are connected to a power source and the capacitor C3 is shortcircuited; at timing .phi.

Abstract: In switch-capacitor systems for extremely low supply voltage, employing a fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal is made possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

Abstract: A switched capacitor filter for applying a filter processing including an integration processing to input analog signals of plural channels on a time shared basis includes an integration sections for sequentially implementing the integration processing for the respective channels on a time shared basis, integrated value storage sections for storing integrated value signals representing results of the integration processing for the respective channels, switches for causing, each time the integration processing for the respective channels is interrupted, an integrated value signal representing result of the integration processing for the particular channel at the time of interruption to be stored in the integrated value storage sections and initializing the result of the integration processing by the integration section and, each time the integration processing for the respective channels is implemented, supplying the integrated value signal for the particular channel from the integrated value storage sections

Abstract: A speed-enhancing comparator with cascaded inverters is disclosed.

Abstract: A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.

Abstract: A chopper comparator for comparing an analog input signal voltage and a comparative reference voltage comprises the following elements. First and second input terminals are provided for receiving the analog input signal voltage and the comparative reference voltage respectively. A first capacitor is provided with a first input side terminal connected through a first switch to the first input terminal. A second capacitor is provided with a second input side terminal connected through a second switch to the second input terminal. A data latch circuit is provided and is connected to first and second output terminals of the first and second capacitors.

Abstract: A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connecting the input of the amplifier through a low impedance path to a point of reference voltage so that when the amplifier is quiescent signals on the bus cannot be fed through the capacitor to turn on the amplifier. A current source and a switchable current sink are connected to the input of the amplifier to change the capacitor to produce the slew rate controlled transitions. Another driver amplifier of the same design but using components of the opposite conductivity type can be used to apply signals of the opposite polarity to the same bus.

Abstract: An object is to obtain a voltage comparator capable of high-accuracy voltage comparison. An input voltage (VIN) and a reference voltage (VREF) are connected to one electrode of a capacitor (C1) through switches (S1) and (S2), respectively. The other electrode of the capacitor (C1) is connected to the input portion of an inverter (INV1). The output portion of the inverter (INV1) is connected to the input portion of an inverter (INV3) and is also fed back to the input through a switch (S3). An inverter (INV11) is further connected in parallel with the inverter (INV1), wherein the input/output characteristics of the inverters (INV1, INV3 and INV11) are set equal.

Abstract: The present invention relates to a control signal generation circuit for telephone charge indicators comprising a capacitor having a first and a second terminals connected to ground through respectively a first and a second switches with the first terminal of the capacitor being also connected through a third switch to a constant current generator which is connected to a positive power supply line with respect to ground. The second terminal of the capacitor is connected to a constant current generator which is connected to a negative power supply line with respect to ground. The first and second terminals are also connected through respectively a first and a second resistance to a circuit node coupled to an output terminal.

Abstract: A charge transfer from signal voltage (U.sub.S) to integrating capacitance (C.sub.O) is accomplished by means of charge transfer capacitance (C.sub.i), an active element (T) and controllable switches (S.sub.61, S.sub.62, S.sub.63, S.sub.64). The operation of the circuit is additionally based on the fact that the charge transfer to the charge transfer capacitance (C.sub.i) is terminated when the transistor (T) is in a current-carrying state and that current flow is ensured by a constant-current element set. These features are combined preferably in such a way that the breaking current of charge transfer is equally great as previously said current of the constant-current element.

Abstract: A MOS switching circuit (1) for providing constant signal-independent gate-to-source voltage at a switching transistor (2) of a differential switched capacitor circuit so that a signal-independent resistance is provided between its source and drain includes a first control transistor (5) coupled between the input (3) and the gate of the switching transistor (2). The gate of switching transistor (2) is also coupled to a first clock phase signal PHI1 and the gate of the first control transistor (5) is coupled to a second, non-overlapping clock phase signal PHI2. A second control transistor (6) is coupled between the input (3) and the second clock phase signal PHI2 and its gate is coupled to the first clock phase signal PHI1. Capacitors (7) and (8) are coupled between the transistors (2, 5 and 6) and the clock phase signals PHI1 and PHI2, respectively.