Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: Systems and methods are disclosed herein to provide low pass filters. For example, in accordance with an embodiment of the present invention, a synchronous low pass filter is disclosed. The filter may be employed, for example, to suppress signal transients in power supply monitoring applications.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: A glitch removal circuit that removes both positive and negative glitches from an input signal includes a delay circuit, a glitch blocking circuit, and a latch circuit. The delay circuit receives the input signal and introduces a delay into it. The glitch blocking circuit is coupled to the delay circuit, and includes two NMOS transistors and two PMOS transistors. The glitch blocking circuit receives the input signal and the delayed input signal and blocks the input signal if there is a glitch in it. The latch circuit is coupled to the output of the glitch blocking circuit. The latch circuit inverts the output of the glitch blocking circuit and stores the output on a continuous basis. The latch circuit provides glitch free signal as the output.

Abstract: A circuit to independently control rise and fall delay edge timing of a signal is achieved. The circuit comprises, first, a first delay element and a second delay element. Each of the delay elements has an input and an output. Each of the inputs is coupled to a common, input signal. Next, an AND function, having two inputs and one output, is used. One of the AND inputs is coupled to the input signal, and another of the AND inputs is coupled to the first delay element output. The AND function output comprises a rise-delayed signal having a controlled rising edge delay between a rising edge of the input signal and a rising edge of the rise-delay signal. Finally, an OR function, having two inputs and one output, is used. One of the OR inputs is coupled to the input signal, and another of the OR inputs is coupled to the second delay element output.

Abstract: A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

Abstract: The present invention discloses a spike free circuit, which comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal. The time shift means shifts input signals, which change logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring. The group of logic gates is connected to the time shift means. The second flip-flop stage is electrically connected to the group of logic gates and triggered by the first edge of the clock signal.

Abstract: A glitch detect filter system is described. The glitch detect filter system produces an output that is not susceptible to glitches. The glitch detect filter system provides a fixed output signal. The fixed output signal relates to the input signal loaded on the rising edge of signal Q1 or signal Q2 as determined by signal Q3. As the output signal is fixed, glitches in the input signal do not affect the output signal.

Abstract: A signal processing circuit and method for measuring the width of an input pulse signal that contains chattering noise. The signal processing circuit converts the input pulse signal into an output pulse signal having no chattering noise by setting and resetting a flip-flop circuit at a timing that is delayed by a predetermined time after the rise and fall in the input pulse signal.

Abstract: A superconducting structure that includes a mesoscopic phase device and a mesoscopic charge device. The superconducting structure further includes a mechanism for coupling the mesoscopic phase device and the mesoscopic charge device so that the quantum state of the mesoscopic phase device and the quantum state of the mesoscopic charge device interact. In another aspect, the superconducting structure includes a mechanism for reading out the quantum state of the mesoscopic charge device.

Abstract: A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output.

Abstract: A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.

Abstract: A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Abstract: A clock signal filtering circuit includes a bistable flip-flop and a controller for controlling state changes of the flip-flop. A first activation circuit activates the controller by edges of non-filtered clock signal pulses when their duration exceeds a first threshold. The first threshold is equal to a half-period corresponding to an upper frequency limit of the clock signal. A second activation circuit activates the controller by edges of filtered clock signal pulses delayed by an amount equal to a half period corresponding to a lower frequency limit of the clock signal. The clock filtering circuit transmits a filtered clock signal at a frequency within a specification interval, and at a duty cycle equal to 0.5 for a variety of different circumstances.

Abstract: A minimum pulse width detection and regeneration circuit is achieved. The circuit includes, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract: A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare.

Abstract: A circuit is utilized to reject false edges from a digital input signal to be provided to a digital circuit from a transmission line. The circuit includes circuitry for sensing the rising and falling edges of the signal and programmably filtering those edges such that the proper signal is transmitted to the digital circuit. The circuit also can be utilized at a plurality of power supply voltage ranges to remove such false edges without appreciably affecting the performance thereof.

Abstract: A clock splitter circuit for providing a Single Event Upset (SEU) tolerant clock signals to latches in a space-based environment. The splitter circuit includes an event offset delay. The event offset delay receives an undelayed clock signal and generates an undelayed inverted clock, a delayed clock signal and an inverted delayed clock signal. The delayed clock signal and the inverted delayed clock signal are delayed by the known duration of Single Event Effects (SEE) on logic. The delayed and undelayed clock signals are passed to a pair of event blocking filters which block any disturbance in the undelayed and/or undelayed clock signals. The event blocking filters each generate a pair of in-phase inverted output signals. The event blocking filters are designed such that both pairs of outputs may not be low simultaneously.

Abstract: A method and apparatus for providing noise immunity for binary signals being transmitted on a chip. A single signal is split into two complementary signals and transmitted from the transmitting portion to the receiving portion. At the receiving portion is a new type of flip-flop, termed a UV flip-flop, similar to an SR flip-flop, but having two memory states for input states 0-0 and 1-1. The Q output of the UV flip-flop is coupled to the receiving point. Since 0-0 and 1-1 are both memory states, positive and negative noise glitches will have no effect on the output of the UV flip-flop.

Abstract: Integrated circuit memory devices include a data synchronization circuit that includes a modulator, a pulse width filter and a demodulator. The circuit is configured to generate a filter input signal as a first pulse train having pulses of nonequivalent widths, in response to a first clock signal and a data input signal that is out of phase relative to the first clock signal. The circuit is further configured to filter the filter input signal and generate a filter output signal as a second pulse train. The circuit generates a data output signal as a true or complementary time corrected version of the data input signal, in response to the filter output signal and a second clock signal. Accordingly, the data is synchronized with a clock signal without requiring the use of a transmission clock signal Tclk and a reception clock signal Rclk, or a data strobe signal.

Abstract: A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

Abstract: Spurious pulses are eliminated in the output of a comparator performing analog to digital conversion by addition of logic which eliminates pulses having a width less than a selected width from the output of the comparator.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: An apparatus for correcting imperfectly equalized bipolar signals includes a delay line having a reset control, an AND gate, and a one-shot multivibrator. The apparatus is used in conjunction with an adaptive equalizer with the output of the adaptive equalizer being coupled to the input of the apparatus of the invention. More particularly, the output of the equalizer is coupled to the input and reset of the delay as well as to one input of the AND gate. The output of the delay line is coupled to the other input of the AND gate. The output of the AND gate is coupled to the input of the one-shot multivibrator and the output of the one-shot multivibrator is the corrected signal. The delay line is approximately equal to the pulse width of an erroneous pulse which is expected from over-equalization. When the delayed signal is compared to the original signal via the AND gate, narrow pulses are removed from the signal.

Abstract: A shift register comprising a digital filter samples an input signal inputted from an external terminal based on a clock signal and inputs output signals a to d of the shift register constituting the results of the sampling to a gate circuit also comprising the digital filter. The voltage level of the output signal of the gate circuit makes a transition from an L level to an H level when at least three voltage levels of the output signals a to d are H levels. A sense circuit then detects changes in the voltage level of the gate circuit and outputs a signal instructing for the data outputted from the counter to be stored in the register.

Abstract: A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50% duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: Circuitry is provided for detecting threshold crossings of an input signal which is generally sinusoidal or otherwise periodic, but which is subject to either high-frequency noise which would cause erroneous multiple threshold crossings, or low-frequency noise which would cause erroneous failure to detect a threshold crossing. Two detection elements detect the crossing of two different threshold values and produce detection signals reflecting whether the input signal is above or below their thresholds. For noisy input signals, these detection signals may be bouncy. High- and low-true versions of the detection signals are logically combined to produce a first signal which is active only while the input signal moves in one direction, and is masked from the active state while the input signal moves in the other direction. Likewise, a second signal is produced which is active the opposite way. The first and second signals set and reset a latch, whose output state represents the threshold crossing.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: A device is provided for neutralizing an electronic circuit whose rate is set by a clock signal in the event of an anomaly in the clock signal. The device includes an inhibition circuit for selectively inhibiting operation of the electronic circuit, and an anomaly detector for activating the inhibition circuit to inhibit operation of the electronic circuit as soon as an anomaly is detected in the clock signal. In one preferred embodiment, the anomaly detector includes two monostable circuits and a logic circuit. The first monostable circuit receives the clock signal and outputs a first pulse at each trailing edge of the clock signal, and the second monostable circuit receives the clock signal and outputs a second pulse at each leading edge of the clock signal. The logic circuit receives the first and second pulses and outputs an activation signal to the inhibition circuit whenever the clock signal shows an anomaly.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A method for processing a signal transitioning from a high state to a low state is described, comprising the steps of detecting a transition of the signal from a high state to a low state, setting a timer for a predetermined interval, sampling, while the timer is running, the signal to determine whether the signal remains in a low state, determining, by reading the timer, whether the predetermined interval has elapsed, repeating the sampling and determining steps until the predetermined interval has elapsed; and concluding, if the signal remains in a low state for each instance of said sampling step, that the transition is valid.

Abstract: An apparatus for and method of removing duty cycle distortion jitter from data by adaptive equalization are disclosed. The apparatus includes an equalization circuit which equalizes input data based on an equalization control signal, a signal analysis circuit, and a control circuit which generates the equalization control signal. A multiport apparatus includes a plurality of equalization circuits, a multiplexor, a signal analysis circuit, and a control circuit. A method includes the steps of receiving an equalization control signal and the input data signal, equalizing the input data signal based on the equalization control signal, analyzing the equalized data signal and generating an analysis result signal, and generating the equalization control signal based on the analysis result signal.

Abstract: A device for removing a noise, in which a delay circuit is used for positively removing a noise contained in a signal regardless of the signal transitioning either from high to low or vice versa. The device includes a noise detecting part for comparing an input signal to a reference signal, to provide the reference signal if a pulse width of the input signal is smaller than a pulse width of the reference signal, and to provide the input signal if the pulse width of the input signal is greater than the pulse width of the reference signal. A noise removing part is also included for accounting and removing an output from the noise detecting part as a noise if the output from the noise detecting part is smaller than the pulse width of the reference signal and for determining and providing the output from the noise detecting part as a valid signal if the output from the noise detecting part is greater than the pulse width of the reference signal.

Abstract: A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.

Abstract: The present invention provides a timing circuit for outputting a signal having an amplified pulse width when a signal having a normal pulse width is inputted thereto, characterized in that when glitch noise whose pulse width is small, is inputted to the timing circuit, a signal having a waveform corresponding to the pulse width thereof is outputted from the timing circuit. The timing circuit comprises a first delay circuit whose input is connected to an input terminal, a first NAND circuit having a first input terminal connected to the first delay circuit and a second input terminal connected to the input terminal, a second delay circuit whose input is connected to the output of the NAND circuit, an inverter whose input is connected to the input terminal, and a second NAND circuit having a first input terminal connected to the output of the second delay circuit and a second input terminal connected to the output of the inverter.

Abstract: An input signal reading circuit includes an up-down counter receiving an input signal and a sampling clock to count up the samplig clock when the input signal is at a high level and to count down the sampling clock when the input signal is at a low level. The up-down counter outputs an underflow signal when a count value of the up-down counter becomes zero. A comparator compares the count value of the up-down counter with a reference value held in a register, to generate a coincidence signal when the count value of the up-down counter becomes coincident with the reference value. A RS flipflop is set by the coincidence signal to bring the read-out signal into a high level, and is reset by the underflow signal to bring the read-out signal into a low level.

Abstract: An apparatus for detecting and removing an additive disturbance from a signal in a data transmission channel, and an method therefor. The apparatus includes: a disturbance detector which detects whether a disturbance exists in an input signal; a canceling signal generating portion which, when a disturbance is detected by the disturbance detector, generates a canceling signal beginning at the same time as the disturbance, based on a predetermined period of the input signal; and a disturbance remover which subtracts the canceling signal from the input signal to remove the disturbance. Therefore, the canceling signal is generated based on both the output and input signals, thereby precisely removing the disturbance.

Abstract: In a pulse filtering device, the pulse signal is sampled to enable the counting of this signal by an asynchronous counter. A pulse of calibrated duration is generated when the counting reaches a predetermined number.

Abstract: The DC sensor signal S, on which a low frequency waviness component S1 and a high frequency noise component S2, is obtained by amplitude detecting for a sinusoidal output signal from a touch signal probe. For generating a touch trigger signal TG at an sbrupt DC level transition of the DC sensor signal S, the signal S is input to a LPF 21 to output a signal (S0+S1), where S0 is a DC offset component, and S1 is a low frequency waviness component. The amplitude transforming circuit 22 multiplies the signal (S0+S1) by a coefficient k to generate a reference signal k(S0+S1). The comparator 23 compares the DC sensor signal S with the reference signal to output the touch trigger signal TG at the abrupt DC transition point of the DC sensor signal S.

Abstract: Method and device for generating bit information in a subscriber station of a bus system, in particular of the bus of the EIBA, essentially symmetrical AC voltage information being superposed as bit information on a DC voltage of the bus in that a DC voltage potential (19) of a line under inductive loading (9) is pulled, in each case in an active pulse (20) to the potential of another line and an equalizing pulse (22, 23) is formed with subsequent energy recovery. It is provided that the active pulse (20) of the bit information at a bit frequency is formed from individual pulses (17) of higher frequency.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: A low pass filter comprises a complementary signal generator circuit for receiving an input pulse signal to output a first and a second signals having phases inverse to each other, a first CR circuit inputted with the first signal, a second CR circuit inputted with the second signal, a flip-flop circuit, a set circuit, and a reset circuit. In the low pass filter, the set circuit detects an output signal of the first CR circuit by the threshold voltage value thereof to set the flip-flop circuit in accordance with a detection result, and the reset circuit detects an output signal of the second CR circuit by the same threshold voltage value to reset the flip-flop circuit in accordance with a detection result.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: A clock enabling circuit that generates an output clock signal such that when the enable output signal changes to a logical false, the output clock signal returns to its steady-state value in a manner that does not produce any glitches, and preserves the duty cycle of the input clock. The circuit comprises a first D flip-flop that is positive-edge triggered, a second D flip-flop that is negative-edge triggered, and a two-input AND gate. The first flip-flop has the D input connected to a constant positive voltage, the positive-edge triggered clock input connected to the input clock signal, the Q output connected to the AND gate, and the Q-complement output connected to the asynchronous reset of the second flip-flop. The second flip-flop has the D input connected to the enable output signal, the negative-edge triggered clock input connected to the input clock signal, the Q output connected to the asynchronous reset of the first flip-flop, and the Q-complement output connected to the AND gate.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).