Abstract: A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry comprises a mixer comprising a first input, a second input and an output. The combined mixer and filter circuitry further comprises a filter comprising an active inductor and a first capacitor. The active inductor comprises a transistor having a first terminal, a second terminal and a third terminal and a resistor connected between the first terminal of the transistor and a voltage potential. The first capacitor is connected between the third terminal and a signal ground and the second terminal of the transistor is connected to the second input of the mixer.

Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Abstract: A circuit includes a main amplifier having a first input and a first output. A main bias circuit is coupled to the main amplifier, and the main bias circuit configured to operate the main amplifier in a first frequency band. A feedforward cancellation amplifier has a second input and a second output, in which the second input is coupled to the first input, and the second output is coupled to the first output. A filter is coupled between the first input and the second input. A feedforward bias circuit is coupled to the feedforward cancellation amplifier. The feedforward bias circuit is configured to operate the feedforward cancellation amplifier in a second frequency band within and narrower than the first frequency band.

Abstract: A dynamic amplifier includes an amplifier configured to differentially amplify first and second input signals to generate first and second output signals, a bias circuit, and a variable impedance circuit. The bias circuit is connected between a first power node configured to supply a first source voltage and the amplifier, and configured to apply bias to the amplifier. The variable impedance circuit is connected between the amplifier and a second power node configured to supply a second source voltage that is lower than the first source voltage. The variable impedance circuit is configured to adjust amplification gain of the amplifier, by adjusting impedance based on a magnitude of one among the first and second input signals and the first and second output signals.

Abstract: An analog to digital converter is provided and includes column processing units that convert analog signal to digital signal. One or more counters count time of analog to digital conversion and one or more comparators compares the voltage of reference signal and analog signal from neuromorphic device. One or more generators generates the reference signal for the comparator.

Abstract: An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT?, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM?. The load elements are not coupled directly to the output terminals OUT+ and OUT?, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM?, enabling a modular approach where multiple instances of the multiplexer may be combined on an “as-needed” basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

Abstract: A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Abstract: Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

Abstract: A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.

Abstract: An amplification circuit configured to generate an output signal by differentially amplifying first and second input signals. The first and second input signals are a differential signal pair. Alternatively, the first input signal is a single-ended signal, and the second input signal is a reference signal. The amplification circuit is configured to perform a differential amplification operation by increasing a gain for generating an output signal based on the first input signal.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a gate bias network connected to the main path and to the auxiliary path, the main path and the auxiliary path each having different structures that are configured to improve linearity of the switching function.

Abstract: An apparatus for regulating a bias-voltage of a switching power supply is disclosed. The apparatus includes a cascode amplifier, feedback-circuit, and bias-regulator circuit. The cascode amplifier includes a common-gate transistor and common-source transistor, where a source of the common-gate transistor is in signal communication with a drain of the common-source transistor. The feedback-circuit is in signal communication with the source of the common-gate transistor and the drain of the common-source transistor and the bias-regulator circuit is in signal communication with a gate of the common-source transistor, a gate of the common-gate transistor, and the feedback-circuit. The feedback-circuit receives a drain-voltage from the drain of the common-source transistor and produces a feedback-voltage and the bias-regulator circuit is configured to receive the feedback-voltage and produce and regulate the bias-voltage.

Abstract: A magnetic field sensor includes a semiconductor substrate, a circular vertical Hall (CVH) sensing element comprising a plurality of Hall elements arranged over an implant region in a semiconductor substrate, adjacent ones of the plurality of vertical Hall element at predetermined angles from each other. A CVH output stage may comprise one or more of drive circuits to drive the plurality of vertical Hall elements and produce an analog signal, and a filter coupled to the CVH output stage to receive the analog signal. The filter may be configured to remove a DC component from the analog signal to produce a filtered signal. An analog-to-digital converter may be coupled to receive the filtered signal and produce a digital signal. A processor stage may be coupled to receive the filtered signal and operable to compute an estimated angle of the external magnetic field.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path, both the main path and the auxiliary path having a plurality of field-effect transistors. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to a first subset of the plurality of FETs of the auxiliary path. The circuit assembly also includes a third gate bias network connected to a second subset of the plurality of FETs of the auxiliary path so that the third gate bias network switches on the auxiliary path when the main path is on for nonlinear cancellation, and switches off the auxiliary path when the main path is off to enable the branch to withstand maximum voltage swings.

Abstract: Hybrid variable gain amplifiers and methods of controlling hybrid VGAs are disclosed. The hybrid VGA includes a first portion that provides a current path between a positive input and a positive output, and a current path either between the positive input and a negative output, in a first mode of operation, or between the positive input and a voltage source, in a second mode of operation. A second portion of the VGA provides a current path between a negative input and the negative output, and a current path either between the negative input and the positive output, in the first mode of operation, or between the negative input and the voltage source, in the second mode of operation. Control voltages selectively enable the paths in the first or second mode of operation. The control voltages further control amount of current flow in the enabled paths.

Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.

Abstract: The disclosure relates to technology for a fully differential adjustable gain device that includes differential input terminals, differential output terminals, fully differential signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a negative input of the fully differential signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a positive input of the fully differential signal processing circuitry.

Abstract: The present invention disclosure provides a multiplier and a power factor correction circuit which the multiplier is applied. The multiplier comprises a Gilbert multiplier circuit comprising a first differential input stage, a second differential input stage and an output stage; a first differential voltage conversion circuit; a second differential voltage conversion circuit; and a bias current generating circuit; Wherein said output stage comprises: a current mirror unit comprising two current input terminals and a current output terminal; and a feedback control unit configured to ensure that the current output terminal does not output current when the voltage difference received by the multiplier is zero. The present invention is advantageous in improving the linearity of the multiplier and the accuracy of the output current of the multiplier output current.

Abstract: The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Abstract: A system for enhanced linearity mixing includes an input-source signal coupler; a local oscillator (LO) signal coupler; a primary mixer that combines, via heterodyning, the primary-mixer-input signal and the primary-mixer-LO signal to generate a primary-mixer-output signal; a distortion-source mixer that combines, via heterodyning, the distortion-mixer-input signal and the distortion-mixer-LO signal to generate a distortion-mixer-output signal; and an output signal coupler that combines the primary-mixer-output signal and the distortion-mixer-output signal to generate an output signal with reduced non-linearity.

Abstract: Devices and methods are disclosed for generating, filtering, and amplifying signals that are sent and received using SOCs. These improved methods and devices advantageously provide filtering of composite RF signals such that the RF signals can be transmitted with an improved SNR. Such filtered signals can then be transmitted at a higher power. Because filtering is performed at an intermediate frequency, the higher cost of low-noise RF-transmitters and/or RF filtering components can be avoided. Accordingly, less expensive (e.g., noisier) components, such as readily available wireless transceiver SOCs, can be used for generating RF signals, filtering the signals, and then transmitting the filtered signals at higher power. As a result of these devices and methods, inexpensive SOCs may be used at higher powers and over longer ranges than would be normally expected.

Abstract: A circuit for controlling a collector current of a substrate bipolar junction transistor (BJT) is provided. The circuit includes a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT, a current transmitter configured to transmit the first mirroring base current, a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT, and a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

Abstract: An impedance detector includes a sensing circuit with an adjustable impedance. The sensing circuit is coupled to a signal path. Further, an evaluation circuit is coupled to the sensing circuit.

Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

Abstract: An amplifier arrangement is presented, comprising a first differential stage (DS1) comprising at least two transistors (M1, M1?) having a first threshold voltage (Vth1), at least a second differential stage (DS2) comprising at least two transistors (M3, M3?) having a second threshold voltage different from the first threshold voltage, at least one of the transistors of the first and second differential stage (DS1, DS2), respectively, has a control input commonly coupled to an input of the amplifier arrangement, at least one transistor (M1) of the first differential stage and one transistor (M3) of the second differential stage are arranged in a common current path, which is coupled to an output of the amplifier arrangement.

Abstract: An analog predistortion linearizer system with dynamic frequency compensation for automatically adjusting predistortion characteristics based on a detected frequency includes a frequency detector configured to generate at least one frequency detection signal in response to receiving an amplifier drive signal, the frequency detection signal including a frequency indicator that indicates the frequency of the amplifier drive signal. Moreover, the system also includes a controller communicatively coupled to the frequency detector and configured to generate a predistorter control signal in response to receiving the frequency detection signal from the frequency detector, and a predistorter communicatively coupled to i) the frequency detector and ii) the controller, the predistorter configured to generate a predistorted amplifier drive signal based on at least the predistorter control signal.

Abstract: A radio frequency receiver is provided. The receiver can be employed in a low power (or ultra-low power) receiver architecture to generate a baseband signal or an intermediate frequency signal. In addition, the receiver includes capabilities of gain control to provide different gain settings as well as providing better/improved impedance matching control.

Abstract: In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes an input stage coupled to the mixer cell, the input stage configured to receive an input signal and to produce a local minimum in a third order harmonic of the output with respect to an input power. The up-conversion mixer further includes a power supply input configured to receive a power supply voltage and a ground, and a maximum number of transistor stages between the power supply input and the ground is two.

Abstract: An apparatus includes: a first transconductance device of a first type configured to convert a first voltage into a first current of an output node; a second transconductance device of a second type configured to convert a second voltage into a second current of the output node; a common mode feedback circuit coupled to the output node configured to control a mean voltage at the output node in accordance with a reference voltage; and a reset circuit configured to reset a voltage at the output node in accordance with a clock signal.

Abstract: A voltage-controlled oscillator includes a voltage-current converter, a first ring oscillator and a second ring oscillator. The voltage-current converter includes a first transistor for receiving a first control voltage at its gate terminal, a second transistor for receiving a second control voltage at its gate terminal, a third transistor connected to the first transistor in series and has a gate terminal connected to a drain terminal of the first transistor, a fourth transistor connected to the second transistor in series and has a gate terminal connected to a drain terminal of the second transistor, a resistor connected to a source terminal of the first transistor and a source terminal of the second transistor, a fifth transistor having a gate terminal connected to the drain terminal of the first transistor, and a sixth transistor having a gate terminal connected to the drain terminal of the second transistor.

Abstract: A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.

Abstract: In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.

Abstract: An RF amplifier, including: an input RF chain configured to receive and process an input RF signal including a plurality of frequency bands within a first band group and output a first signal; and a plurality of output RF chains coupled to the input RF chain, each output RF chain of the plurality of output RF chains configured to process the first signal within at least one band of the plurality of frequency bands of the first band group, wherein each output RF chain includes a bias circuit configured to receive an enable signal to enable the processing of the first signal within the at least one band and output an output RF signal within the at least one band.

Abstract: A DC-coupled differential amplifier has an output common-mode voltage near the ground reference. A feedback circuit superimposed on a trans-linear loop improves linearity and extends the bandwidth of the basic PNP differential pair.

Abstract: A phase-locked loop circuit includes a regulator circuit, first and second inductor-capacitor tank circuits, and first and second load capacitors. The regulator circuit generates a supply voltage. The first load capacitor is coupled to the regulator circuit and to the first inductor-capacitor tank circuit. The first load capacitor provides current for the supply voltage to the first inductor-capacitor tank circuit. The second load capacitor is coupled to the regulator circuit and to the second inductor-capacitor tank circuit. The second load capacitor provides current for the supply voltage to the second inductor-capacitor tank circuit.

Abstract: A balun converts a single-ended radio-frequency signal into differential signals. A differential matching circuit outputs a maximum-level positive-phase output signal at a lower or higher frequency than the center frequency and outputs a maximum-level reverse-phase output signal at a higher or lower frequency than the center frequency. An amplification circuit amplifies a positive-phase output signal and a reverse-phase output signal of the differential matching circuit. A mixing circuit converts the positive-phase output signal and the reverse-phase output signal that are output from the amplification circuit into intermediate-frequency signals using locally generated signals.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: A unidirectional sampling mixer utilizes a stepped phase modulation to shift the frequency of an input signal. An RF input signal is supplied to an RF input switch from an RF input port. An ordered set of phase shift values to be applied to the RF input signal and a set of times each element of which correspond to a time at which a phase shift value is be applied to the RF signal are determined. For each phase shift value within the ordered set of phase shift values, a controller controls the RF input switch to select an input of a phase shifting device and controls an RF output switch to select an output of the phasing shifting device. The input of the phase shifting device and the output of the phase shifting device are selected to apply the phase shift value at its corresponding time to the RF input signal. A frequency shifted signal is supplied to an RF output port from an output of the RF output switch.

Abstract: Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

Abstract: A multi-mode circuit can switch an output section between mixer and amplifier modes, with or without variable gain, to create a variable gain amplifier or a variable gain mixer or route an input signal by adjusting a bias current. An input section is controlled by a bias section and connected to the output section. The output section includes a first base-coupled transistor pair adapted to receive an input signal at emitters of the first base-coupled transistor pair, receive a bias signal at bases of the first base-coupled transistor pair, and provide an output signal at collectors of the first base-coupled transistor pair.

Abstract: An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.

Abstract: A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.

Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection circuit includes a multiplier circuit configured to multiply a first voltage signal by a second voltage signal. The multiplier circuit receives the first voltage signal at gates of a first transistor pair and receives the second voltage signal at gates of second and third transistor pairs. In some embodiments, a drain of a first transistor in the first transistor pair is coupled to sources of the second transistor pair, and drain of a second transistor in the first transistor pair is coupled to sources of the third transistor pair. In some embodiments, the power detection circuit includes a comparison circuit that compares the first pair of currents and a second pair of currents associated with a threshold voltage signal.

Abstract: A single-balanced balun mixer circuit includes a balun with a center tap connected to a differential pair with a tail resistor. The balun receives a first input signal and a second signal at the single-ended input terminal and the center tap, respectively. Such a balun mixer may be used as an up-converter mixer by supplying a baseband or intermediate signal at the center tap and a local oscillator (LO) signal at the single-ended input terminal.

Abstract: A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region.

Abstract: A frequency mixer circuit includes a mixer, a load stage, and again stage. The load stage cooperates with the mixer to generate a differential output voltage signal with a mixed frequency according to a differential local oscillator voltage signal and a differential input voltage signal. The gain stage has a transconductance, and a magnitude of the differential current signal and the transconductance have a positive relationship therebetween, so as to result in a positive relationship between the transconductance and a conversion gain which is a ratio of magnitude of the differential output voltage signal to magnitude of the differential input voltage signal.

Abstract: A method includes, in at least one aspect, selecting a first phase signal, where the first phase signal concurrently enables a first pair of switching elements; selecting a second phase signal, where the second phase signal concurrently enables a second pair of switching elements; and generating an interpolated phase signal by providing a connection between a switching element of the first pair of switching elements to an output node and providing a connection between a switching element of the second pair of switching elements to the output node.

Abstract: A high frequency mixer with a tunable dynamic range is disclosed. One embodiment provides a mixer apparatus including multiple first transistors at an input branch that receive a differential radio frequency (RF) signal, and multiple second transistors at a second branch that receive a differential local oscillator (LO) signal. The second transistors generate an intermediate frequency (IF) differential output signal. The bias current that flows at the input branch and the output branch can be independently adjusted to allow the conversion gain, linearity, or the output noise of the mixer to be controlled.