Abstract: Several methods and systems for facilitating multimedia data encoding are disclosed. In an embodiment, a plurality of picture buffers associated with multimedia data are received in an order of capture associated with the plurality of picture buffers. Buffer information is configured for each picture buffer from among the plurality of picture buffers comprising at least one of a metadata associated with the corresponding picture buffer and one or more encoding parameters for the corresponding picture buffer. A provision of picture buffers in an order of encoding is facilitated based on the configured buffer information.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(Vin) approximating a polynomial nominal trans-characteristic given by f ? ( V i ? n ) = ( 3 A ? V i ? n - 4 A 3 ? V i ? n 3 ) ? g m where A represents an amplitude of the input voltage and gm is a transconductance of transistors of the first and second transistor pairs.

Abstract: Systems, methods, and devices relate to tunable baluns for multimode power amplification. For example, a variable-gain amplification system can include a power amplifier configured to provide an amplified signal and to selectively operate in at least a first gain mode and a second gain mode. The variable-gain amplification system can also include a tunable balun circuit configured to receive the amplified signal from the power amplifier and to provide an output signal. The tunable balun circuit can be configured to implement a first turn ratio for the first gain mode and a second turn ratio for the second gain mode.

Abstract: Apparatuses and methods are disclosed regarding a multiband transmitter. In an example aspect, an apparatus for processing signals for wireless transmission includes a wireless interface device. The wireless interface device includes an upconverter, a tunable filter, and a driver amplifier. The upconverter has an output and is configured to upconvert a baseband frequency to a radio frequency based on a local oscillator signal. The tunable filter has an input and an output; the input of the tunable filter is coupled to the output of the upconverter. The driver amplifier has an input; the input of the driver amplifier is coupled to the output of the tunable filter.

Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.

Abstract: A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

Abstract: A method includes generating a first current through a first node based on a differential pair of signals received by a differential pair of input nodes of a differential circuit of a first integrated circuit die of an isolator product. The method includes generating a second current through a second node. The second current matches the first current through the first node and is based on an attenuated version of an output measurement signal. The method includes generating the output measurement signal having a level corresponding to an average amplitude of the differential pair of signals based on the first current and the second current.

Abstract: Embodiments of a gain control circuit and a wideband communication circuit that uses the gain control circuit are disclosed. In an embodiment, gain control circuit includes first and second output terminals to output gain control signals and first and second diode-connected transistors connected between a supply voltage and the first and second output terminals, which are connected to input terminals of a communication component circuit with a plurality of input transistors. The gain control circuit further includes a current digital-to-analog converter connected to the diode-connected transistors to generate first and second currents for the diode-connected transistors based on an N-bit input code, wherein a ratio of the first and second currents sets voltages of the gain control signals that are output from the gain control circuit to the communication component circuit to control signal gain provided by the communication component circuit.

Abstract: A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.

Abstract: Several methods and systems for facilitating multimedia data encoding are disclosed. In an embodiment, a plurality of picture buffers associated with multimedia data are received in an order of capture associated with the plurality of picture buffers. Buffer information is configured for each picture buffer from among the plurality of picture buffers comprising at least one of a metadata associated with the corresponding picture buffer and one or more encoding parameters for the corresponding picture buffer. A provision of picture buffers in an order of encoding is facilitated based on the configured buffer information.

Abstract: For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the dividend to generate bit-level partial remainders. Furthermore, the circuit architecture may enable a fast round-to-zero division of signed integers by flipping the input bits of a negative integer and output bits of the corresponding quotient and performing only one increment operation, either before the division or after the division. In addition, the circuit architecture may also perform a division of a dividend in a carry-save form.

Abstract: The invention relates to a mixer circuit, which includes a transconductance stage circuit, a switch stage circuit and a load stage circuit which are electrically connected in sequence. The transconductance stage circuit is used to access a radio frequency voltage signal and convert the radio frequency voltage signal into a radio frequency current signal The switch-level circuit is used to access the local oscillator signal and the radio frequency current signal, and the switch-level transistor is turned on by using the local oscillator signal; the load-level circuit is used to convert the intermediate frequency current signal into a voltage signal for output. In the present invention, the transconductance stage circuit adopts a transistor superposition technology structure, which improves the conversion gain of the mixer; at the same time, it uses a source degenerate inductance structure, which further improves the conversion gain and linearity of the circuit.

Abstract: Aspects of the present disclosure provide a low power differential frequency multiplier. An example frequency multiplier circuit generally includes a first set of transistors, a second set of transistors, and a resonant circuit. The first set of transistors comprises a first transistor and a second transistor, wherein each of the transistors in the first set is a first type of transistor. The second set of transistors comprises a third transistor and a fourth transistor, wherein each of the transistors in the second set is a second type of transistor. The resonant circuit has a first terminal coupled to the first set of transistors and a second terminal coupled to the second set of transistors, wherein the resonant circuit comprises an inductive element and a capacitive element coupled in parallel with the inductive element.

Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.

Abstract: Apparatus and methods for power amplifiers isolated by differential ground are provided. In certain implementations, a mobile device includes a transceiver that generates a plurality of radio frequency input signals including a first radio frequency input signal and a second radio frequency input signal, and a plurality of differential power amplifiers including a first differential power amplifier that provides amplification to the first radio frequency input signal and a second differential power amplifier that provides amplification to the second radio frequency input signal. The first differential power amplifier and the second differential power amplifier each operate with differential ground so as to provide isolation between the first differential power amplifier and the second differential power amplifier.

Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

Abstract: Apparatus and methods for power amplifier systems with differential ground are provided. In certain implementations, a semiconductor die for a radio frequency communication system includes a differential ground network configured to distribute a ground voltage. The differential ground network is substantially symmetric with respect to a line of symmetry. The semiconductor die further includes a first differential power amplifier including a first half circuit and a second half circuit that operate differentially to provide amplification. The first half circuit and the second half circuit are symmetrically connected to the differential ground network. The semiconductor die can further include a second differential power amplifier, and the differential ground network serves to provide isolation between the first differential power amplifier and the second differential power amplifier.

Abstract: A SIM card carrier includes a connector, an ejecting mechanism, and a tray. The connector includes a cavity having an open end, a closed end, a top side, and a bottom side. The ejecting mechanism includes a first resilient member and a movable arm. The first resilient member is disposed on the closed end of the cavity, the movable arm is disposed on the bottom side of the cavity. The tray includes a holder having a notch at a side and the movable arm engages the notch. The tray is held in the cavity when the notch is engaged, and the tray is ejected from the connector by the first resilient member when the movable arm disengages from the notch.

Abstract: In a multi-electrode ablation system, method, and controller, a power supply is configured to be coupled to a plurality of electrodes, and a controller is coupled to the power supply. The controller is configured to couple an output voltage of the power supply to the plurality of electrodes, and for each electrode of the plurality of electrodes, measure a temperature associated with the electrode, and determine a thermal gain of each electrode of the plurality of electrodes.

Abstract: A mobile device can include a support frame adapted to support one or more electronic components of the mobile device. The mobile device includes a chassis shell adapted to form an exterior of the mobile device. The mobile device can include a tray exposed on the exterior and having at least two functional components of the mobile device attached thereon serving at least two different functions (e.g., an electronic function, an input or output function, and/or a mechanical function to support a permanent or temporary component). The chassis shell exposes one of the functional components on the exterior. The tray is capable of sliding outward to further expose the other one of the functional components.

Abstract: An ultra-wideband radio frequency transmission system capable of receiving a first signal with discrete levels, and including: a voltage-controlled oscillator capable of supplying a first oscillating signal including an oscillating circuit powered by a power supply circuit comprising at least one first current source controlled by the first signal with discrete levels or a second signal with discrete levels obtained from the first signal with discrete levels; a mixer capable of receiving the first oscillating signal and of supplying a second oscillating signal equal to the first oscillating signal multiplied by a gain which depends on the first signal with discrete levels or on a third signal with discrete levels obtained from the first signal with discrete levels; and an antenna or an electromagnetic coupling device capable of transmitting a radio frequency signal based on the second oscillating signal.

Abstract: A magnetoresistive mixer, comprising a spiral coil, a bridge-type magnetoresistive sensor and a magnetic shielding layer, wherein the spiral coil is located between the bridge-type magnetoresistive sensor and the magnetic shielding layer. Four tunnel magnetoresistive sensor units forming the bridge-type magnetoresistive sensor respectively contain N array-type magnetic tunnel junction rows. The magnetic tunnel junction rows are connected in series, parallel, or combination of series and parallel connections to form two port structures.

Abstract: The compact C-multiplier includes four MOSFETs operating in the subthreshold region using the translinear principle. The multiplier is controllable to meet designer requirements. A Tanner Tspice simulator is used to confirm the functionality of the design in 0.13 pm CMOS Technology. The circuit operates from a ±0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs.

Abstract: This document discusses, among other things, a resistance multiplier configured to provide a more specific and controllable resistance value, the resistance multiplier including an amplifier configured to control a resistance across a first transistor using a received reference resistance value and to control a resistance across a second transistor using the resistance across the first transistor and a relationship between the first and second transistors.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Abstract: A frequency converter, capable of obtaining resonance characteristics having a high Q factor and a high multiplication signal and having a narrow-band frequency selectivity function, is provided by the following configuration. A magnetoresistance effect element includes a pinned magnetization layer, a free magnetization layer, and a non-magnetic spacer layer disposed between the pinned magnetization layer and the free magnetization layer. In response to an input of a high frequency signal and a local signal, the magnetoresistance effect element generates a voltage signal (multiplication signal) by multiplying the signals by each other using a magnetoresistance effect. A magnetic field generated by a magnetic-field applying unit is applied to the free magnetization layer of the magnetoresistance effect element in a direction perpendicular to a film surface direction or by tilting an angle of the magnetic field from the film surface direction toward a direction perpendicular to the film surface direction.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: An electronic device comprises an input transmission line that receives an input signal, an output transmission line that transmits an output signal, a local oscillator transmission line that transmits a local oscillator signal, multiple amplification and mixing stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal and mixing the amplified portion of the input signal with the local oscillator signal to produce a portion of the output signal, and multiple amplification stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal to produce a portion of the output signal. The amplification stages are located proximate an output side of the electronic device, and the amplification and mixing stages are located proximate an input side of the electronic device.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: A harmonic mixer includes first through third field effect transistors. A gate electrode of the first field effect transistor is supplied with a positive-phase signal of a first signal. A gate electrode of the second field effect transistor is supplied with a negative-phase signal of the first signal. A source electrode of the second field effect transistor is short-circuited with a source electrode of the first field effect transistor and is grounded. A source electrode of the third field effect transistor is connected to a terminal at which drain electrodes of the first field effect transistor and the second field effect transistor are short-circuited. A gate electrode of the third field effect transistor is supplied with a second signal. A drain electrode of the third field effect transistor outputs a signal.

Abstract: An improved microwave mixer manufactured using multilayer processing includes an integrated circuit that is electrically connected to a top metal layer of a substrate. The microwave mixer includes: a first metal layer; a dielectric substrate on the first metal layer; a second metal layer directly on the substrate, at least two passive circuits arranged on the second metal layer and a top layer metal; a thin dielectric layer on the second metal layer, wherein the top layer metal is directly on the thin dielectric layer; an integrated circuit (IC) attached to the second metal layer, wherein the IC includes at least one combination of non-linear devices, and wherein the IC is directly connected to the passive circuits on the second metal layer; and a protection layer on the IC.

Abstract: An apparatus of a Harmonic Rejection Mixer (HRM) for removing a harmonic component and an operating method thereof are provided. The HRM includes a Local Oscillator (LO), at least one frequency converter, at least two mixers, at least one phase converter, and a combiner. The LO generates an LO signal. The at least one frequency converter multiplies the LO signal using different variables to provide the same to at least two mixers. The at least two mixers convert a frequency band of an input signal using the LO signal provided from the LO and the at least one frequency converter. The at least one phase converter controls a phase of an output signal of at least one other mixer excluding one of the at least two mixers. The combiner combines an output signal of the one mixer with an output signal of the at least one phase converter.

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract: Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems. In one aspect, a nanoelectromechanical system (NEMS) based computing element includes: a substrate; two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element.

Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.

Abstract: In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.

Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

Abstract: The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.

Abstract: An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal.

Abstract: Examples of a digital transceiver, a switched-capacitor sampling mixer, and an N-stage switched-capacitor amplifier are generally described herein. The digital transceiver may include a plurality of switched-capacitor sampling mixers and a plurality of N-stage switched-capacitor amplifiers. Each mixer samples a received differential RF signal. The pair of N-stage switched-capacitor amplifiers operates as charge redistribution amplifiers. Each N-stage switched-capacitor amplifier provides a near-constant capacitive load for one of the mixers.

Abstract: A frequency mixer is disclosed. In an implementation, the multi-LO band switched-core includes a single field-effect transistor (FET) ring having a first mixer core and a second mixer core. The first mixer core and the second mixer core configured to connect to a radio frequency (RF) port and an intermediate frequency (IF) port. The frequency mixer also includes a first local oscillator (LO) transformer and a second LO transformer. The first LO transformer is configured to furnish a first LO signal occurring in a first limited range of frequencies to the first mixer core, and the second LO transformer is configured to furnish a second LO signal occurring in a second limited range of frequencies to the second mixer core.

Abstract: A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique.

Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.

Abstract: An embodiment of a variable-gain mixer for down-converting a modulated input signal into a modulated output signal in a wireless receiver is proposed. The mixer includes means for selecting a mixer gain according to a power level of the input signal, amplifying means for amplifying the input signal into a modulated intermediate current (IRF+,IRF?) in response to a control signal indicative of the selected mixer gain, the intermediate current having an intermediate component, consisting of a direct current, varying according to the selected mixer gain, means for generating the output signal from the intermediate current, the output signal having an output component, consisting of a direct current or voltage, depending on the intermediate component; in an embodiment, the mixer further includes means for setting a compensation current in response to the control signal for compensating the variation of the intermediate component, and means for adding the compensation current to the intermediate current.

Abstract: A sub-harmonic electronic mixer has at least one field effect transistor (FET) having a gate, source, and drain; and a useful signal input at a useful frequency; and a local oscillator input. The input receives the oscillator signal at a frequency being an integral fraction of the useful frequency, plus or minus a mixing frequency to provide a signal output. A gate of the FET and/or the drain and/or the source receives the useful signal to generate a gate-source voltage and/or a drain-source voltage whereby the gate receives the local oscillator signal to generate a gate-source voltage, and the drain or a source receives the local oscillator signal to generate a drain-source voltage. A phase shift is introduced between the signal received at the gate and the signal received at the drain or source of the FET.