Product Patents (Class 327/356)
  • Patent number: 10715195
    Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
  • Patent number: 10658977
    Abstract: Apparatus and methods for power amplifiers isolated by differential ground are provided. In certain implementations, a mobile device includes a transceiver that generates a plurality of radio frequency input signals including a first radio frequency input signal and a second radio frequency input signal, and a plurality of differential power amplifiers including a first differential power amplifier that provides amplification to the first radio frequency input signal and a second differential power amplifier that provides amplification to the second radio frequency input signal. The first differential power amplifier and the second differential power amplifier each operate with differential ground so as to provide isolation between the first differential power amplifier and the second differential power amplifier.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 19, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Foad Arfaei Malekzadeh, Stephen Joseph Kovacic
  • Patent number: 10389375
    Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 20, 2019
    Assignee: Mythic, Inc.
    Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
  • Patent number: 10218310
    Abstract: Apparatus and methods for power amplifier systems with differential ground are provided. In certain implementations, a semiconductor die for a radio frequency communication system includes a differential ground network configured to distribute a ground voltage. The differential ground network is substantially symmetric with respect to a line of symmetry. The semiconductor die further includes a first differential power amplifier including a first half circuit and a second half circuit that operate differentially to provide amplification. The first half circuit and the second half circuit are symmetrically connected to the differential ground network. The semiconductor die can further include a second differential power amplifier, and the differential ground network serves to provide isolation between the first differential power amplifier and the second differential power amplifier.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 26, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Foad Arfaei Malekzadeh, Stephen Joseph Kovacic
  • Patent number: 10148302
    Abstract: A SIM card carrier includes a connector, an ejecting mechanism, and a tray. The connector includes a cavity having an open end, a closed end, a top side, and a bottom side. The ejecting mechanism includes a first resilient member and a movable arm. The first resilient member is disposed on the closed end of the cavity, the movable arm is disposed on the bottom side of the cavity. The tray includes a holder having a notch at a side and the movable arm engages the notch. The tray is held in the cavity when the notch is engaged, and the tray is ejected from the connector by the first resilient member when the movable arm disengages from the notch.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 4, 2018
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Wen-Bing Wu
  • Patent number: 10080601
    Abstract: In a multi-electrode ablation system, method, and controller, a power supply is configured to be coupled to a plurality of electrodes, and a controller is coupled to the power supply. The controller is configured to couple an output voltage of the power supply to the plurality of electrodes, and for each electrode of the plurality of electrodes, measure a temperature associated with the electrode, and determine a thermal gain of each electrode of the plurality of electrodes.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: September 25, 2018
    Assignee: ST JUDE MEDICAL, CARDIOLOGY DIVISION, INC.
    Inventors: Joseph Allen Brotz, John Eric Hein, Raymond Vincent Froehlich, Joseph William Barnier
  • Patent number: 9838521
    Abstract: A mobile device can include a support frame adapted to support one or more electronic components of the mobile device. The mobile device includes a chassis shell adapted to form an exterior of the mobile device. The mobile device can include a tray exposed on the exterior and having at least two functional components of the mobile device attached thereon serving at least two different functions (e.g., an electronic function, an input or output function, and/or a mechanical function to support a permanent or temporary component). The chassis shell exposes one of the functional components on the exterior. The tray is capable of sliding outward to further expose the other one of the functional components.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 5, 2017
    Assignee: ESSENTIAL PRODUCTS, INC.
    Inventors: David John Evans, V, Xinrui Jiang, Andrew E. Rubin, Matthew Hershenson, Xiaoyu Miao
  • Patent number: 9800441
    Abstract: An ultra-wideband radio frequency transmission system capable of receiving a first signal with discrete levels, and including: a voltage-controlled oscillator capable of supplying a first oscillating signal including an oscillating circuit powered by a power supply circuit comprising at least one first current source controlled by the first signal with discrete levels or a second signal with discrete levels obtained from the first signal with discrete levels; a mixer capable of receiving the first oscillating signal and of supplying a second oscillating signal equal to the first oscillating signal multiplied by a gain which depends on the first signal with discrete levels or on a third signal with discrete levels obtained from the first signal with discrete levels; and an antenna or an electromagnetic coupling device capable of transmitting a radio frequency signal based on the second oscillating signal.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 24, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alexandre Siligaris, Cédric Dehos
  • Patent number: 9768726
    Abstract: A magnetoresistive mixer, comprising a spiral coil, a bridge-type magnetoresistive sensor and a magnetic shielding layer, wherein the spiral coil is located between the bridge-type magnetoresistive sensor and the magnetic shielding layer. Four tunnel magnetoresistive sensor units forming the bridge-type magnetoresistive sensor respectively contain N array-type magnetic tunnel junction rows. The magnetic tunnel junction rows are connected in series, parallel, or combination of series and parallel connections to form two port structures.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: September 19, 2017
    Assignee: MultiDimension Technology Co., Ltd.
    Inventors: Zhimin Zhou, James Geza Deak
  • Patent number: 9553562
    Abstract: The compact C-multiplier includes four MOSFETs operating in the subthreshold region using the translinear principle. The multiplier is controllable to meet designer requirements. A Tanner Tspice simulator is used to confirm the functionality of the design in 0.13 pm CMOS Technology. The circuit operates from a ±0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: January 24, 2017
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Munir A. Al-Absi, Eyas Saleh Al-Suhaibani, Muhammad Taher Abuelma'atti
  • Patent number: 9374066
    Abstract: This document discusses, among other things, a resistance multiplier configured to provide a more specific and controllable resistance value, the resistance multiplier including an amplifier configured to control a resistance across a first transistor using a received reference resistance value and to control a resistance across a second transistor using the resistance across the first transistor and a relationship between the first and second transistors.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: June 21, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventor: Juha-Matti Kujala
  • Patent number: 9261541
    Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: February 16, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: David Maes, Bharath Mandyam
  • Patent number: 9225288
    Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: December 29, 2015
    Assignees: FUJITSU LIMITED, SOCIONEXT INC.
    Inventors: Kazuaki Oishi, Masahiro Kudo, Kotaro Murakami
  • Patent number: 9030251
    Abstract: A frequency converter, capable of obtaining resonance characteristics having a high Q factor and a high multiplication signal and having a narrow-band frequency selectivity function, is provided by the following configuration. A magnetoresistance effect element includes a pinned magnetization layer, a free magnetization layer, and a non-magnetic spacer layer disposed between the pinned magnetization layer and the free magnetization layer. In response to an input of a high frequency signal and a local signal, the magnetoresistance effect element generates a voltage signal (multiplication signal) by multiplying the signals by each other using a magnetoresistance effect. A magnetic field generated by a magnetic-field applying unit is applied to the free magnetization layer of the magnetoresistance effect element in a direction perpendicular to a film surface direction or by tilting an angle of the magnetic field from the film surface direction toward a direction perpendicular to the film surface direction.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 12, 2015
    Assignee: TDK Corporation
    Inventors: Yuji Kakinuma, Masato Takahashi
  • Patent number: 9007116
    Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Ying-Ta Lu, Mei-Show Chen, Chewn-Pu Jou
  • Publication number: 20150091632
    Abstract: An electronic device comprises an input transmission line that receives an input signal, an output transmission line that transmits an output signal, a local oscillator transmission line that transmits a local oscillator signal, multiple amplification and mixing stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal and mixing the amplified portion of the input signal with the local oscillator signal to produce a portion of the output signal, and multiple amplification stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal to produce a portion of the output signal. The amplification stages are located proximate an output side of the electronic device, and the amplification and mixing stages are located proximate an input side of the electronic device.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventor: Keith C. Griggs
  • Patent number: 8994435
    Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporation
    Inventor: Siraj Akhtar
  • Publication number: 20150070072
    Abstract: A harmonic mixer includes first through third field effect transistors. A gate electrode of the first field effect transistor is supplied with a positive-phase signal of a first signal. A gate electrode of the second field effect transistor is supplied with a negative-phase signal of the first signal. A source electrode of the second field effect transistor is short-circuited with a source electrode of the first field effect transistor and is grounded. A source electrode of the third field effect transistor is connected to a terminal at which drain electrodes of the first field effect transistor and the second field effect transistor are short-circuited. A gate electrode of the third field effect transistor is supplied with a second signal. A drain electrode of the third field effect transistor outputs a signal.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 12, 2015
    Inventors: Toshihiko YOSHIMASU, Takayuki SHIBATA
  • Patent number: 8912090
    Abstract: An improved microwave mixer manufactured using multilayer processing includes an integrated circuit that is electrically connected to a top metal layer of a substrate. The microwave mixer includes: a first metal layer; a dielectric substrate on the first metal layer; a second metal layer directly on the substrate, at least two passive circuits arranged on the second metal layer and a top layer metal; a thin dielectric layer on the second metal layer, wherein the top layer metal is directly on the thin dielectric layer; an integrated circuit (IC) attached to the second metal layer, wherein the IC includes at least one combination of non-linear devices, and wherein the IC is directly connected to the passive circuits on the second metal layer; and a protection layer on the IC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: December 16, 2014
    Assignee: Marki Microwave, Inc.
    Inventor: Christopher Ferenc Marki
  • Patent number: 8907713
    Abstract: An apparatus of a Harmonic Rejection Mixer (HRM) for removing a harmonic component and an operating method thereof are provided. The HRM includes a Local Oscillator (LO), at least one frequency converter, at least two mixers, at least one phase converter, and a combiner. The LO generates an LO signal. The at least one frequency converter multiplies the LO signal using different variables to provide the same to at least two mixers. The at least two mixers convert a frequency band of an input signal using the LO signal provided from the LO and the at least one frequency converter. The at least one phase converter controls a phase of an output signal of at least one other mixer excluding one of the at least two mixers. The combiner combines an output signal of the one mixer with an output signal of the at least one phase converter.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Woo Cho, Jae-Young Ryu, Jong-Jin Kim, Hyun-Koo Kang, Yeon-Woo Ku, Jeong-Su Lee
  • Publication number: 20140355381
    Abstract: Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems. In one aspect, a nanoelectromechanical system (NEMS) based computing element includes: a substrate; two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element.
    Type: Application
    Filed: May 8, 2014
    Publication date: December 4, 2014
    Applicant: CORNELL UNIVERSITY
    Inventors: Amit Lal, Serhan Ardanuc, Jason T. Hoople, Justin C. Kuo
  • Publication number: 20140354344
    Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.
    Type: Application
    Filed: March 28, 2014
    Publication date: December 4, 2014
    Applicant: Tektronix, Inc.
    Inventors: Daniel G. Knierim, John J. Pickerd
  • Patent number: 8847654
    Abstract: In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 30, 2014
    Assignee: Princeton Technology Corporation
    Inventors: Yang-Han Lee, Yung-Yu Wu, Huei-Huang Chen
  • Patent number: 8847662
    Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Mediatek Inc.
    Inventors: Wei-Hao Chiu, Ang-Sheng Lin
  • Publication number: 20140285250
    Abstract: A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.
    Type: Application
    Filed: January 29, 2014
    Publication date: September 25, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Kazuaki OISHI, Masahiro KUDO, Kotaro MURAKAMI
  • Publication number: 20140253214
    Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Rohit Goyal, Amit Kumar Dey
  • Publication number: 20140253215
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Application
    Filed: November 11, 2013
    Publication date: September 11, 2014
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Patent number: 8818310
    Abstract: The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 26, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Reza Bagger
  • Patent number: 8797112
    Abstract: An ASK modulator includes a baseband unit which obtains a sequence comprising at least one amplitude value and adds an additional value to each of the at least one amplitude value to generate a modified sequence; a digital-to-analog converter coupled to the baseband unit, the digital-to-analog converter converts the modified sequence to generate a first signal, the additional value is determined based on a half scale of the digital-analog converter; and a mixer which receives the first signal and a second signal and generate a modulated signal by mixing the first signal with the second signal.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Beken Corporation
    Inventors: Peng Han, Dawei Guo Guo, Jiazhou Liu, Yanfeng Wang
  • Publication number: 20140204985
    Abstract: Examples of a digital transceiver, a switched-capacitor sampling mixer, and an N-stage switched-capacitor amplifier are generally described herein. The digital transceiver may include a plurality of switched-capacitor sampling mixers and a plurality of N-stage switched-capacitor amplifiers. Each mixer samples a received differential RF signal. The pair of N-stage switched-capacitor amplifiers operates as charge redistribution amplifiers. Each N-stage switched-capacitor amplifier provides a near-constant capacitive load for one of the mixers.
    Type: Application
    Filed: December 9, 2013
    Publication date: July 24, 2014
    Inventors: Nicholas Cowley, Viacheslav Suetinov
  • Patent number: 8779834
    Abstract: A frequency mixer is disclosed. In an implementation, the multi-LO band switched-core includes a single field-effect transistor (FET) ring having a first mixer core and a second mixer core. The first mixer core and the second mixer core configured to connect to a radio frequency (RF) port and an intermediate frequency (IF) port. The frequency mixer also includes a first local oscillator (LO) transformer and a second LO transformer. The first LO transformer is configured to furnish a first LO signal occurring in a first limited range of frequencies to the first mixer core, and the second LO transformer is configured to furnish a second LO signal occurring in a second limited range of frequencies to the second mixer core.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: William T. Foley
  • Patent number: 8766730
    Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: July 1, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Mingquan Bao, Herbert Zirath
  • Patent number: 8766698
    Abstract: A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 1, 2014
    Assignee: Southeast University
    Inventors: Jianhui Wu, Chao Chen, Hong Li, Longxing Shi, Zixuan Wang, Jie Sun, Zhiyi Ye, Meng Zhang
  • Patent number: 8761703
    Abstract: An embodiment of a variable-gain mixer for down-converting a modulated input signal into a modulated output signal in a wireless receiver is proposed. The mixer includes means for selecting a mixer gain according to a power level of the input signal, amplifying means for amplifying the input signal into a modulated intermediate current (IRF+,IRF?) in response to a control signal indicative of the selected mixer gain, the intermediate current having an intermediate component, consisting of a direct current, varying according to the selected mixer gain, means for generating the output signal from the intermediate current, the output signal having an output component, consisting of a direct current or voltage, depending on the intermediate component; in an embodiment, the mixer further includes means for setting a compensation current in response to the control signal for compensating the variation of the intermediate component, and means for adding the compensation current to the intermediate current.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 24, 2014
    Assignee: Accent S.p.A.
    Inventor: Anabel Souto Diez
  • Publication number: 20140145778
    Abstract: A sub-harmonic electronic mixer has at least one field effect transistor (FET) having a gate, source, and drain; and a useful signal input at a useful frequency; and a local oscillator input. The input receives the oscillator signal at a frequency being an integral fraction of the useful frequency, plus or minus a mixing frequency to provide a signal output. A gate of the FET and/or the drain and/or the source receives the useful signal to generate a gate-source voltage and/or a drain-source voltage whereby the gate receives the local oscillator signal to generate a gate-source voltage, and the drain or a source receives the local oscillator signal to generate a drain-source voltage. A phase shift is introduced between the signal received at the gate and the signal received at the drain or source of the FET.
    Type: Application
    Filed: May 13, 2011
    Publication date: May 29, 2014
    Inventors: Hartmut G. Roskos, Alvydas Lisauskas, Sebastian Boppel
  • Publication number: 20140132330
    Abstract: A switching unit serves for the arithmetic linking of at least two input signals supplied to the switching unit. For this purpose, the switching unit provides a switching matrix to which the at least two input signals are supplied. The switching matrix applies at least one summation operation to at least two input signals and/or at least one multiplication operation to at least one input signal. Additionally or alternatively, the switching matrix can also connect at least one input signal directly through to a first output. The switching matrix comprises for this purpose several current switches.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 15, 2014
    Inventors: Alexander Schild, Alexander Kunze
  • Patent number: 8723588
    Abstract: In a mixer circuit that solves the problem of the extreme increase in circuit complexity that accompanies compensating for amplitude errors and phase errors, a voltage current conversion unit (11) converts an RF signal, which is a voltage signal, to a current signal and supplies the current signal. An RF path selection unit (12) connects its input terminal to any of its output terminals in accordance with the state of a four-phase clock signal and separately supplies, from its output terminals, a plurality of IF signals obtained by multiplying the RF signal by clock signals in the four-phase clock signal. An IF path selection unit (13) switches the connection relationship between its input terminals and its output terminals in accordance with a selection signal (S) and supplies the IF signal input to each of its input terminals from its output terminals that are connected to the input terminals.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: May 13, 2014
    Assignee: NEC Corporation
    Inventor: Masaki Kitsunezuka
  • Patent number: 8704582
    Abstract: A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33? percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the I-Q image and even order harmonics.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Ankush Goel, Neric Fong
  • Publication number: 20140105325
    Abstract: Disclosed is a communication modulator with sample rate conversion. The modulator comprises a symbol mapping module configured to map an input bitstream to a symbol sequence; a pre-distortion module configured to multiply the symbol sequence by a discrete frequency response to produce a pre-distorted symbol sequence; a modulation module configured to modulate the pre-distorted symbol sequence to a time-domain baseband sample sequence; a sample rate conversion module configured to convert the sample rate of the baseband sample sequence to a different sample rate to produce a sample-rate-converted baseband sample sequence; and an up-conversion module configured to up-convert the sample-rate-converted baseband sample sequence to an intermediate frequency signal. The discrete frequency response by which the pre-distortion module multiplies the symbol sequence is configured to compensate for passband droop introduced to the sample-rate-converted baseband sample sequence by the sample rate conversion module.
    Type: Application
    Filed: March 9, 2011
    Publication date: April 17, 2014
    Applicant: COMMONWEALTH SCIENTIFIC AND INDUSTRIAL RESEARCH SYSTEMS
    Inventors: Xiaojing Huang, Yingjie Jay Guo, Jian Zhang
  • Patent number: 8698545
    Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Tony R. Larson, Srikanth Vellore Avadhanam Ramamurthy, Dimitar T. Trifonov
  • Publication number: 20140097882
    Abstract: An improved microwave mixer manufactured using multilayer processing includes an integrated circuit that is electrically connected to a top metal layer of a substrate. The microwave mixer includes: a first metal layer; a dielectric substrate on the first metal layer; a second metal layer directly on the substrate, at least two passive circuits arranged on the second metal layer and a top layer metal; a thin dielectric layer on the second metal layer, wherein the top layer metal is directly on the thin dielectric layer; an integrated circuit (IC) attached to the second metal layer, wherein the IC includes at least one combination of non-linear devices, and wherein the IC is directly connected to the passive circuits on the second metal layer; and a protection layer on the IC.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 10, 2014
    Applicant: Marki Microwave, Inc.
    Inventor: Christopher Ferenc Marki
  • Patent number: 8665000
    Abstract: A method of frequency down-converting an input signal to an output signal, a first local oscillator signal is generated as a square wave having a duty cycle of 1/3 or 2/3, and the input signal is mixed with first oscillator signal to achieve a first down-converted signal, a second local oscillator signal is generated as a modified square wave having the same period time as the first oscillator signal and a duty cycle of 2/3, of which one part has a positive amplitude and another part has a negative amplitude. The input signal is mixed with the second oscillator signal to achieve a second down-converted signal. The first oscillator signal has a delay of 1/4 of the period time to achieve a phase shift of ?/2 between the oscillator signals, and at least one down-converted signal is multiplied by a pre-calculated factor. The resulting down-converted signals are added to achieve the output signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Stefan Andersson, Fredrik Tillman, Imad Ud Din, Daniel Eckerbert
  • Patent number: 8660514
    Abstract: A multiple mode RF circuit includes a switching network to switch the RF circuit between a mixer mode and amplifier mode of operation. Two differential amplifier stages coupled to a differential transistor pair form the core of the circuit. A differential local oscillator (LO) source is selectively coupled to the two differential amplifier stages for mixer operation by the switching network and a feedback loop is selectively coupled between the input of the differential transistor pair and the output of the two differential amplifier stages by the switching network for amplifier operation. Gain is controlled in both modes by varying the DC bias on the two differential amplifier stages so that partial cancellation of the amplified signal from the differential transistor pair occur at the RF output. The multiple mode RF circuit operates over a large dynamic range by adjusting a bias current to scale linearity.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 25, 2014
    Assignee: Rockwell Collins, Inc.
    Inventor: Russell D. Wyse
  • Publication number: 20140047920
    Abstract: Provided is a technology capable of preventing arithmetic operation accuracy from deteriorating even when a bipolar transistor used to form a Gilbert multiplier core has poor characteristics. A correction current generating circuit (3) uses a constant current source (301) to feed a constant current I0 to an emitter of a bipolar transistor (Q7) being a first replica transistor having the same current gain ? as bipolar transistors (Q1 to Q4) that form the Gilbert multiplier core (101), to generate a current of ?·I0 on a collector side thereof. The current is output as a correction current ?·I0, and is added to each of one of input signals (±K1·Vy) of the Gilbert multiplier core (101) as a bias current, to thereby eliminate influence of the current gain ? on an output signal being a multiplication result.
    Type: Application
    Filed: April 25, 2012
    Publication date: February 20, 2014
    Inventor: Yoichi Nagata
  • Publication number: 20140043086
    Abstract: A frequency converter, capable of obtaining resonance characteristics having a high Q factor and a high multiplication signal and having a narrow-band frequency selectivity function, is provided by the following configuration. A magnetoresistance effect element includes a pinned magnetization layer, a free magnetization layer, and a non-magnetic spacer layer disposed between the pinned magnetization layer and the free magnetization layer. In response to an input of a high frequency signal and a local signal, the magnetoresistance effect element generates a voltage signal (multiplication signal) by multiplying the signals by each other using a magnetoresistance effect. A magnetic field generated by a magnetic-field applying unit is applied to the free magnetization layer of the magnetoresistance effect element in a direction perpendicular to a film surface direction or by tilting an angle of the magnetic field from the film surface direction toward a direction perpendicular to the film surface direction.
    Type: Application
    Filed: September 7, 2012
    Publication date: February 13, 2014
    Applicant: TDK CORPORATION
    Inventors: Yuji Kakinuma, Masato Takahashi
  • Patent number: 8629698
    Abstract: There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit 803 including a grounded-gate MOS transistor M1 with a source into which an input signal is input, and a grounded-source MOS transistor M2 with a gate into which the input signal is input; a frequency converter 802 for converting frequencies of a first current signal output from the grounded-gate MOS transistor M1 and a second current signal output from the grounded-source MOS transistor M2, and for generating a third current signal and a fourth current signal; a load MOS transistor M7, with a gate and a drain connected, for receiving a third current signal; and a load MOS transistor M8, with a gate and a drain connected, for receiving a fourth current signal.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: January 14, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Yosuke Ueda
  • Patent number: 8624657
    Abstract: A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: January 7, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Christopher Jacques Beale, Bernard Mark Tenbroek
  • Patent number: 8624659
    Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a first input voltage. The current passing through the voltage controlled resistance circuit is based upon a second input voltage. The first transistor and the second transistor form a current mirror to mirror the current passing through the voltage controlled resistance circuit to provide a power supply control current to a wideband code division multiple access radio frequency power amplifier.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: January 7, 2014
    Assignee: RF Micro Devices, Inc.
    Inventors: Praveen Varma Nadimpalli, Joseph Hubert Colles
  • Patent number: 8624660
    Abstract: In one aspect, the present invention exploits the termination conductances of a time-discrete harmonic mixer as another degree of freedom in configuring the mixer to meet given harmonic rejection performance requirements while using reduced number of unit cells. The values of these termination conductances are purposefully configured to introduce a desired non-linearity in quantization of the mixer transconductance by the unit cells. The non-uniform quantization produces a non-linear fitting of the transconductance levels to the transconductance points defining the target sinusoidal waveform. As a consequence of its termination conductance configuration, the contemplated mixer achieves levels of harmonic rejection with that would not be met if the reduced number of unit cells operated with uniform quantization. As a further advantage, the manipulated conductance values generally are lower than those used in conventional designs, e.g.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: January 7, 2014
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Lars Sundström, Martin Anderson
  • Publication number: 20140002173
    Abstract: A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.
    Type: Application
    Filed: April 5, 2013
    Publication date: January 2, 2014
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, SK hynidx Inc.
    Inventors: Hong June PARK, Ji Hun LIM