Abstract: A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

Abstract: Embodiments herein describe input devices that include receivers for sampling capacitive sensing signals. In one embodiment, the receivers perform continuous demodulation where the sampling of the capacitive sensing signal is not synchronized with the modulated signal applied to the sensor. To calibrate, the receiver generates first and second measurements of the capacitive sensing signal when driving a modulated signal onto one or more sensor electrodes during two respective time periods. However, the phase of at least one signal is controlled during the time periods so that the first and second measurements have a phase difference of ninety degrees. Using the first and second measurements, the receiver can determine a phase offset between the capacitive sensing signal and the modulated signal which can be used to alter future measurements so that at least some of these measurements are captured when the capacitive sensing signal is at a peak amplitude.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.

Abstract: The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.

Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: There are provided a Schmitt trigger circuit that has hysteresis characteristics in which a release point and an operating point are determined based on a width of an inputted pulse.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: A communication apparatus including: a modulator which modulates a reference clock signal having a predetermined basic frequency and outputs a modulated clock signal whose value fluctuates at a first frequency with respect to the basic frequency; a PWM signal generator which generates a PWM signal at a second frequency, with the modulated clock signal being as an operation clock; a switching portion which outputs a signal by switching an analog signal on the basis of the PWM signal; a filter which passes a signal included in an output signal of the switching portion, a frequency of the passed signal being lower than a third frequency, and a setting portion which sets the first frequency and the second frequency such that a fourth frequency in which a duty value of the PWM signal fluctuates is higher than the third frequency and such that the first frequency is higher than the second frequency.

Abstract: Circuits and methods of dynamic modulation are disclosed. A dynamic modulator is used to reduce measurable conducted and/or radiated electromagnetic interference (EMI). The dynamic modulator is configured to generate either a set of optimal frequency modulation depths or discrete frequencies or both, and dynamically selects them to use over a series of programmable time durations (dwell time). Together with the utilization of Peak, Average or Quasi-Peak (QP) method of measurement, the dynamic modulator can reduce the spectral amplitude of EMI components, in particular the lower harmonics, to effectively pass regulatory requirements. In alternative embodiments, the dynamic modulator is used in a closed loop system to continuously adjust the frequency and the duty cycle of a PWM signal to reduce conducted and/or radiated EMI.

Abstract: An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.

Abstract: A low noise oscillator includes a resonator 102 that is excited with a pulsed signal (i.e., an impulse of energy) to replace energy lost to parasitic resistive losses once every Nth period (where N=1, 2, 3 . . . ). The resonating signal is monitored by a level detector and when the signal falls below a predetermined threshold, the pulse generator outputs a pulse or adjusts pulse width, pulse amplitude (or both) of a pulsed signal to create the necessary impulse for application to the resonator to recoup losses resulting from resonator operation. A phase shifting circuit may be provided to ensure the pulses are time aligned with the resonating signal to reduce noise.

Abstract: A random clock generator for a spread spectrum modulating device includes a random number generator for generating a plurality of random number signals according to a first square wave signal and a control signal, a reference wave generator coupled to the random number generator for generating a triangular signal and a second square wave signal according to the plurality of random number signals, and a trigger signal generator coupled to the random number generator and the reference wave generator, for generating the first square wave signal according to the second square wave signal.

Abstract: A system for controlling the delay applied to one branch of a pulse width modulation amplifier. The delay typically incorporated whether input signal level is low and diminished when the input signal level increases. The system may be implemented using a switch, a level detector and a timer, which in conjunction determine whether the delay unit is included in the branch or bypassed. The system may also use a programmable delay that can adjust the period of delay applied or be programmed to operate as a pass-through where delay is no longer beneficial for providing high signal quality.

Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.

Abstract: The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.

Abstract: A circuit drives an LED array and controls the brightness of the LED array by regulating the current flowing through the array. The LED array is driven by a pulse-shaped current of which the mean value is regulated with at least one or two of the following types of modulation: frequency modulation, pulse-width modulation, and amplitude modulation.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

Abstract: A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

Abstract: The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, coupled to the PWM controller, detects a load of the electronic system according to the PWM signal and generates a decision value accordingly. The adjusting module, coupled to the PWM controller and the load detector, controls the PWM controller to adjust the PWM signal according to the decision value.

Abstract: A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit is to output detecting pulses in response to any input pulse. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse.

Abstract: A digital modulator for driving a digital amplifier. The digital modulator has a subtractor which receives a digital input signal. A filter amplifier receives the output of the filter amplifier and is tuned to an idle frequency of the digital modulator. The digital modulator includes a delay element and a digital comparator. The digital comparator receives the output from the filter and applies it to the delay element. A feedback loop couples the output of the delay element to the subtractor.

Abstract: A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further determine whether the falling edge of the output clock should be triggered by the rising or the falling edge of the falling edge of the input clock signal. The counter may be implemented as a M/N:D counter in which a phase accumulator is compared to predetermined values to select the rising and falling edges of the output clock signal. In a default condition, the rising and falling edges of the output clock signal are triggered by rising edges of the input clock signal. However, if the accumulated phase value is greater than or equal to M/2 and less than M, an overriding signal will trigger the rising edge of the output clock based on the falling edge of the previous input clock cycle.

Abstract: A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated circuit. The low frequency receiver may be a conventional level based receiver. The high frequency receiver is a Schmitt-trigger with hysteresis around a DC level or two comparators with separate reference voltages. The outputs of these receivers are combined to produce a receiver output that has increased reliability and noise immunity.

Abstract: Systems and methods for independently adjusting a duty cycle of an input clock signal in an IC to compensate for uncertainties and distortions in the logic signals resulting from the logic signals propagating through the IC to improve system performance. This is accomplished by inputting first and second programming instructions into one of a plurality of edge-triggered circuits to select one of a series of plurality of incremental or decremental duty cycle adjust circuits to adjust the duty cycle of a clock signal as a function of the first and second programming instructions.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

Abstract: A neutralization of an equivalent parallel capacitor of a piezoelectric resonator is realized to obtain a stable activation of oscillation and secure a large frequency variation. A crystal resonator is connected between an input and output terminals of an inverting amplifier to form a Colpitts-type oscillator circuit, an input terminal of another inverting amplifier is connected to the output terminal through a capacitor and the output terminal is connected to the input terminal through another capacitor to form a Miller capacitor circuit for electrically neutralizing a parallel capacitor existing equivalently between both sides of the crystal resonator.

Abstract: Duty measuring circuitry of the present invention includes a pulse detecting circuit for detecting at least one of a convex pulse width and a concave pulse width included in an input data signal. A duty decision circuit determines whether or not the convex pulse width or the concave pulse width detected is smaller than a preselected value. If the detected pulse width is smaller than the preselected, the duty decision circuit determines that the pulse width is valid, and feeds it to an averaging circuit. The circuitry obviates the need for an exclusive fixed pattern, e.g., ONEs and ZEROs alternating with each other customarily used for the measurement of a duty. In addition, the circuitry is capable of accurately measuring a duty even with a random pattern based on RZ (Return-to-Zero) code or NRZ (Non-Return-to-Zero) code.

Abstract: A minimum pulse width detection and regeneration circuit is achieved. The circuit includes, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.

Abstract: A duty cycle discriminating circuit used, for example, in a VTR includes an up/down counter with sign bit for counting up or counting down a count clock signal depending on a potential level of a signal to be discriminated. It also includes an up counter for counting up the count clock signal, and an addend data generating circuit for producing an addend data having a value corresponding to a predetermined proportion of a count value of the up counter. There is an addition circuit with sign bit for adding a count value of the up/down counter and the addend data produced by the addend data generating circuit. The sign bit of the addition circuit is outputted as a discrimination result signal of the duty cycle discriminating circuit. The predetermined proportion of the count value up counter is specified to perform duty cycle discrimination of the signal by using a desired threshold point.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: An apparatus for synchronizing a plurality of signals entering an electronic device. In one embodiment, the apparatus comprises a filter to receive a signal of the plurality of signals entering the electronic device, wherein if a pulse width of the signal exceeds a first predetermined width, the filter outputs a pulse of a second predetermined width. The apparatus further comprises a pulse generator coupled to receive the pulse of the second predetermined width, and in response, to transmit a signal to elements of the electronic device to indicate a change of state of the signal.

Abstract: A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

Abstract: A device for removing a noise, in which a delay circuit is used for positively removing a noise contained in a signal regardless of the signal transitioning either from high to low or vice versa. The device includes a noise detecting part for comparing an input signal to a reference signal, to provide the reference signal if a pulse width of the input signal is smaller than a pulse width of the reference signal, and to provide the input signal if the pulse width of the input signal is greater than the pulse width of the reference signal. A noise removing part is also included for accounting and removing an output from the noise detecting part as a noise if the output from the noise detecting part is smaller than the pulse width of the reference signal and for determining and providing the output from the noise detecting part as a valid signal if the output from the noise detecting part is greater than the pulse width of the reference signal.

Abstract: A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.

Abstract: The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

Abstract: A method for generating an output signal of desired polarity from an input periodical signal of frequency f1 via a clock signal of frequency f2, wherein f2 is substantially greater than f1, is provided. The input periodical signal includes a cyclic duration T1 of a first logic state and duration T2 of a second logic state. The method includes the steps of (1) counting pulses N of the clock signal during T1; (2) counting pulses M of the clock signal during T2; (3) generating the output signal by inverting the input periodical signal as M being larger than N and an activated state of select signal are determined.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means.