Abstract: An inertial delay circuit includes a negative glitch removing circuit connected in series with a positive glitch removing circuit. The negative and positive glitch removing circuits are respectively configured to pass only negative and positive pulses of an input signal having a pulse width greater than a pre-determined width. The negative glitch removing circuit passes its input through a delay line and performs a logical OR on its input and the delayed signal. The positive glitch removing circuit passes its input through a delay line and performs a logical AND on its input and the delayed signal. The glitch removing circuits may further include respective pulse width restoring circuits to restore the pulses passing therethrough to their original widths.

Abstract: A phase lock detector for a digital phase locked loop frequency synthesiser in which phase errors, represented by phase error pulses of a duration equal to the relative time displacement of synthesised and reference waveforms in the phase locked loop, are compared with a predetermined time interval representing the maximum phase error acceptable in a phase-lock condition. A favourable result of the comparison may be required to persist for a predetermined time before a phase-lock indication is given, to avoid jitter or flicker of that indication in a near-lock situation.

Abstract: A detector circuit operating in parallel with a bandwidth limited measurement channel in a measurement instrument generates a warning signal when an input signal exceeds a predetermined repetition rate or has a pulse width less than a predetermined value. To provide a warning signal to the measurement instrument that the input signal contains high frequency components that are likely to be missed by the measurement channel, the detector circuit operates in parallel with the measurement channel. A pulse width in the input signal that is sufficiently narrow or a repetition rate that is too high causes the detector to generate the warning signal that is provided to the measurement instrument.

Abstract: An address transition detecting circuit comprising a first address transition detecting stage for generating a first address transition detection signal, the first address transition detection signal having a pulse width which is constant and stable when a supply voltage is relatively low, a second address transition detecting stage for generating a second address transition detection signal, the second address transition detection signal having the same pulse width as that of the first address transition detection signal from the first address transition detecting stage when the supply voltage is relatively high, a switching stage for switching selectively the first and second address transition detection signals from the first and second address transition detecting stages to an output line, and a supply voltage detecting stage for detecting a level of the supply voltage and controlling the switching stage in accordance with the detected level.

Abstract: A time domain signal filter detects a change in an input signal and replaces the input signal with an internally generated substitute signal for a filter period. The filter period is user selectable and can be set through a bit in a hardware register. After passage of the filter period, the time domain signal filter resumes direct supply of the input signal as the output signal. The time domain signal filter determines the start of the filter period by using either the falling edge or the rising edge of the clock input, whichever edge comes first after detecting the change in the input signal.

Abstract: A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Abstract: One embodiment of a circuit and corresponding method for generating a trigger signal upon the occurrence of either set up or hold time violations in the same waveform acquisition produces a trigger signal referenced to, but displaced in time from, the input clock signal. Transitions (13) in a data signal initiate a window pulse (14') whose duration is equal to the sum of a set up time requirement and a hold time requirement. The window pulse is used as the D input to a flip-flop (20) that is clocked by a version of a clock signal whose active edge has been delayed (28) for an interval that corresponds to the hold time requirement. The output of the flip-flop (20) is a trigger signal that only occurs when a set up or hold time violation has occurred. In another embodiment, triggers generated as the result of a set up time violation are referenced to the clock edge, while triggers that are generated as the result of a hold time violation are referenced to a transition in the data signal.

Abstract: A duty ratio discriminating circuit for discriminating a ratio of a high-level precedent portion to one period of an information signal whose level varies periodically, on the basis of threshold values. A sequencer outputs a shift signal to obtain a first threshold level, by detecting the precedent portion of the information signal to output a sampling signal. A subsequent portion of the information signal is detected to output a lath signal, and both the precedent and subsequent portions of the information signal are detected to output a reset signal. A counter circuit detects a time period of the precedent portion of the information signal by counting a number of reference clock signals to obtain count data. A shift circuit shifts the count data. A discriminating circuit obtains a discriminate point by comparing a time period of the subsequent portion of the information signal with a second threshold value corresponding to the count data shifted by the shift circuit.