Abstract: An electronic device according to various embodiments of the present invention comprises: a receiving circuit for outputting an AC power received wirelessly; and a rectifier circuit for rectifying the AC power being output from the power receiving circuit. The rectifier circuit comprises a forward rectifier circuit and a reverse rectifier circuit. A first terminal of the forward rectifier circuit is connected to the receiving circuit and the reverse rectifier circuit, a second terminal of the forward rectifier circuit is connected to an output terminal, and the forward rectifier circuit comprises first transistors for rectifying the AC power during a first period.

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

Abstract: A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or generating a first intermediate signal and a second intermediate signal. The first and second intermediate signals are output to a signal analog-to-digital converter having a predetermined sampling frequency.

Abstract: A dual-band Doherty amplifier and method therefor are provided. The dual-band Doherty amplifier includes a first amplifier gain element, a first transmission line coupled to a first output of the first amplifier gain element, a second amplifier gain element, a second transmission line coupled to a second output of the second amplifier gain element, and a controller configured, when a signal to be amplified is in a first band, to provide a first bias signal to a first bias input of the first amplifier gain element and a second bias signal to a second bias input of the second amplifier gain element and, when the signal is in a second band, to provide the second bias signal to the first bias input of the first amplifier gain element and the first bias signal to the second bias input of the second amplifier gain element.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.

Abstract: A maximum power point tracking controller includes an input port for electrically coupling to an electric power source, an output port for electrically coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control switching of the control switching device to regulate a voltage across the input port, based at least in part on a signal representing current flowing out of the output port, to maximize a signal representing power out of the output port.

Abstract: A current-mode analog computational circuit can be controlled to produce multiplying, squaring, divider and inverse functions and corresponding current outputs. The current-mode analog computational circuit is based on an implementation using MOSFETs operating in a sub-threshold region as can provide relatively ultra-low power dissipation. Furthermore, the current-mode analog computational circuit can be operated from a ±0.75 V DC supply. Tanner simulation results conducted using a 0.35-?m TSMC CMOS process confirmed the functionality of the multiplying, squaring, divider and inverse functions of the circuit. The current-mode analog computational circuit advantageously can have a total power consumption of 2.3 ?W, a total harmonic distortion is 1.1%, a maximum linearity error of 0.3% and a bandwidth of 2.3 MHz.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.

Abstract: A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output.

Abstract: Power mixer arrays for providing watt-level power in mobile systems. In one embodiment, a fully-integrated octave-range CMOS power mixer that occupies only 2.6 mm2 using a 130 nm semiconductor process has been demonstrated. The power mixer provides an output power of +31.5 dBm into an external 50 ? load with a power added efficiency (PAE) of 44% at 1.8 GHz and a full power gain compression of only 0.4 dB.

Abstract: A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Abstract: A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA.

Abstract: A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract: A divider has a clock generation circuit which combines a first trigger clock and a second trigger clock having a first phase difference, so as to generate a third clock having pulse edges corresponding to pulse edges of the first trigger clock and the second trigger clock; an output dividing circuit which divides the frequency of the third clock in half so as to generate a first differential output clock and a second differential output clock having a duty ratio corresponding to the first phase difference; and a phase correction circuit which detects a phase of the first output clock or the second output clock at a timing of the pulse edge of the first trigger clock or the second trigger clock, so as to generate a phase correction signal for resetting the output dividing circuit when the detected phase is not a normal phase.

Abstract: A multiplier circuit to multiply a first signal with a second signal includes an analog-to-digital converter that has a first input and a second input. The first input is to receive the first signal. The multiplier circuit also has an inverting circuit having an input to receive the second signal, and an output connected to the second input of the analog-to-digital converter. An output value produced by a combination of the analog-to-digital converter and the inverting circuit is approximately a multiplication of the first signal and the second signal.

Abstract: A circuit for producing a quotient of two input voltages, Vy and Vx has a resistor across which said two input voltages are selectively successively applied. An operational amplifier has a reference potential (Vref) applied to one input, and a tap selectively connectable at one side to various points of the resistor is connected at its other side to the other input of the operational amplifier. The tap also provides a voltage output node of the circuit. After the tap has been configured with input voltage Vy applied across the resistor so that a voltage on the output node is substantially equal to the reference potential (Vref), when the input voltage Vx is applied across the resistor, a voltage on the output node represents a quotient of the input voltages Vy and Vx.

Abstract: The power combiner/distributor for performing one of power combination and power division, includes: a first branch circuit (117) having a plurality of first branch side terminals (113, 114) connected in parallel and one first combination side terminal (115), which are connected through a first power combination point (116); and a second branch circuit (137) having a plurality of second branch side terminals (133, 134) connected in parallel and one second combination side terminal (135) connected through a second power combination point (136), the one first combination side terminal and the one of plurality of second branch side terminals being connected to each other, in which a length from the first power combination point to the second power combination point is an integral multiple of ½ wavelength.

Abstract: A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.

Abstract: Provided are a harmonic rejection mixer and a harmonic rejection mixing method. A plurality of oscillator signals having a ? duty cycle and uniform phase differences may be generated and a differential or quadrature mixer with harmonic rejection may be realized by using the oscillator signals.

Abstract: A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a 1/2-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

Abstract: An apparatus and method is disclosed to calculate the actual received desired channel power from the downstream transmit power of a Cable Modem Termination System (CMTS) when operating at the nominal line voltage and/or at the normal room temperature as per the DOCSIS specification. A Set-top Device produces a Downstream Power Management (DPM) gain measurement signal having a known power level. The Set-top Device embeds the DPM gain measurement signal onto a received downstream multi-channel communication signal. After embedding the DPM gain measurement signal onto the downstream multi-channel communication signal, the Set-top Device downconverts the combined DPM gain measurement signal and downstream multi-channel communication signal to recover one or more communication channels containing information of a broadcast.

Abstract: The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal.

Abstract: Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary metal-oxide-semiconductor (CMOS), in that, it is not a true CMOS type circuitry that has no DC current dissipation, but nevertheless does operate well at relatively high frequencies and relatively low power supply voltage levels. Appropriately placed p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs) and n-channel MOSFETs (e.g., N-MOSFETs) are employed to provide for an all digital divider circuitry. In some embodiments, four active circuitry element levels are stacked between a power supply voltage and ground voltage level. In other embodiments, three active circuitry element levels are stacked between a power supply voltage and ground voltage level. The three active circuitry element levels embodiment provides for a greater area savings (e.g.

Abstract: The sampling circuit of the present invention includes a latch circuit 12 which latches the digital signal S1 at a constant period, an addition register 13 which adds the sampled data for the same input code, a divider 15 which divides the added value by a predetermined divisor, a digital memory which stores the divided value and outputs it at an arbitrary timing for a predetermined reading out number, an operator which operates the output data from the digital memory 16 in accordance with an algorism that is previously set, and a judgment circuit 13 which judges the operation result with a predetermined judgment criterion, and a control logic part 11 which controls such that the addition and outputting processing by the addition register 13 and the division and outputting processing by the divider 15 are carried out concurrently with the sampling processing that is performed by the latch circuit 12. Thereby, a sampling circuit in an AD converter or a DA converter that can reduce the inspection cost.

Abstract: Methods, systems, and apparatuses, for down-converting and up-converting an electromagnetic signal. In embodiments the invention operates by receiving an EM signal and recursively operating on approximate half cycles of the carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In embodiments, up-conversion is accomplished by controlling a switch with an oscillating signal, the frequency of the oscillating signal being selected as a sub-harmonic of the desired output frequency. When the invention is being used in the frequency modulation or phase modulation implementations, the oscillating signal is modulated by an information signal before it causes the switch to gate the bias signal. The output of the switch is filtered, and the desired harmonic is output.

Abstract: Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I?) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q?) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.

Abstract: A mixer capable of detecting or controlling a common mode voltage thereof, includes at least: a mixing module for mixing a first set of differential signals and a second set of differential signals to generate at least one mixed signal; and a compensation module for compensating at least one operation point of the mixing module.

Abstract: A signal converter is comprised of a plurality of counters (“macro-counters”). In turn, each of the macro-counters is comprised of a plurality of single-bit counters (“micro-counters”) that are adapted to receive configuration data in the form of bit fields. The configuration data is comprised of data corresponding to a plurality of coefficients and of data for grouping the micro-counters into the macro-counters. The coefficients are derived from an input signal/output signal ratio of the converter, and control the manner by which the macro-counters generate the output signal. Thus the converter can be programmed by an end-user in the field.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A loading circuit capable of canceling a DC offset and a mixer using the same. The loading circuit includes a first current mirror unit and a second current mirror unit for respectively receiving a first input signal and a second input signal and generating a first signal current and a second signal current proportional to the first and second input signals, a first compensation unit and a second compensation unit for respectively receiving the first and second input signals, filtering AC components of the input signals, and generating a first compensation current and a second compensation current proportional to the DC components of the first and second input signals, a first loading unit for receiving the first signal current and the second compensation current and generating a first output signal, and a second loading unit for receiving the second signal current and the first compensation current and generating a second output signal.

Abstract: The present invention introduces an integrated analog multiplier-divider circuit. The multiplier-divider block according to the present invention is ideal for use in the power factor correction (PFC) controllers of many switch-mode power supplies. The analog multiplier-divider according to the present invention is built with CMOS devices. Because of this, it has many advantages over prior-art multiplier-dividers. One important advantage is that the die-size and the cost can be reduced. Another important advantage of the multiplier-divider according to the present invention is substantially reduced temperature dependence.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A method and apparatus are provided for driving an electro-optic converter assembly with an information signal. The method includes the steps of disposing a resistor having a resistance substantially equal to a resistance of the electro-optic converter adjacent the electro-optic converter, coupling the electro-optic converter and resistor together, in series, to form a current loop, driving the electro-optical converter end of the current loop with the information signal and driving the resistor end of the current loop with an opposite polarity of the information signal.

Abstract: The switched charge multiplier-divider according to the present invention is constructed of CMOS devices. Capacitor charge theory is employed to implement the circuit of the switched charge multiplier-divider. The switched charge multiplier-divider includes an output capacitor and controls the voltage across the output capacitor, so that it is proportional to the product of the charge current and the charge-time interval. The switched charge multiplier-divider is ideal for use in the power factor correction (PFC) of switching mode power supplies. Potentially, it can also be applied to automatic gain control (AGC) circuits.

Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.

Abstract: Circuits and methods for generating signals representing the division or multiplication of two analog signals are incorporated into optical triangulation distance measurement systems. In one embodiment one of two analog voltage signals is used to generate a current signal. A capacitor is charged by the current signal. The voltage on the capacitor is compared with the other analog voltage signal and a signal is generated that has a time interval representing the division of the two analog voltage signals. In the application of the circuit and method to optical triangulation distance measurement the time interval signal is further processed to obtain distance measurement to a target.

Abstract: A divider circuit provides a divide operation with a multiplier, counter and comparator. The divide operation of two values, x and y, to produce the value of x divided by y, x/y, is provided by sequentially multiplying y in the multiplier with values from the counter until the product of y and a current counter value is determined to cross a unity level, or "1," as determined by a comparator. Therefore, the current value in the counter is approximately equal to 1/y. Then, the determined value of 1/y is multiplied by x to provide x/y. A preferred embodiment of the divider circuit employs a single multiplier, and the divide circuit includes a mux, a multiplier, a counter, a comparator, and an optional buffer. The mux receives two values x and y and a selection signal provided by the comparator. The counter is loaded with an initial value, which may be a zero dataword.

Abstract: A voltage subtracter circuit of the present invention includes a constant current source 1, a first MOS transistor pair 2, one end of which is connected to a source voltage terminal, and a second MOS transistor pair 3, one end of which is connected to the constant current source 1. A first differential input voltage is applied between the gate terminals of the first transistor pair 2, and a second differential input voltage is applied between the gate terminals of the second transistor pair 3. Output terminals V1 and V2 are connected to the connecting point between the first and second transistor pairs 2 and 3. From these nodes V1 and V2, a differential voltage between the first differential input voltage and a differential voltage proportional to the second differential input voltage is outputted.

Abstract: Self-oscillation of a prescalar circuit is avoided by including offset generators on the inputs of the prescalar circuit. This ensures that when the transistors in one differential pair in the prescalar circuit transition from ON to OFF, the other differential pair of transistors will not transition. As a result, spikes are prevented in the differential pair that does not have a transition. A quadrature signal generator constructed with such a prescalar circuit provides an accurate output despite weak or non-existent input signals.

Abstract: A method for correcting an amplitude error between an I signal and a Q signal which are outputted from a quadrature detector including a first multiplier for multiplying a reference signal and a measured signal, a first integrator for smoothing the output of the first multiplier to generate the I signal, a 90-degree phase shifter for generating an auxiliary reference signal from the reference signal, a second multiplier for multiplying the auxiliary reference signal and the measured signal, and a second integrator for smoothing the output of the second multiplier to generate the Q signal. The method includes the step of inputting the auxiliary reference signal, instead of the reference signal, to the first multiplier to obtain a first output signal and inputting the reference signal, instead of the auxiliary reference signal, to the second integrator to obtain a second output signal.

Abstract: An analog arithmetic circuit directly divides an input voltage by another input voltage with high accuracy without requiring a logarithmic conversion process or an adjustment process. The analog arithmetic circuit includes: an integrator for integrating a dividend signal and a feedback signal; a hysteresis comparator having two threshold levels to compare an output signal of the integrator and generates a comparison output; a limiter which receives the comparison output and a divisor signal and generates the feedback signal that is proportional to the divisor signal; an average circuit connected to an output of the hysteresis comparator to generates an average value of the comparison output as a quotient signal.

Abstract: A sawtooth generates a sawtooth wave having a high response speed and good linearity with a simple arrangement in converting a change in phase of an input signal into a linear level change. A signal interpolating apparatus uses this sawtooth wave to output a predetermined signal (interpolation signal) every predetermined phase change of the input signal with a simple arrangement. An arithmetic operation section receives two sinusoidal signals A and B having equal periods and phases which are offset by 90.degree. and with respect to each other, obtain a signal X=A/(B+a) and a signal Y=A/(B+B) using constants .alpha. and .beta. respectively satisfying B+.alpha..apprxeq.0 and B+.beta..apprxeq.0. A switching unit selects the linear ramp portions of the signals X and Y to output a continuous sawtooth wave. On the basis of the value of this sawtooth wave, a desired interpolation signal is output from a memory which stores predetermined data.

Abstract: An analog calculating circuit capable of storing data.A calculating circuit according to the present invention converts an analog voltage level to a time value by using a charging voltage of an RC circuit and stores the time value as a number of clock cycles in a digital counter. The circuit then converts another voltage level to a second time value and either adds the second time value to or subtracts it from the first time value. This yields a time value corresponding to a multiplication or division, respectively, of the analog voltage levels.

Abstract: A circuit for providing an output current proportional to a first voltage raised to a fractional exponential power divided by a second voltage raised to a fractional exponential power, is supplied. The circuit has four strings of series connected pn junctions. The first and second voltages are connected to the first and fourth string, respectively. A reference current is provided to the second string, while the third string provides the output current. The number of pn junctions are chosen to give the desired fractional exponents of the two voltages while the number of pn junctions in the third string is selected to adjust for the number of pn junctions in the other strings.