Abstract: Circuitry for amplifying a single-ended analog sensor output includes a field effect transistor (FET) having a gate connected to a first end of a capacitor, the second opposite end of which is connectable to the sensor output. The gate of the FET is also connected to a first end of a resistor and to a cathode of a diode. The anode of the diode, the opposite end of the resistor and the drain of the FET are connectable to a ground reference, and the source of the FET defines an amplifier output that is connectable to a constant current source. The capacitor, resistor and diode are operable to bias the FET to thereby prevent clipping of the output signal at the amplifier output. A high-pass filter is also provided at the second end of the capacitor, and a number of diodes are preferably included for providing for amplifier input protection, electrostatic discharge protection and output DC overvoltage protection.

Abstract: A CMOS driver circuit for high-speed data transmission has a complementary differential switch formed by four transistors, a bias cell containing current mirrors controlled by a reference current, two drive-current limiting devices for limiting the drive current to a required value via the bias cell, a current-shunting switch, and buffers which drive each of the gate nodes of the switches. CMOS transistors used in these buffers are limited in size to limit the rate at which they operate the switches and to limit the rate at which current is steered from one side of the differential switch to the other. One supply side of each of these buffers is connected to one of the current-limited supply nodes of the main output switches, thus greatly reducing variations in switching rate. The CMOS devices have sizes optimized to achieve both the required switching speed and minimized sensitivity to variations affecting switching speed.

Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

Abstract: Current switches are arranged to reduce signal transit-time variations when they switch current signals that have a wide range of current magnitudes. The transit-time variations are reduced by shifting the range of currents that are carried by switching transistors. In particular, a current range is shifted upward to a higher current range in which the variation of the transistors' transition frequency fT is reduced. In general, the switches include a differential pair of transistors, an offset current source that generates an offset current and a current-steering system that steers the offset current along a current path that includes a switched-on transistor but excludes the output port of that transistor.

Abstract: The present invention relates to a bus control buffer amplifier. The output terminal is associated with a first pull-down N-channel MOS transistor and with a second pull-up N-channel MOS transistor. The first N-channel MOS transistor is directly controlled by an input signal. The second MOS transistor is an N-channel transistor, and its gate is controlled by a third pull-down N-channel MOS transistor directly controlled by the input signal, and by a fourth pull-up N-channel MOS transistor, which is controlled by the inverted input signal. The fourth N-channel MOS transistor has a very abrupt drain-substrate junction.

Abstract: A driver circuit (12) having a controlled transition rate is provided. The driver circuit (12) includes a first device (56) operable to switch a supply voltage to load. A second device (54) is coupled to an input for the first device (56) in source follower arrangement. A third device (66), coupled to the input for first device (56) and an output for the second device (54), is operable to function as a Miller amplifier in conjunction with the first device (56). A fourth device (152) is coupled to an input of the second device (54). The fourth device (152) is operable to function as a Miller amplifier in conjunction with the first device (56) and the second device (54). A capacitor (68) is coupled between an output for the first device (56) and inputs for the third device (66) and the fourth device (152). The capacitor (68) is operable to function as a Miller capacitor to control transition rates at the output of the first device (56).

Abstract: A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the overdrive voltage applied to a driver transistor.

Abstract: A plurality of output transistors for an output buffer of a semiconductor device are provided in parallel. Potentials to be applied to gates of output transistors are set to different levels upon conduction of the output transistors. By sequentially rendering the transistors conductive in the order of increasing voltage during conduction, rapid flow of a large amount of current is prevented, thereby reducing ringing. More preferably, the transistors are increased in size according to the order of conduction of the output transistors.

Abstract: In a system of plural bus driver circuits connected to a shared bus line, each of the driver circuits has combinatorial logic responsive, driving a final clock cycle for an active driver, to the difference between the data input and output of a tri-state driver element so as to generate a control signal that maintains the driver element in a active state until the data input and output are identical and then providing early release of the driver element to an inactive state, so that the next driver circuit can be activated at the start of the next clock cycle without conflict.

Abstract: Generally speaking, steep signal edges are required for the processing of digital signals; however, notably externally supplied signals which are conducted, for example, via long cables are liable to have comparatively flat signal edges. By selecting appropriate switching thresholds, delays between an input signal and an output signal of a circuit can be minimized. The circuit selects the first switching threshold at a low value of the input signal and switches the first threshold value to a second, higher threshold value when the input signal exceeds a further, higher threshold value. Thus, an output signal is generated comparatively quickly after the beginning of the positive-going or negative-going edge of the input signal. This can be realized by switching over the switching threshold of a comparator or by utilizing two comparators.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: A driver circuit for slope-controlled pulsed switching of a load having a MOS switching transistor switching the load and a control loop with an amplifier having an amplifier input coupled with a switch control pulse source, an amplifier output connected with the gate of the MOS switching transistor, and a feedback capacitor. The driver circuit also includes a switchable current mirror circuit with a current mirror transistor formed by the MOS switching transistor and a diode transistor wired as a current mirror diode, a connection point between the diode transistor and the gate of the MOS switching transistor being connected with the amplifier output. A timer circuit is supplied on the input side with the switch control pulses from the switch control pulse source, and switches the diode transistor into a conductive state for essentially the duration of each switch control pulse edge and otherwise into a nonconductive state.

Abstract: A driver circuit (12) having a reduced propagation delay is provided. The driver circuit (12) includes a first device (56) having an input and operable to switch a supply voltage to a load (14). A second device (54) having an output coupled to the input of the first device (56), operable to turn on the first device upon receipt of a first signal. A third device (66) having an output coupled to the input of the first device (56), operable to turn off the first device upon receipt of a second signal. A kick start circuit (30) coupled to the input for the first device (56), the input for the second device (54), and the input for the third device (66), operable to generate a threshold voltage on the first device (56), the second device (54), and the third device (66). The kick start circuit (30) operable to produce a threshold voltage that is just below the voltage in which the first device (56), the second device (54), and the third device (66) turn on, or conduct.

Abstract: An integrated circuit including a primary operating circuit and an added-function circuit which reduces propagation delays during normal operation of the primary operating circuit, the primary operating circuit includes an input and an output, an associated voltage source and ground, a transistor positioned on the path from the voltage source to the output and a second transistor positioned on the path from ground to the output, the added-function circuit includes two transistors, each of which is coupled to a transistor of the primary operating circuit on the path from either the source or ground to the output, and the added-function circuit transistors have widths of at least two times the size of the primary operating circuit transistors such that when the added-function transistors are enabled, a pseudo-voltage source and a pseudo-ground are generated for the primary operating circuit transistors to reduce propagation delays in the primary operating circuit based on the added-function circuit.

Abstract: An N-channel power MOSFET includes a storage capacitor and a pair of diodes connected between the gate and drain terminals, respectively, and the capacitor. Since at any given time the voltage at either the drain or the gate of the MOSFET is high, a charge is maintained on the storage capacitor as the MOSFET is switched on and off. The charge stored on the capacitor yields an output voltage which may be used to power a gate drive circuit or other components within or outside the MOSFET.

Abstract: A power reduction circuit is provided that includes a first switching device between a first operating voltage terminal and a second operating voltage terminal being controlled by a first active signal. A second switching device is between a third operating voltage terminal and a fourth operating voltage terminal is controlled by the inverse active signal. A signal transfer gate logic coupled between the second and the fourth operating voltage terminals to selectively output one of the second and the fourth operating voltages. A first voltage drop device is between the first and the second operating voltage terminals and is selectively activated by a first control device according to one of a first and a second operating modes. A second voltage drop device is between the third and the fourth operating voltage terminals and is selectively activated by a second control device according to one of the first and the second operating modes.

Abstract: An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step.

Abstract: An output circuit which outputs a data signal from an output terminal after setting the output terminal to a potential intermediate between a power supply line potential and a ground line potential. The output circuit includes an output drive configured of first and second transistors. The first transistor has a first control terminal to which is input a first control signal. The second transistor has a second control terminal to which is input a second control signal. It further includes a setting member which controls the first and second control signals to set the first and second transistors to the off state. It further includes a shorting member which shorts one of the first and second control terminals and the output terminal. Moreover, before the data signal is output, the transistors are set to the off state by the setting member, after which shorting is carried out according to the potential of the output terminal, and the output terminal is set to an intermediate potential.

Abstract: A trigger circuit for a field-effect-controlled power semiconductor component has a controllable gate resistor for the power semiconductor component, which has low impedance in a normal situation and is switched to high impedance in the event of a short circuit. As a result, the turn-on time in the normal situation is shortened, and limiting the gate-to-source voltage of the power semiconductor component in the short-circuit situation is made possible.

Abstract: The level converting circuit has first and second transistors of a first conductivity type. The control terminals of the transistors are connected to a first supply potential via the load path of the respective other transistor. A load path of a third transistor of a second conductivity type is connected between the control terminal of the first transistor and a reference-ground potential. The control terminal of the third transistor is coupled to the input of the level converting circuit. A node between the second and third transistors forms the output of the circuit. A fourth transistor of the second conductivity type has a load path connected between the control terminal of the second transistor and the control terminal of the third transistor. A capacitance is connected between the control terminals of third and fourth transistors. A limiter circuit is connected upstream of the control terminal of the fourth transistor.

Abstract: A circuit is provided to switch a drive transistor in a write driver circuit controlled by a write control signal to direct write current in a selected direction through an inductive head. Current is selectively conducted from a control region of the drive transistor in response to switching of the write control signal. A first bias circuit limits voltage fluctuation at the control region of the drive transistor. A second bias circuit prevents saturation of the drive transistor.

Abstract: A driving circuit for driving an IGBT includes a forward-bias power supply, a reverse-bias power supply, a forward-bias semiconductor switch, a reverse-bias semiconductor switch, a first resistor for limiting forward-bias current, and a second resistor for limiting reverse-bias current. In this driving circuit, one terminal of a capacitor is connected to a common node of the resistor for limiting forward-bias current, the resistor for limiting reverse-bias current, and a gate of the IGBT. A mode switching semiconductor switch is connected at one terminal to the other terminal of the capacitor. The other terminal of the mode switching semiconductor switch is connected to a common node of the forward-bias power supply and the reverse-bias power supply. In operation, the mode switching semiconductor switch is turned on and turned off so as to establish a given rate of change of voltage which is independently selected for turn-on and turn-off of the IGBT.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.

Abstract: A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.

Abstract: A milled tooth shaped rotary cone drill bit for drilling oil wells and the like manufactured using a powder metallurgy process in which an alloy powder is pressure molded into the desired bit shape, sintered, and precision machined.

Abstract: An integrated circuit driver drives a differential signal over a communication cable, such as a twisted-pair cable. The integrated circuit driver includes a differential pre-driver that receives an input signal having an about 50% duty cycle and produces an amplified differential signal that swings between a power rail level and a ground level. A signal conditioner circuit receives the amplified differential signal and outputs a conditioned differential signal. The conditioned differential signal swings between the power rail level and an intermediate power level. The integrated circuit driver further includes an output driver that receives the conditioned differential signal that swings between the power rail level and the intermediate power level. The output driver produces a differential output signal that is communicated to the communication cable. The differential output signal has an about zero signal crossing and maintains the about fifty percent duty cycle.

Abstract: A pulse output circuit which has an output stage connected to a capacitive load capable of improving a through-rate of an input pulse signal with reduced power consumption is provided.

Abstract: An N-channel power MOSFET is fabricated with its source and body connected together and biased at a positive voltage with respect to its drain. The gate is controlled by a switch which alternately connects the gate to the source or to a voltage which turns the channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and provides a lower-resistance path than a conventional PN diode. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch is particularly suitable for as a synchronous rectifier in a power converter where it reduces the power loss and stored charge in the "break before make" interval (i.e., the interval between the turn-off of the shunt switch and the turn-on of the synchronous rectifier).

Abstract: A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

Abstract: Disclosed is an integrated circuit comprising storage circuits, these circuits themselves comprising insulation transistors to which a determined positive bias voltage may be applied. This bias voltage is determined by means of a first bias circuit. The disclosed circuit comprises a second bias circuit whose time constant in response to a voltage step is smaller than the time constant of the first circuit in response to the same step, this second circuit making it possible to reduce the response time of the first bias circuit.

Abstract: A method for the turn-on regulation of an IGBT and an apparatus for carrying out the method are specified. In contrast to the prior art, the gate current is used as controlled variable rather than the gate voltage. Said gate current acts on the gate electrode according to a desired-actual comparison of an actual voltage value present at the gate electrode and of a corresponding desired value. The regulation guides the load current on a predetermined trajectory during the switching operation. Nevertheless, no current detection is necessary on the load side. Instead, use is made of the fact that, during the turn-on of the MOSFETs in the IGBT, the behavior of the latter predominates. It can be shown that there is a quadratic relationship between the gate voltage and the load current as soon as the gate voltage is greater than the threshold voltage. This is true until the full load current flows.

Abstract: A differential amplifier achieving a high throughput rate with reduced power consumption includes a differential circuit, output circuit, a constant current source transistor, a drive transistor, and a switching circuit. A difference voltage relative to a difference between voltages applied to non-inverting and inverting inputs of the differential circuit is applied to the switching circuit. The switching circuit supplies a drive signal to the drive transistor to enable the drive transistor when the difference voltage is below a predetermined threshold voltage, and to disable the drive transistor when the difference voltage is above the predetermined threshold voltage.

Abstract: An additional MOS transistor receiving at its control electrode a signal complementary to that applied to control electrodes of MOS transistors is provided between a power supply node and a control electrode line formed by resistors having a significant resistance and interconnecting respective control electrodes of MOS transistors which are connected in parallel and each of which is connected between output signal line and power supply node. When MOS transistors are rendered non-conductive, the additional MOS transistor is rendered conductive. As a result, internal nodes are driven by an inverter and the additional MOS transistor to a power supply voltage, thereby turning off MOS transistors at the same timing. Consequently, through current in a semiconductor output circuit can be suppressed and an output signal has no ringing.

Abstract: A low power regenerative feedback device and method automatically increases bias current during positive large-signal slewing, enabling output to change faster. When the device is not in a positive slew, bias currents are unchanged, providing a low standby current. Since regenerative feedback is internal and automatic to the device, current is increased only for the device driving an active column of an LCD panel. Thus, the present invention is power efficient. In addition, the AC response of the device is preserved because the device utilizes a regenerative feedback circuit that does not add appreciable excess phase shift. The device achieves an output that switches readily from positive supply to negative supply.

Abstract: A control circuit for providing fast turn on of a PNP transistor in which a capacitor charging current is boosted and provided to the base of the PNP transistor. An embodiment of the invention provides a current amplifier in parallel with a current source for coupling to the base of the PNP transistor. The PNP transistor is connected to a positive voltage supply. A capacitor is also coupled to the positive voltage supply for delivering a charging current amplifier. In a further embodiment, an NPN transistor has its base coupled to the capacitor and its collector coupled to the base of the PNP transistor for providing the drive current boost. A diode may be coupled to the capacitor for passing a discharge current to the capacitor when the PNP transistor is off and to block the capacitor current when the PNP transistor is being switched on. A PNP drive transistor may be coupled between the collector of the NPN transistor and the base of the PNP transistor.

Abstract: A design method using a device with a capacitance inserted in between the output of a MOS circuit and it's corresponding load. This creates a smaller equivalence capacitance to be seen by the MOS circuit. This in turn creates faster switching times and lower power dissipation. Careful design of the circuits which have the capacitor that was added in their input stage is necessary since the high voltage level that these circuits will see is now modified due to the voltage divider created by the added capacitor and the load capacitance. With careful optimization of all parameters involved, circuits could achieve superior switching speed or superior power performance or both compared to other circuits of the same size that do not use this technique.

Abstract: A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver.

Abstract: The present invention teaches a variety of electrical devices and methods for connecting a switch such as a transistor to decrease a voltage drop across an electrical coupling connecting the switch's source with a gate driver regulating operation of the switch, the voltage drop due, at least in part, to a change in current flowing through the switch. Decreasing the voltage drop from the switch's source to the gate driver tends to improve the operational characteristics of the switch. One embodiment of the present invention teaches an electronic device including a switch having a gate, a drain, and a source, and a plurality of source terminals. A gate bias voltage V.sub.gs (the voltage potential from the gate to the source) controls a flow of current through the switch between the drain and the source. The source terminals are each connected to the source by a distinct electrical coupling, each of the electrical couplings having some inductance.

Abstract: A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.

Abstract: A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

Abstract: A differential receiver that includes a first input, a second input, and an output has a first signal path from the first input to the output, the first signal path including a first differential amplifier and a first active load. The first differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the first active load. The first differential amplifier also has a connection to the first input and the second input, and the first active load has a connection to the output. The receiver also has a second signal path from the second input to the output, the second signal path including a second differential amplifier and a second active load. The second differential amplifier has an end connected to a first power supply voltage and a second end connected to a second power supply voltage and the second active load.

Abstract: Gate leakage in the DMOS transistor of a low-side driver device is detected and reported by utilizing a sense circuit to sense the voltage on the gate of the DMOS transistor, and by determining whether the voltage on the gate of the DMOS transistor has exceeded a predetermined value within a predefined period of time when the device is turned on.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1,/.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: Circuit arrangement of a driver using bipolar NMOS technology for generating fast high/low edges with a low bias current requirement.

Abstract: A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.

Abstract: An output buffer device utilizes a PMOS transistor as a first pull-up element and an NMOS transistor as a second pull-up element. An output signal is used to control a feedback circuit. An output signal is switched from a low to high voltage by a trigger voltage. The first pull-up element switches to the second pull-up element to complete the voltage switching from low to high. The device combines the high speed of the first pull-up element and the low noise of the second pull-up element.

Abstract: The invention is embodied in a receiver and a method for responding to an input signal. The input signal is received in a first stage of the receiver, which generates a first stage output signal responsive thereto. If the input signal does not exceed a first level, the first stage output signal is generated by an overvoltage element. That is, for this case, the overvoltage element passes the input signal through to the first stage output, and the first stage output voltage is not increased by a first stage pullup element. If, on the other hand, the input signal exceeds the first level, the first stage output signal voltage level is increased by the first stage pullup element to a higher output voltage level. The output signal from the first stage is received in a second stage. The second stage generates a second stage output responsive thereto.

Abstract: An N-channel power MOSFET is fabricated with its source and body connected together and biased at a positive voltage with respect to its drain. The gate is controlled by a switch which alternately connects the gate to the source or to a voltage which turns the channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and provides a lower-resistance path than a conventional PN diode. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch is particularly suitable for use as a synchronous rectifier in a power converter where it reduces the power loss and stored charge in the "break before make" interval (i.e., the interval between the turn-off of the shunt switch and the turn-on of the synchronous rectifier).

Abstract: A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage .[.equal.]. .Iadd.corresponding .Iaddend.to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.