Abstract: A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.

Abstract: Systems and methods are described herein for controlling a switch. In some embodiments, circuitry may detect a voltage across the switch. A current reference signal may be generated based on the voltage across the switch. The switch may be controlled based, at least in part, on the current reference signal.

Abstract: A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

Abstract: A semiconductor switch control circuit configured to perform an ON/OFF control of a semiconductor switch and includes: a pulse signal generating part configured to generate a pulse signal; a drive current generating part configured to generate a drive current based on the pulse signal which the pulse signal generating part generates and supplies the drive current to a gate electrode of the semiconductor switch; a gate voltage detecting part configured to detect a gate voltage VGS of the semiconductor switch; and a drive current control part configured to control the drive current which the drive current generating part generates based on the pulse signal which the pulse signal generating part generates and the gate voltage VGS which the gate voltage detecting part detects.

Abstract: A method for driving a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. The method includes providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process. The method includes transitioning from the first phase to the second phase based on the first indication and the second indication. A multi-die, distributed package technique addresses power dissipation requirements for a driver product based on size and associated power dissipation needs of the high-power drive device in a target application.

Abstract: The present invention provides a clock signal output circuit and a liquid crystal display device. The clock signal output circuit comprises a clock signal conversion unit, a voltage dividing unit, a protection signal generation unit, an over-current protection unit, and a switching unit. The protection signal generating unit comprises a subtractor, a comparator, a switch, a current source, and a capacitor.

Abstract: A semiconductor device includes a gate terminal, a ground terminal, a power-supply terminal, and a source terminal. The semiconductor device includes a first switch element having a gate and a source, the first switch element connected between the gate terminal and the source terminal, a second switch element connected between one of the gate of the first switch element and the source terminal or between the gate of the first switch element and the ground terminal and configured to switch the first switch element between turned-on and turned-off states, and a capacitor having one terminal thereof connected to the power-supply terminal and the ground terminal and another terminal thereof connected to the gate of the first switch element. Based on the potential state of the ground terminal and the state of the second switch element, the capacitor boosts the voltage of the gate of the first switch element.

Abstract: A vehicle powertrain includes an electric machine, an inverter including an IGBT having a gate configured to flow current through a phase of the electric machine, and a gate driver. The gate driver is configured to supply power onto the gate via a voltage regulated source, and in response to a collector current of the IGBT exceeding a previous steady state current through the phase, transition to a current regulated source to drive the gate. The gate driver may be configured to delay the transition by a predetermined time that is based on a difference between the previous steady state current and a reverse recovery peak current.

Abstract: Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

Abstract: Unique systems, methods, techniques and apparatuses of a reverse-conducting IGBT (RC-IGBT) are disclosed. One exemplary embodiment is a circuit comprising a series connection of controllable switch components where at least one of the controllable switch components is an RC-IGBT. The circuit is operated by applying a pre-trigger pulse to the gate electrode of the RC-IGBT during reverse conduction of the RC-IGBT at a first time instant, the pre-trigger pulse corresponding to a turn-on gate pulse. Next, a turn-on gate pulse is applied at a second time instant to the other controllable switch component of the series connection for controlling the other controllable switch component to a conductive state such that the pre-trigger pulse and the turn-on gate pulse overlap, and ending the pre-trigger pulse after a delay time at the third time instant. The delay time is the time period when the turn-on gate pulse and the pre-trigger pulse overlap.

Abstract: An exemplary arrangement and method for a power semiconductor switch, where a first current between a first electrode and a second electrode can be controlled based on a control voltage between a third electrode and the first electrode. The arrangement includes an inductance connected in series with the power semiconductor switch, wherein a first end of the inductance is connected to the first electrode, first measuring source for generating a first measurement voltage based on the first end's voltage with respect to a reference potential, second measuring source for generating a second measurement voltage on the basis of the inductance's second end voltage with respect to the reference potential, a comparator for comparing the first measurement voltage with the second measurement voltage, and driver for generating the control voltage. The driver being configured to generate a first control voltage level and a second voltage level of the control voltage.

Abstract: A power converter driver that is supplied with two different voltages.

Abstract: A driving circuit for an IGBT module is provided. The driving circuit includes: a gate driving resistor connected with the IGBT module; a driving module connected with the gate driving resistor; an integrating circuit connected with the driving module, in which the integrating circuit comprises an equivalent resistor and a first capacitor connected in series with the equivalent resistor, and a time constant of the integrating circuit is adjusted by changing a resistance of the equivalent resistor; a first optical coupler connected with the integrating circuit; and a micro control unit, connected with the first optical coupler. The disclosed driving circuit for an IGBT module can adjust an equivalent resistance of the gate driving resistor, thus driving the IGBT module working at different powers without replacing the gate driving resistor, and improving an operation state of the IGBT module.

Abstract: One or more systems and techniques for managing one or more electronic devices are provided. A determination is made that a first capacitor in a set of one or more capacitors has a defect. Responsive to the determination, the first capacitor is disabled, and a second capacitor is enabled.

Abstract: Continuous-time linear equalization of received signals on multiple wire channels while maintaining accurate common mode signal values. Multiwire group signaling using vector signaling codes simultaneously transmits encoded values on multiple wires, requiring multiple receive signals to be sampled simultaneously to retrieve the full transmitted code word. By misaligning transitions on multiple wires, skew introduces a transient common mode signal component that is preserved by using frequency-selective common mode feedback at the receiver to obtain accurate sampling results.

Abstract: An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

Abstract: An output circuit includes a driver circuit and a node control circuit. The driver circuit includes a first transistor and a second transistor. The first transistor includes one end coupled to an external terminal and the other end coupled to a first node. The second transistor includes one end coupled to the first node and the other end coupled to a wiring that is supplied with a power supply voltage. When the first transistor and the second transistor are deactivated, the node control circuit supplies a node control signal based on a voltage of the external terminal to the first node.

Abstract: A switch control circuit that includes a control unit configured to generate a control signal; a switch driving unit configured to drive a switch element based on the control signal; and a slew rate adjusting unit configured to control the switch driving unit to change a slew rate of the switch element periodically in a predetermined change pattern.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.

Abstract: A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “?15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (?15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “?15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.

Abstract: In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A method for dealing with high inrush current when voltage is applied to mixed voltage logic integrated circuits is disclosed. A depletion N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or junction Field Effect Transistor (JFET) is added to a linear voltage regulator in mixed voltage logic integrated circuits. The Field Effect Transistor (FET) is utilized to allow the core voltage to come up with Input/Output voltage prior to turn-on of linear voltage regulator. Turn-on state of FET allows the core voltage to rise with Input/Output voltage until the FET threshold is reached across the gate. When threshold is reached, the FET turns off to allow linear voltage regulator turn on and take over supply power.

Abstract: Disclosed is a device for driving an inverter having a semiconductor switching element. A gate voltage calculating unit (20) calculates a surge voltage from the temperature, current, and DC-side voltage of each of IGBTs of the inverter and compares the surge voltage with the breakdown voltage of the element. The gate voltage calculating unit (20) commands a gate voltage control unit (22) to set a gate voltage higher than the normal value (reference value) in the case of judging that the difference between the element breakdown voltage and the surge voltage exceeds a predetermined threshold voltage and that a margin exists in the surge voltage. The voltage control unit (22) performs switching control of gates of the IGBTs according to the gate voltage command higher than the reference voltage to thereby reduce stationary losses of the IGBTs.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: A semiconductor device according to an exemplary embodiment of the present invention includes a discharge circuit and a control circuit. The discharge circuit includes a first transistor connected between a gate of an output transistor and an output terminal, and a capacitor connected to a gate of the first transistor, and discharges a gate voltage of the output transistor to the output terminal by turning on the first transistor with an electric charge of the capacitor. The control circuit includes a charge path, a first discharge path, and a second discharge path. The first discharge path discharges an electric charge of the charged capacitor when the system turns off. The second discharge path discharges the electric charge of the capacitor for a time period longer than a time period for discharging the output transistor by the discharge circuit upon detection of an abnormality in the system.

Abstract: A solid state relay has independent charge pumps isolating each gate of a full bridge to achieve faster and proper gate turn on. The low side MOSFETs of the bridge are the current sensing device reducing loss and allowing a device controlled by the relay to achieve peak performance. Dynamic braking is achieved by the two low side MOSFETs being fully conducted and applying a load across the DC motor. Addition of a microprocessor to the device provides undervoltage sensing, current vs time readings, motor stall sensing, and motor temperature sensing. Motor temperature is detected by checking impedance of the motor at microsecond pulses to see if the motor is getting hot.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes an auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt; an auxiliary FET in parallel with the main switching FET; the auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a predetermined maximum rate of decrease the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain; the auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: A subject of the present invention is to reduce noise caused by ringing or the like while reducing turn-on power loss of the element and reverse recovery loss of the diode in a switching circuit of a power semiconductor element to which a SiC diode having small recovery current is connected in parallel. A means for solving the problem is to detect gate voltage and/or collector voltage of the power semiconductor switching element and change gate drive voltage in several stages based on the detected value.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract: Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS): correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors: capacitors (C2, C3) connected between the control terminals and the input terminal: diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially same threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

Abstract: The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affects a slew rate.

Abstract: As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance. A semiconductor device having a semiconductor switching element and a drive controlling means (1) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means (2) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means (1).

Abstract: An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry blanks out current spikes in the output current occurring on a leading pulse edge of at least one of a plurality of outputs of the digital pulse-width modulator.

Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.

Abstract: Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.

Abstract: An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

Abstract: The invention relates to a comprehensive control method for switch on and off processes of power semiconductor switches (S1–S4). In a switching phase A the collector current transient dic/dt is controlled in order to safeguard a controlled clear-off of the edge zones of a serial freewheeling diode (Ds). In a switching phase B the collector voltage gradient dvCE/dt is controlled in order to specifically switch the power semiconductor switch (S1–S4), thereby establishing a closed control loop by returning primary and optionally secondary condition variables (vc, dvc/dt, ic, dic/dt, iG, vG, diG/dt, dvG/dt) of the power semiconductor switch (S1–S4).

Abstract: A drive circuit for a power semiconductor device includes: a sampling signal generating circuit for detecting that an input control signal instructs OFF and outputting a sampling signal at the time instant of start of a Miller period of time of an IGBT; a gate voltage detecting circuit for detecting a Miller voltage of the IGBT at the timing when the sampling signal is inputted and outputting, when the Miller voltage is equal to or larger than a threshold, an over-current detection signal; and a gate voltage controlling circuit for controlling, in response to the over-current detection signal, a gate voltage of the IGBT in such a way that the IGBT is turned OFF at slower speed than in the normal state. Thus, it is possible to suppress a surge voltage which is generated when the IGBT is turned OFF during the flow of an over-current.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: A method and structure for providing dynamic control of a slew rate of an electronic circuit. The structure has a signal line that is coupled to a number of capacitive elements that may be selectively switched in or out of the electronic circuit in order to provide precise control of the slew rate of the electronic circuit. A control element switches the capacitive elements into the signal line so that the slew rate may be precisely controlled at one or more time instants. The method includes determining a desired slew rate of the electronic circuit. Based upon the desired value of the slew rate, one or more of the capacitive elements are switched into the signal line at one or more time instants without changing an output impedance of the electronic circuit.

Abstract: A method for reducing a magnitude of a rate of current change of an integrated circuit is provided. The method uses a plurality of transistors controlled by a finite state machine, such as a counter, to gradually reduce current sourced from a power supply. Further, the finite state machine is controlled by a micro-architectural stage that determines when the integrated circuit needs to be powered down.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d