Abstract: A short-circuit protection circuitry is adapted for a power transistor. The short-circuit protection circuitry includes a first diode, a first resistor, a voltage dividing circuit, a gate voltage generator, a pull-down circuit, and a control signal generator. The first diode is coupled to a drain of the power transistor. The first resistor is coupled between the first diode and the power transistor. The voltage dividing circuit is coupled between a gate and a source of the power transistor to generate a dividing voltage. The gate voltage generator provides a gate voltage to the gate of the power transistor according to a first driving signal and a second driving signal. The pull-down circuit pulls down the gate voltage according to a control signal. The control signal generator generates the control signal according to the first driving signal, a voltage on the anode of the first diode and the dividing voltage.

Abstract: An RF switch circuit is provided. The RF switch circuit may include a first switch disposed between a transmitting port and an antenna port and including a plurality of first transistors; a second switch disposed between the antenna port and a receiving port and including a plurality of second transistors; and a switch control circuit configured to generate control voltages to control the first transistors and the second transistors, generate a first Off voltage to turn off at least one first transistor among the plurality of first transistors and the plurality of second transistors in a transmitting mode, and generate a second Off voltage to turn off at least one second transistor among the plurality of first transistors and the plurality of second transistors in a receiving mode, wherein the second Off voltage may be higher than the first Off voltage.

Abstract: In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes an electronically variable capacitor (EVC) comprising discrete capacitors, each discrete capacitor having a corresponding switching circuit for switching in and out the discrete capacitor to alter a total capacitance of the EVC. Each switching circuit comprises at least one switching field-effect transistor (FET) operably coupled to the corresponding discrete capacitor to cause the switching in and out of the discrete capacitor. For each switching circuit, when the switching circuit is switched OFF to switch out the corresponding discrete capacitor, the at least one switching FET receives a bias voltage from a bias voltage source to reduce a capacitance variability of the at least one switching FET.

Abstract: A switching circuit includes a first input terminal, an output terminal, and a first circuit that switches between outputting and not outputting, to the output terminal, a first voltage that is inputted to the first input terminal. The first circuit includes a first transistor and a second transistor that are connected in series between the first input terminal and the output terminal and a first voltage-dividing circuit that divides the first voltage and supplies the first voltage thus divided to a common node between the first transistor and the second transistor.

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or fed back from the power transistor device; wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.

Abstract: The embodiments of the present application provide a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. Here, the shift register unit includes a first controlling sub-circuit, a first voltage dividing sub-circuit, a charging and discharging sub-circuit, and an outputting sub-circuit. Here, an output signal of the outputting sub-circuit is controlled by the charging and discharging sub-circuit. A first input signal and a second input signal input at a first input signal terminal Forward and a second input signal terminal Backward electrically coupled to the charging and discharging sub-circuit are pulse signals.

Abstract: One or more embodiments of a power circuit can comprise a capacitor in series between a power source and a gate of a transistor, to receive a driver output of a first voltage from the power source. The power circuit can further comprise a first diode in parallel between the power source and the gate of the transistor. In some embodiments, when the driver output is present and exceeds a first breakdown voltage of a second diode, and the second diode enables flow of current from the first cathode to the ground, resulting in the capacitor being negatively charged up to a second voltage corresponding to excess of the first voltage over the first breakdown voltage. In additional embodiments, after the capacitor is at least partially charged, when the driver output is not present, the capacitor discharges a negative current based on the negative charging of the capacitor up to the second voltage.

Abstract: A transistor circuit having a dummy capacitor or a dummy transistor between an input terminal and a transistor is disclosed. The circuit improves secondary nonlinear characteristics of the transistor attributable to one or more parasitic components and a clock signal. The transistor circuit includes an input terminal configured to receive an input signal, a transistor having a gate configured to receive a clock signal, and a source connected to the input terminal, a connection line between the input terminal and the transistor and having a parasitic resistor therein, a parasitic capacitor between the input terminal and the transistor, and a dummy transistor having a first terminal that is connected to the connection line between the input terminal and the transistor.

Abstract: According to an aspect of one or more exemplary embodiments, there is provided a constant on-time buck converter with calibrated ripple injection having improved light load transient response and reduced output capacitor size.

Abstract: A measurement system is described, comprising a sampling clock unit, a travelling wave sampler circuit and at least a first analog-to-digital converter and a second analog-to-digital converter. The sampling clock unit is configured to generate a sampling timing for the travelling wave sampler circuit. The travelling wave sampler circuit is configured to receive an input signal. The travelling wave sampler circuit is further configured to provide at least a first time-discrete intermediate signal and a second time-discrete intermediate signal and to sample the first and the second time-discrete intermediate signal with the same sampling timing. The first analog-to-digital converter and the second analog-to-digital converter are configured to receive the first time-discrete intermediate signal sampled and the second time-discrete intermediate signal sampled, respectively.

Abstract: A plug-and-play Transient Suppression Unit (TSU) for Voltage Regulator Modules (VRMs), which comprises a bi-directional current source connected via a high voltage port and a low voltage port of the TSU in parallel to a voltage output of the VRM, adapted to immediately sink or source current supplied to a load; a detection circuit for detecting mismatches between the voltage output of the VRM to a reference steady-state voltage, which comprises a first comparator for detecting a match between the voltage output of the VRM to the reference steady-state voltage; a second comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold higher than the reference steady-state voltage; a third comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold lower than the reference steady-state voltage value; a transient response accelerator, connected via a third port of the TSU to the output compensation port of the VRM error amplifier, and ada

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: A power circuit of an embodiment includes an amplifier circuit having a first and a second input. The amplifier circuit receives power from a power input and outputs an output voltage corresponding to a voltage difference between the first and second inputs. A reference voltage circuit supplies a reference voltage to the first input. A feedback circuit supplies a feedback voltage corresponding to the output voltage to the second input. A first ballast capacitance element is between the power input and the first input of the amplifier circuit.

Abstract: A power converter includes: a power converter main circuit that includes semiconductor switching elements; gate drive circuits driving the semiconductor switching elements, respectively; and one or a plurality of impedance element groups connected between at least one pair of the gate drive circuits. At least one of the gate drive circuits includes a detector that detects a voltage across the impedance element group, and changes the driving speed of the semiconductor switching elements in accordance with an output of the detector.

Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.

Abstract: Biasing architectures and methods for lower loss switches. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.

Abstract: A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.

Abstract: An electronic circuit arrangement, by which a line termination or terminating resistor of a serial bus, for example a CAN bus, is implemented in a switchable manner and can be electronically connected or disconnected by electronically operating switching elements and a microcontroller, or a computer port of the latter, which is present in an electronic control unit.

Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells includes a field-effect transistor having a drain terminal, a source terminal, a FET gate terminal, and a body terminal and an off-state linearization network. The off-state linearization network includes varactors coupled to the drain terminal and the source terminal of the field-effect transistor.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a switch architecture including a shunt termination path, for example to provide isolation between two terminals. More particularly, aspects of the present disclosure relate to methods for operating a shunt path to achieve various termination states. An exemplary method generally includes providing a first control signal to a plurality of transistors coupled in series between an electrical path and a termination transistor, wherein the termination transistor is coupled in series between the plurality of transistors and ground, providing a second control signal to the termination transistor, and dynamically controlling the first and second control signals to achieve a desired termination state for the electrical path.

Abstract: A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.

Abstract: Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.

Abstract: A current limit peak regulation circuit, a current limit circuit and a power converter including the current limit peak regulation circuit. The current limit peak regulation circuit provides a current limit threshold to limit a maximum allowable peak current value of a current flowing through a main switch of the power converter and adjusts the current limit threshold to decrease with decrease in a switching frequency of the power converter when the power converter is in a constant voltage mode so as to reduce power dissipation of the power converter in standby mode.

Abstract: There are disclosed a backlight source driving circuit and a display apparatus. The backlight source driving circuit comprises a switch field effect transistor (Q1), a freewheeling field effect transistor (Q2), a power supplying module, a control module, a LED group (Z) and a feedback module, the power supplying module is configured to supply power to the LED group (Z), the control module is configured to control turn-on timings of the switch field effect transistor (Q1) and the freewheeling field effect transistor (Q2) to be opposite, and the feedback module is configured to provide a feedback voltage to the control module. The backlight source driving circuit is disposed in the display apparatus. By utilizing the field effect transistor as the freewheeling device in the backlight source driving circuit, the power consumption of the driving circuit is decreased effectively and an efficiency of the driving circuit is enhanced.

Abstract: Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.

Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.

Abstract: A power conversion device includes a diode built-in transistor configured to include a transistor configured to be driven by a drive signal input into a gate, a diode configured to be connected in parallel with transistor, and have a forward direction from an emitter to a collector of the transistor, and sense diode configured to detect a current flowing in the diode, and have a cathode connected with the collector of the transistor; voltage generation part configured to generate, in a case where the diode does not conduct electricity, voltage between an anode of the diode and an anode of the sense diode, the voltage having a predetermined or greater difference with respect to a case where the diode conducts electricity; and determination part configured to determine whether the diode conducts electricity, based on the voltage between the anode of the diode and the anode of the sense diode.

Abstract: An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

Abstract: A gate driver circuit capable of quickly driving a semiconductor device without erroneous ignitions. It has a positive power supply for forward bias, a negative power supply for backward bias, a first bias circuit that outputs the positive- or negative-power-supply voltage according to gate driver signal S, a capacitor that is charged by the negative-power-supply voltage when the first bias circuit outputs the negative-power-supply voltage, and a second bias circuit that supplies the gate of the semiconductor device with the positive- or negative-power-supply voltage according to gate driver signal S. Only in an early stage of a transition period during which the semiconductor device is turned on, the second bias circuit supplies the gate of the semiconductor device, instead of the positive-power-supply voltage, with a voltage boosted by adding the charged voltage of the capacitor onto the positive-power-supply voltage outputted from the first bias circuit.

Abstract: A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that compares one of the differential data strobe signals to the other, output a high logic value when the one of the differential data strobe signals is higher than the other, and output a low logic value when the one is lower than the other; a second receiver that compares one of the differential data strobe signals to a strobe reference voltage, output a high logic value when the one of the differential data strobe signals is higher than the strobe reference voltage, and output a low logic value when the one of the differential data strobe signals is lower than the strobe reference voltage; and a determination circuit that outputs a logical OR of an output of the first receiver and an output of the second receiver.

Abstract: A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.

Abstract: The 11Less Green Technology are Noiseless Field Programmable Integrated Circuit FPIC, Curtainless Window, Bladeless Turbo Fan, Brakeless Vehicle, Sawless, Resistorless, Capless, Inductorless, Diodeless Random Number Generator, Xtaless Clock Generator, Clockless Switch Mode Power Supply. The Green Technology of the Current Regulator for Green Power & Noise of Green Chip and Smart Window Driver for Smart Window of Green House are the fundamental building blocks of the next century green technology industry. Zilinx' FPIC is the last Field Programmable Integrated Chip. For the Green Building Management System, the IGU of the Smart Window includes the transparent Solar Cell, ElectroChromic Window and Smart Fan to adjust the light, temperature and ventilation simultaneously.

Abstract: Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.

Abstract: A semiconductor device of the present invention is a semiconductor device applicable in a cooling system including an ECU functioning as a setting part that sets target temperature of a refrigerant used to cool the semiconductor device, and a sensor functioning as a detector that detects the temperature of the refrigerant as refrigerant's temperature. The semiconductor device generates variable heating loss. The semiconductor device includes a heating controller that controls the heating loss in the semiconductor device such that the target temperature and the refrigerant's temperature become the same.

Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.

Abstract: A gate driving device may include an inverter arm including a high-side switch and a low-side switch, a gate driving unit including a first gate driver that receives an instruction signal to command switching controlling of the inverter arm to output a switching control signal for the high-side switch and the low-side switch, and a second gate driver that receives the switching control signal for the high-side switch to be output to the high-side switch, and a balancing unit maintaining balance in voltage between the first gate driver and the second gate driver, according to the switching of the inverter arm based on the switching control signal for the high-side switch.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (FETs) defining an RF signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the RF signal therebetween, and a second state corresponding to the input and output ports being electrically isolated. The switching circuit includes a voltage distribution circuit configured to reduce voltage distribution variation across the switch, including one or more elements coupled to a selected body node of one or more FETs so as to reduce voltage distribution variation across the switch when the switch is in the first state and encountered by an RF signal at the input port.

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.

Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

Abstract: A shunt switch includes first switching elements provided in series between a first node and a second node. Second switching elements are provided in series between the nodes but not in series with the first switching elements. A distortion generation element connected in series with second switching elements generates a distortion which may be used for compensating for a signal distortion at the first node. A distortion changeover element is connected in parallel with the distortion generation element and is configured to have a conductance state that is opposite to the conductance state of the first switching elements, such that the changeover element is conducting when the first switching elements are in an non-conductive state and non-conducting when the first switching elements are in a conducting state.

Abstract: Embodiments of radio frequency (RF) switching circuitry are disclosed that include (at least) a first switch and a body switching network operably associated with the first switch. The first switch has a first control contact, a first switch contact and a first body contact. The body switching network includes a first switchable path and a second switchable path. The first switchable path is connected between the first body contact and the first control contact of the first switch. Additionally, the second switchable path is connected between the first body contact and the first switch contact. Accordingly, the first body contact is can be appropriately biased by the switchable paths without requiring a resistor network and thus there is less loading. This maintains the Q factor of the RF switching circuitry.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.