Signal Transmission Integrity Or Spurious Noise Override Patents (Class 327/379)
  • Patent number: 11069274
    Abstract: The embodiments of the present application provide a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. Here, the shift register unit includes a first controlling sub-circuit, a first voltage dividing sub-circuit, a charging and discharging sub-circuit, and an outputting sub-circuit. Here, an output signal of the outputting sub-circuit is controlled by the charging and discharging sub-circuit. A first input signal and a second input signal input at a first input signal terminal Forward and a second input signal terminal Backward electrically coupled to the charging and discharging sub-circuit are pulse signals.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: July 20, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhichong Wang, Seungwoo Han, Guangliang Shang, Haoliang Zheng, Lijun Yuan, Xing Yao, Mingfu Han
  • Patent number: 11063589
    Abstract: One or more embodiments of a power circuit can comprise a capacitor in series between a power source and a gate of a transistor, to receive a driver output of a first voltage from the power source. The power circuit can further comprise a first diode in parallel between the power source and the gate of the transistor. In some embodiments, when the driver output is present and exceeds a first breakdown voltage of a second diode, and the second diode enables flow of current from the first cathode to the ground, resulting in the capacitor being negatively charged up to a second voltage corresponding to excess of the first voltage over the first breakdown voltage. In additional embodiments, after the capacitor is at least partially charged, when the driver output is not present, the capacitor discharges a negative current based on the negative charging of the capacitor up to the second voltage.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 13, 2021
    Assignee: GAN FORCE CORPORATION
    Inventors: Loveday Haachitaba Mweene, Tushar Heramb Dhayagude
  • Patent number: 11038501
    Abstract: A transistor circuit having a dummy capacitor or a dummy transistor between an input terminal and a transistor is disclosed. The circuit improves secondary nonlinear characteristics of the transistor attributable to one or more parasitic components and a clock signal. The transistor circuit includes an input terminal configured to receive an input signal, a transistor having a gate configured to receive a clock signal, and a source connected to the input terminal, a connection line between the input terminal and the transistor and having a parasitic resistor therein, a parasitic capacitor between the input terminal and the transistor, and a dummy transistor having a first terminal that is connected to the connection line between the input terminal and the transistor.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 15, 2021
    Assignee: DB HiTek Co., Ltd.
    Inventor: Tae-Ho Hwang
  • Patent number: 10965215
    Abstract: According to an aspect of one or more exemplary embodiments, there is provided a constant on-time buck converter with calibrated ripple injection having improved light load transient response and reduced output capacitor size.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 30, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Surya Prakash Rao Talari, Venkata Murali Krushna Malla, Ioan Stoichita, Matthew Weng
  • Patent number: 10955441
    Abstract: A measurement system is described, comprising a sampling clock unit, a travelling wave sampler circuit and at least a first analog-to-digital converter and a second analog-to-digital converter. The sampling clock unit is configured to generate a sampling timing for the travelling wave sampler circuit. The travelling wave sampler circuit is configured to receive an input signal. The travelling wave sampler circuit is further configured to provide at least a first time-discrete intermediate signal and a second time-discrete intermediate signal and to sample the first and the second time-discrete intermediate signal with the same sampling timing. The first analog-to-digital converter and the second analog-to-digital converter are configured to receive the first time-discrete intermediate signal sampled and the second time-discrete intermediate signal sampled, respectively.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 23, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Oliver Landolt
  • Patent number: 10840808
    Abstract: A plug-and-play Transient Suppression Unit (TSU) for Voltage Regulator Modules (VRMs), which comprises a bi-directional current source connected via a high voltage port and a low voltage port of the TSU in parallel to a voltage output of the VRM, adapted to immediately sink or source current supplied to a load; a detection circuit for detecting mismatches between the voltage output of the VRM to a reference steady-state voltage, which comprises a first comparator for detecting a match between the voltage output of the VRM to the reference steady-state voltage; a second comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold higher than the reference steady-state voltage; a third comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold lower than the reference steady-state voltage value; a transient response accelerator, connected via a third port of the TSU to the output compensation port of the VRM error amplifier, and ada
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: November 17, 2020
    Assignee: B.G. NEGEV TECHNOLOGIES AND APPLICATIONS LTD., AT BEN-GURION UNIVERSITY
    Inventors: Mor Mordechai Peretz, Alon Cervera, Or Kirshenboim
  • Patent number: 10812068
    Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 20, 2020
    Assignee: pSemi Corporation
    Inventors: Mark L. Burgener, James S. Cable, Robert H. Benton
  • Patent number: 10812138
    Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick Ware, Carl Werner
  • Patent number: 10797694
    Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 6, 2020
    Assignee: pSemi Corporation
    Inventors: Mark L Burgener, James S. Cable, Robert H. Benton
  • Patent number: 10790820
    Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 29, 2020
    Assignee: pSemi Corporation
    Inventors: Mark L. Burgener, James S. Cable, Robert H. Benton
  • Patent number: 10770020
    Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Hoon Lee, Seung-Hwan Moon, Yong-Soon Lee, Young-Su Kim, Chang-Ho Lee, Whee-Won Lee, Jun-Yong Song, Yu-Han Bae
  • Patent number: 10727729
    Abstract: A power converter includes: a power converter main circuit that includes semiconductor switching elements; gate drive circuits driving the semiconductor switching elements, respectively; and one or a plurality of impedance element groups connected between at least one pair of the gate drive circuits. At least one of the gate drive circuits includes a detector that detects a voltage across the impedance element group, and changes the driving speed of the semiconductor switching elements in accordance with an output of the detector.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukio Nakashima, Takayoshi Miki
  • Patent number: 10725487
    Abstract: A power circuit of an embodiment includes an amplifier circuit having a first and a second input. The amplifier circuit receives power from a power input and outputs an output voltage corresponding to a voltage difference between the first and second inputs. A reference voltage circuit supplies a reference voltage to the first input. A feedback circuit supplies a feedback voltage corresponding to the output voltage to the second input. A first ballast capacitance element is between the power input and the first input of the amplifier circuit.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akio Ogura
  • Patent number: 10713333
    Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Farhana Sheikh, Ankit Sharma, Jaydeep Kulkarni
  • Patent number: 10693459
    Abstract: Biasing architectures and methods for lower loss switches. In some embodiments, a switching device can include a series arm having transistors implemented in a stack configuration between first and second nodes. The switching device can further include a shunt arm having transistors implemented in a stack configuration between the first node and a ground node. The switching device can further include a bias architecture having a series arm bias circuit and a shunt arm bias circuit. The series arm bias circuit can be configured to bias the transistors of the series arm and include a gate-gate resistor that couples each pair of neighboring transistors. The shunt arm bias circuit can be configured to bias the transistors of the shunt arm and include a gate-gate resistor that couples each pair of neighboring transistors.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: Guillaume Alexandre Blin
  • Patent number: 10516392
    Abstract: A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 24, 2019
    Assignee: NXP USA, INC.
    Inventor: Thierry Sicard
  • Patent number: 10333744
    Abstract: An electronic circuit arrangement, by which a line termination or terminating resistor of a serial bus, for example a CAN bus, is implemented in a switchable manner and can be electronically connected or disconnected by electronically operating switching elements and a microcontroller, or a computer port of the latter, which is present in an electronic control unit.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: June 25, 2019
    Assignee: KNORR-BREMSE SYSTEME FUER NUTZFAHRZEUGE GMBH
    Inventor: Wolfgang Gscheidle
  • Patent number: 10277222
    Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells includes a field-effect transistor having a drain terminal, a source terminal, a FET gate terminal, and a body terminal and an off-state linearization network. The off-state linearization network includes varactors coupled to the drain terminal and the source terminal of the field-effect transistor.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 30, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Baker Scott, Marcus Granger-Jones, Dirk Robert Walter Leipold
  • Patent number: 10256287
    Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 9, 2019
    Assignee: pSemi Corporation
    Inventors: Eric S. Shapiro, Matt Allison
  • Patent number: 10211830
    Abstract: Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a switch architecture including a shunt termination path, for example to provide isolation between two terminals. More particularly, aspects of the present disclosure relate to methods for operating a shunt path to achieve various termination states. An exemplary method generally includes providing a first control signal to a plurality of transistors coupled in series between an electrical path and a termination transistor, wherein the termination transistor is coupled in series between the plurality of transistors and ground, providing a second control signal to the termination transistor, and dynamically controlling the first and second control signals to achieve a desired termination state for the electrical path.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Nelles Brindle, Jingbo Wang, Pasi Tapani Tikka
  • Patent number: 10122356
    Abstract: A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 6, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yugo Kunishi, Yasuhiko Kuriyama, Yoshio Itagaki
  • Patent number: 10110271
    Abstract: Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 23, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Yuan Li, Edward F. Lawrence
  • Patent number: 9998022
    Abstract: A current limit peak regulation circuit, a current limit circuit and a power converter including the current limit peak regulation circuit. The current limit peak regulation circuit provides a current limit threshold to limit a maximum allowable peak current value of a current flowing through a main switch of the power converter and adjusts the current limit threshold to decrease with decrease in a switching frequency of the power converter when the power converter is in a constant voltage mode so as to reduce power dissipation of the power converter in standby mode.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 12, 2018
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Li Lian
  • Patent number: 9881589
    Abstract: There are disclosed a backlight source driving circuit and a display apparatus. The backlight source driving circuit comprises a switch field effect transistor (Q1), a freewheeling field effect transistor (Q2), a power supplying module, a control module, a LED group (Z) and a feedback module, the power supplying module is configured to supply power to the LED group (Z), the control module is configured to control turn-on timings of the switch field effect transistor (Q1) and the freewheeling field effect transistor (Q2) to be opposite, and the feedback module is configured to provide a feedback voltage to the control module. The backlight source driving circuit is disposed in the display apparatus. By utilizing the field effect transistor as the freewheeling device in the backlight source driving circuit, the power consumption of the driving circuit is decreased effectively and an efficiency of the driving circuit is enhanced.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 30, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Kailiang Zhang
  • Patent number: 9800238
    Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 24, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Ethan Prevost
  • Patent number: 9800285
    Abstract: Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 24, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yuan Li, Edward F. Lawrence
  • Patent number: 9793825
    Abstract: A power conversion device includes a diode built-in transistor configured to include a transistor configured to be driven by a drive signal input into a gate, a diode configured to be connected in parallel with transistor, and have a forward direction from an emitter to a collector of the transistor, and sense diode configured to detect a current flowing in the diode, and have a cathode connected with the collector of the transistor; voltage generation part configured to generate, in a case where the diode does not conduct electricity, voltage between an anode of the diode and an anode of the sense diode, the voltage having a predetermined or greater difference with respect to a case where the diode conducts electricity; and determination part configured to determine whether the diode conducts electricity, based on the voltage between the anode of the diode and the anode of the sense diode.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: October 17, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yosuke Osanai, Ayuki Koishi
  • Patent number: 9698813
    Abstract: An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: July 4, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chihhou Tsai, Ying-Zu Lin
  • Patent number: 9660511
    Abstract: A gate driver circuit capable of quickly driving a semiconductor device without erroneous ignitions. It has a positive power supply for forward bias, a negative power supply for backward bias, a first bias circuit that outputs the positive- or negative-power-supply voltage according to gate driver signal S, a capacitor that is charged by the negative-power-supply voltage when the first bias circuit outputs the negative-power-supply voltage, and a second bias circuit that supplies the gate of the semiconductor device with the positive- or negative-power-supply voltage according to gate driver signal S. Only in an early stage of a transition period during which the semiconductor device is turned on, the second bias circuit supplies the gate of the semiconductor device, instead of the positive-power-supply voltage, with a voltage boosted by adding the charged voltage of the capacitor onto the positive-power-supply voltage outputted from the first bias circuit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 23, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Atsushi Morimoto
  • Patent number: 9558798
    Abstract: A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that compares one of the differential data strobe signals to the other, output a high logic value when the one of the differential data strobe signals is higher than the other, and output a low logic value when the one is lower than the other; a second receiver that compares one of the differential data strobe signals to a strobe reference voltage, output a high logic value when the one of the differential data strobe signals is higher than the strobe reference voltage, and output a low logic value when the one of the differential data strobe signals is lower than the strobe reference voltage; and a determination circuit that outputs a logical OR of an output of the first receiver and an output of the second receiver.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 31, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Noriyuki Tokuhiro, Ryo Mizutani
  • Patent number: 9552893
    Abstract: A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: January 24, 2017
    Assignee: NXP USA, Inc.
    Inventor: Jerome Enjalbert
  • Patent number: 9520827
    Abstract: The 11Less Green Technology are Noiseless Field Programmable Integrated Circuit FPIC, Curtainless Window, Bladeless Turbo Fan, Brakeless Vehicle, Sawless, Resistorless, Capless, Inductorless, Diodeless Random Number Generator, Xtaless Clock Generator, Clockless Switch Mode Power Supply. The Green Technology of the Current Regulator for Green Power & Noise of Green Chip and Smart Window Driver for Smart Window of Green House are the fundamental building blocks of the next century green technology industry. Zilinx' FPIC is the last Field Programmable Integrated Chip. For the Green Building Management System, the IGU of the Smart Window includes the transparent Solar Cell, ElectroChromic Window and Smart Fan to adjust the light, temperature and ventilation simultaneously.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 13, 2016
    Assignee: Anlinx
    Inventor: Min Ming Tarng
  • Patent number: 9484888
    Abstract: Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Yong Yang, Zuoguo Wu
  • Patent number: 9283850
    Abstract: A semiconductor device of the present invention is a semiconductor device applicable in a cooling system including an ECU functioning as a setting part that sets target temperature of a refrigerant used to cool the semiconductor device, and a sensor functioning as a detector that detects the temperature of the refrigerant as refrigerant's temperature. The semiconductor device generates variable heating loss. The semiconductor device includes a heating controller that controls the heating loss in the semiconductor device such that the target temperature and the refrigerant's temperature become the same.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 15, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Miyamoto, Mitsunori Aiko
  • Patent number: 9100005
    Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: August 4, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Publication number: 20150145586
    Abstract: A gate driving device may include an inverter arm including a high-side switch and a low-side switch, a gate driving unit including a first gate driver that receives an instruction signal to command switching controlling of the inverter arm to output a switching control signal for the high-side switch and the low-side switch, and a second gate driver that receives the switching control signal for the high-side switch to be output to the high-side switch, and a balancing unit maintaining balance in voltage between the first gate driver and the second gate driver, according to the switching of the inverter arm based on the switching control signal for the high-side switch.
    Type: Application
    Filed: April 25, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Won Jin CHO
  • Patent number: 9013225
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (FETs) defining an RF signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the RF signal therebetween, and a second state corresponding to the input and output ports being electrically isolated. The switching circuit includes a voltage distribution circuit configured to reduce voltage distribution variation across the switch, including one or more elements coupled to a selected body node of one or more FETs so as to reduce voltage distribution variation across the switch when the switch is in the first state and encountered by an RF signal at the input port.
    Type: Grant
    Filed: July 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anuj Madan, Hanching Fuh, Fikret Altunkilic, Guillaume Alexandre Blin
  • Patent number: 8988116
    Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Tatsuya Onuki
  • Publication number: 20150070073
    Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.
    Type: Application
    Filed: April 17, 2013
    Publication date: March 12, 2015
    Applicant: The Silanna Group Pty Ltd
    Inventors: Vijay Yashodhan Moghe, Andrew Terry
  • Patent number: 8975947
    Abstract: A shunt switch includes first switching elements provided in series between a first node and a second node. Second switching elements are provided in series between the nodes but not in series with the first switching elements. A distortion generation element connected in series with second switching elements generates a distortion which may be used for compensating for a signal distortion at the first node. A distortion changeover element is connected in parallel with the distortion generation element and is configured to have a conductance state that is opposite to the conductance state of the first switching elements, such that the changeover element is conducting when the first switching elements are in an non-conductive state and non-conducting when the first switching elements are in a conducting state.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Publication number: 20150035582
    Abstract: Embodiments of radio frequency (RF) switching circuitry are disclosed that include (at least) a first switch and a body switching network operably associated with the first switch. The first switch has a first control contact, a first switch contact and a first body contact. The body switching network includes a first switchable path and a second switchable path. The first switchable path is connected between the first body contact and the first control contact of the first switch. Additionally, the second switchable path is connected between the first body contact and the first switch contact. Accordingly, the first body contact is can be appropriately biased by the switchable paths without requiring a resistor network and thus there is less loading. This maintains the Q factor of the RF switching circuitry.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 5, 2015
    Inventors: George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 8947126
    Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Barrenscheen, Laurent Beaurenaut
  • Publication number: 20150022256
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.
    Type: Application
    Filed: August 29, 2014
    Publication date: January 22, 2015
    Inventors: Steven Christopher SPRINKLE, Fikret ALTUNKILIC, Haki Cebi
  • Publication number: 20150008973
    Abstract: In a switching control circuit, a determiner determines whether there is one of a first type of abnormality and a second type of abnormality different therefrom in a target switching element and/or the switching control circuit. A controller controls a second switching element to close a low-impedance discharge path for discharging a control terminal of the target switching element when it is determined that there is the first type of abnormality, and disables closing of a high-impedance discharge path for discharging the control terminal while the low-impedance discharge path is closed by the second switching element. The controller controls a third switching element to close the high-impedance discharge path when it is determined that there is the second type of abnormality; and disables closing of the low-impedance discharge path while the high-impedance discharge path is closed by the third switching element.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 8, 2015
    Inventor: Junichi FUKUTA
  • Patent number: 8922267
    Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 30, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Carlo Peschke, Ernst Muellner
  • Patent number: 8917135
    Abstract: A circuit includes a diode circuit and a deactivation circuit. The diode circuit includes a first terminal, a second terminal, and a plurality of diodes coupled in parallel between the first terminal and the second terminal. The diode circuit is configured to be forward biased in an on-time and reverse biased in an off-time. The deactivation circuit is configured to switch a first group of the diodes into a deactivation state at a time instant before the end of the on-time, the first group of diodes including one or more but less than all of the diodes included in the diode circuit.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Patent number: 8901990
    Abstract: In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takahiro Yamashita
  • Patent number: 8901986
    Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Leonid Fleshel, Michael Priel
  • Publication number: 20140347118
    Abstract: An electronic switch contains an input terminal, and output terminal and at least one first switch element, which provides a voltage-dependent characteristic. In this context, the first switch element connects the input terminal to the output terminal in a selective manner. The electronic switch further comprises a compensation element, which provides a voltage-dependent characteristic. In this context, the compensation element is arranged in such a manner that it at least partially compensates the frequency-dependent characteristic of the switch element.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Rohde & Schwarz GmbH & Co. KG
    Inventor: Bernhard Richt
  • Patent number: 8884681
    Abstract: A gate driving device includes a gate driving unit, a first control unit, a second control unit and a switch unit. The first control unit includes an input terminal receiving a first output signal and a first clock input terminal receiving a first clock signal. The second control unit includes an input terminal receiving a second output signal and a first clock input terminal receiving a second clock signal. The switch unit, the first control unit and the second control unit are coupled to a carryout signal output node for generating a carryout signal at the carryout signal output node which indicates whether the gate driving unit is functioning correctly. The first output signal and the second output signal of the gate driving unit are respectively one signal generated by any two different stages of shift register in the gate driving unit.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 11, 2014
    Assignee: Innolux Corporation
    Inventor: Sheng-Feng Huang