Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.

Abstract: A load driving device capable of preventing thermal destruction even when a load short-circuit or an overcurrent occurs, thereby having improved reliability, is provided. A load driving device, in which a power switch element for driving a load and a circuit for controlling the power switch element according to a signal VIN supplied from the outside are formed on one chip, is provided with an OFF-time delaying circuit for delaying an OFF-time transition of a level of an input signal at which the power switch element makes the transition from an ON state to an OFF state, according to a result of detection of a current flowing through the load and the level of the input signal to the power switch element.

Abstract: In integrated circuits with internally generated supply voltages, during the run-up of the internal voltage generators, unintentionally high currents can arise through switching stages connected to the internal supply voltage. A control circuit provides for the initialization of the switching stages during power-up. The control circuit contains an inverter that, in signal terms, can be driven by a precharge signal and, on the supply voltage side, is connected to the internal supply voltage via respective transistors. During power-up, the transistors are switched off and then switched on. The precharge signal is forwarded to the switching stage via a further inverter.

Abstract: A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the source terminal. The protection circuit has a resistance variable between a first value and a second value according to the operating condition of the power device. In a first embodiment of the protection circuit, an ON-OFF switch made by means of a horizontal MOS transistor has a control terminal connected to the drain terminal of the power device. In a second embodiment of the protection circuit, the ON-OFF switch is replaced with a gradual-intervention switch made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal of the power device.

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract: An active resistance is controlled to modify a drive signal provided to a gated device such as an insulated gate bipolar transistor (IGBT). The active resistance is between an input lead that receives an input drive signal, such as from a conventional gate driver IC, and an output lead at which an output drive signal is provided to the device's gate. The active resistance is controlled in response to a feedback signal that includes information about the output drive signal, so that the output drive signal is a modified version of the input drive signal. To reduce di/dt and hence control EMI emission, the output drive signal can include turn-on and turn-off transitions where the input drive signal includes steps.

Abstract: An adjustable integrated circuit output driver circuit is described which has a push-pull output circuit comprised of a pullup and pulldown transistor. A series of parallel transistors are connected to both the pullup and pulldown transistors. The gates of the parallel transistors are selectively controlled to adjust the driver current connected to a data bus line. Adjustable slew rate control circuits are describe which are coupled ot the pullup and pulldown transistors. Slew rate control circuitry and output control circuitry is provided to selectively adjust the driver circuit either during manufacture or after installation on a data bus. An alternate open-drain adjustable output driver circuit is also described.

Abstract: A circuit is provided that has an output buffer connected to one of a plurality of output pads. A power source is connected to one of the plutrality of output pads. A first pair of capacitors is connected to the power source. A second pair of capacitors is connected to the first pair of capacitors and the power source. A first pair of signal sources are connected to the first pair of capacitors. A second pair of signal sources connected to the second pair of capacitors. The first pair of signal sources and the second pair of signal sources control discharge to the power source and recharge to the power source of the first pair of capacitors and the second pair of capacitors to cancel out noise caused by either a voltage or current switching transient. Also, a method is provided for sending data to an output buffer, determining data to be clocked the next cycle, and controlling a charge-pump circuit to compensate for a voltage transition from one of high-to-low and low-to-high.

Abstract: The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.

Abstract: A gate drive circuit of a voltage drive switching element, which is characterized by control of di/dt and dv/dt when an IGBT is switched by controlling increases in the switching time and loss of the IGBT, includes a drive means for amplifying a signal for controlling the switching operation of a voltage drive switching device including the IGBT, a means for detecting the gate voltage of the IGBT, a voltage decrease (increase) means for slowly decreasing (increasing) the output voltage when the drive means is turned on (off) in the course of time, and a voltage increase (decrease) means for slowly increasing (decreasing) the output voltage. By switching from the voltage decrease (increase) means to the voltage increase (decrease) means according to the detected value of the gate voltage of the IGBT, di/dt and dv/dt are controlled when the IGBT is turned on (off).

Abstract: A slew rate output circuit includes a switching device connected to an output terminal, a driver circuit connected to the switching device for driving the switching device, and a control circuit connected to the driver circuit for controlling the driver circuit in accordance with an input signal so that, in an initial time period after a change in level of the input signal, the average slew rate is higher than that in a subsequent time period.

Abstract: An active drive circuit for high power IGBTs provides optimized switching performance for both turn-on and turn-off by incorporating a three-stage action to improve performance characteristics. The gate drive circuit includes a semiconductor switch such as a MOSFET connected in series with a low resistance gate turn-on resistor between the supply line and the gate input line, and a parallel connected bipolar transistor. During the first and third stages of turn-on, the MOSFET switch is turned on to provide rapid charging of the gate, whereas during the second stage the bipolar transistor is turned on to provide a controlled level of current charging of the gate. Similarly, a switch such as an MOSFET is connected in series with a low resistance gate turn-off resistor between the turn-off supply voltage line and the gate input line, and a bipolar transistor is connected in parallel therewith across the supply line and the gate input line.

Abstract: A method and apparatus of an output buffer for controlling the ground bounce and power supply noise during output switching is provided. A CMOS output buffer comprises a P-channel output transistor, a N-channel output transistor and a predrive circuit. During output pull-down transition, the predrive circuit generates a first gate voltage on the pull-down N-channel output transistor for a predetermined time, and further generates a second voltage value which is smaller than the first voltage value, then returns to the first voltage value after the elapse of the predetermined time. The predrive circuit makes the pull-down N-channel output transistor stay in the saturation region longer than the uncontrolled scheme, the steep rising gate voltage on the N-channel output transistor can be avoided with a very little speed degradation but instead of better ground bounce improvement.

Abstract: Leading-edge blanking circuits blank the leading edge of a current sense signal generated by sensing circuitry sensing the current through a switching field-effect transistor. A current sensor is employed to sense the magnitude of gate current being provided to the gate of the switching transistor by a driver circuit. A comparator indicates whether the sensed magnitude of the gate current exceeds a predetermined threshold current. A blanking circuit component, such as a transistor connected to ground, is also used. In one blanking circuit, the blanking component forces the current sense signal to zero when the comparator indicates that the gate current of the switching transistor exceeds the threshold current, and otherwise allows the value of the current sense signal to be determined by the current-sensing circuitry. In another blanking circuit, a latch is interposed between the comparator and the blanking component. The latch generates a blanking control signal to control the blanking component.

Abstract: The switching di/dt and switching dv/dt of a MOS gate controlled ("MOS-gated") power device are controlled by respectively controlling the voltage and current waveforms. Open loop control of the turn-on of the MOS-gated device is provided by coupling a common terminal of a current generator circuit, which provides a current to the gate of the MOS device, to a first resistor for controlling the switching dv/dt. At the detection of a negative dv/dt, the common terminal of the current generator circuit is then coupled to a second resistor for controlling the switching di/dt. The first and second resistors are, in turn, coupled to the source terminal fo the MOS-gated device. An analogous operation provides turn-off control of the MOS-gated power device. Closed loop control is also provided by measuring the switching dv/dt and the switching di/dt which are then fed back to the circuit to control the current supplied to the gate of the MOS-gated device.

Abstract: An-on-chip decoupling capacitor system for an integrated circuit comprises parallel capacitive and fusible paths between power and ground. The capacitive path includes a field-effect-transistor based capacitor and another "capacitive-path" transistor in series with the capacitor. The fusible path includes an electromigratable fuse and a "fusible-path" transistor in series with the fuse. The capacitive-path transistor, which is controlled by the voltage at a "fusible-path" node between the fuse and the fusible-path transistor, is on during normal operation. The fusible-path transistor, which is controlled by the voltage at a "capacitive-path" node between the capacitor and the capacitive-path transistor, is off during normal operation. During normal operation, the capacitor provides local voltage regulation by sinking charge during voltage surges and supply charge during voltage drops.

Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: An adjustable integrated circuit output driver circuit is described which has a push-pull output circuit comprised of a pullup and pulldown transistor. A series of parallel transistors are connected to both the pullup and pulldown transistors. The gates of the parallel transistors are selectively controlled to adjust the driver current connected to a data bus line. Adjustable slew rate control circuits are described which are coupled to the pullup and pulldown transistors. Slew rate control circuitry and output control circuitry is provided to selectively adjust the driver circuit either during manufacture or after installation on a data bus. An alternate open-drain adjustable output driver circuit is also described.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: A method for the turn-on regulation of an IGBT and an apparatus for carrying out the method are specified. In contrast to the prior art, the gate current is used as controlled variable rather than the gate voltage. Said gate current acts on the gate electrode according to a desired-actual comparison of an actual voltage value present at the gate electrode and of a corresponding desired value. The regulation guides the load current on a predetermined trajectory during the switching operation. Nevertheless, no current detection is necessary on the load side. Instead, use is made of the fact that, during the turn-on of the MOSFETs in the IGBT, the behavior of the latter predominates. It can be shown that there is a quadratic relationship between the gate voltage and the load current as soon as the gate voltage is greater than the threshold voltage. This is true until the full load current flows.

Abstract: A clock line over-protection circuit (28) carried on an interface card (16) for interfacing synchronous clock line (20), power line (22), DC common line (24) and data line (26) between a host computer (12) and a plurality of data link modules (14) with a plurality of associated controlled devices (18) including a series resistor (52) interconnected between a clock disable switch (52) and a clock signal generating amplifier (48) and a current sensor circuit (64, FIG. 3) connected across the series resistor (50) to produce a current sensor signal on an output (62). The current sensor signal is integrated by an over-current protection circuit (58, FIG. 4) to produce an over-current detection signal that varies with the difference in the clock line current magnitude during clock signal phases of opposite polarity.

Abstract: The cutoff process of a collector current of an insulated gate transistor is divided into an emitter-to-collector voltage recovery period and a collector current cutoff period. During the emitter-to-collector voltage recovery period the resistance of a gate resistor of the transistor is reduced, and during the collector current cutoff period the resistance of the gate resistor is increased. With this arrangement, the cutoff time is shortened, thereby reducing switching loss and suppressing surge voltage.

Abstract: Decoupling capacitors are activated by high current impulses that occur due to electrical over stress or electrostatic discharge, which occurs when the chip is powered off with no additional control signal or feedback elements. The high current or high voltage impulse is used to activate a rise time network, which turns on an electric switch, enabling the capacitor network. The basic circuit can be modified to address the situation where a failed decoupling capacitor needs to be switched out. In this modification, there is in addition to the three basic elements listed above, a feedback element connected between the decoupling capacitor and the switch. This feedback element operates to turn the electronic switch off when the decoupling capacitor is leaky. A further modification of the basic invention allows the decoupling capacitor to be used as a decoupling transistor during chip operation and as a capacitor during electrostatic discharge (ESD) testing or an ESD event.

Abstract: A current slew rate limiter for limiting the rate at which current is applied to the base of an NPN output transistor. Current is applied to the output transistor base via a first output port of a current splitter. The current provided by the second output port of the current splitter is fed back to the input of the current splitter via an NPN current mirror and a PNP current mirror connected in series. A current limiting resistor is provided in at least one of the input and output circuits of the PNP current mirror to limit the maximum output current to the base of the NPN output transistor.

Abstract: A predriver circuit for current switching, di/dt, noise control for high current load devices is disclosed. Parallel weak pull up and pull down circuit paths are combined with strong pull up and pull down circuit paths, respectively, to provide control over the rate of change of current through the load during predetermined turn-on and turn-off time periods. Predriver control for both NMOS driver, current sink NMOS, and PMOS driver, current source PMOS, are demonstrated. The predriver circuit provides control of the rate of current switching through the load without excessive delay in fully turning on or off the load device.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: An electronic device comprises a circuit that is provided with incrementally modifiable power consumption control means. By applying a program signal to this control means the balance between speed and power consumption is optimized. A PLA circuit considerably benefits from this architecture.

Abstract: A level-shifting circuit (LS.sub.A) including a series arrangement of a load resistor (R.sub.A), a main current path of an input transistor and a bipolar series transistor (T3.sub.A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1.sub.A) is not conductive a large amount of charge accumulates in the series transistor (T3.sub.A), which is then in saturation. When the input transistor (T1.sub.A) is turned on the accumulated charge causes an overshoot in the current (I.sub.A) through the level-shifter which overshoot compensates for the slow response as a result of the parasitic capacitance (PC.sub.A) at the node (N.sub.A).

Abstract: A capacitance elimination circuit for eliminating known parasitic capacitance at a node in a circuit. The capacitance elimination circuit is particularly useful at a connection of multiple pass gates in a switch matrix of a programmable logic device (PLD). The capacitance elimination circuit includes a current measuring device including a measuring capacitor having a first end connected to the node having the known capacitance. A second end of the measuring capacitor is connected to a current supply mechanism which provides current to the node to replace current withdrawn by the parasitic capacitance. In one embodiment, the current supply mechanism includes a first current mirror made up of transistors having a first channel type, the first current mirror having one arm coupled to the second end of the measuring capacitor. Another arm of the first current mirror is connected to an arm of a second current mirror made up transistors having a second channel type.

Abstract: An output buffer is provided with a terminal, a first driver, a second driver and enable circuitry. The first driver is for driving the terminal to a voltage corresponding to a logic value of the output signal. The second driver is for driving the terminal to the same voltage as the first driver, when the output signal transitions in logic value. The enable circuitry responds to a transition in logic value of the output signal by, after a predetermined delay, enabling the second driver to drive the terminal. However, the enable circuitry only enables the second driver to drive the terminal for a predetermined time period.

Abstract: In an output buffer circuit for a semiconductor integrated circuit, the waveform of an input to the gate of each output transistor slowly changes not only when the transistor is turned on but also when it is turned off.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

Abstract: A circuit arrangement for limiting the current to be switched of an electrical load, with the power input of the electrical load being controlled by means of a Triac, said Triac being connected in series with the electrical load, with a Diac being connected to the gate terminal of the Triac, said Diac being connected in series with a resistor arrangement whose resistance value is variable for the purpose of controlling the Triac, said Triac being disconnectible from the power supply by means of a first switch, wherein a second switch is provided by means of which the series arrangement comprised of the resistor arrangement and the Diac is disconnectible from the power supply, and wherein, on turning the electrical load on, the first switch is closed first, while the second switch is closed with a time delay. Advantageously, on turning the electrical load off, the second switch is opened first, while opening of the first switch occurs with a time delay.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: In a semiconductor device, a first resistor is connected between the base and collector of a dummy bipolar transisitor, a second resistor is connected between the base and emitter of the dummy bipolar transistor, and a third resistor is connected to the collector of the dummy bipolar transistor. A first pad and a second pad are connected to the base and emitter, respectively, of the dummy bipolar transistor. A third pad is connected to the third resistor. A fourth pad is connected to the collector of the dummy bipolar transistor.

Abstract: An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.

Abstract: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

Abstract: A load current detection circuit restrains the generation of noise spikes with a minimum of circuitry when changing between current detection sensitivity ranges by providing a plurality of sensitivity resistors between the output of a voltage source, such as a negative feedback voltage amplifier, and a load. Sensitivity range changing is performed via switches that increase or decrease the number of sensitivity resistors between the voltage source and the load. When a current detection sensitivity change is commanded, a voltage difference across the sensitivity resistors is measured, and a control processor generates a control voltage for changing voltage difference gradually until the voltage difference is zero without changing the voltage across the load. The sensitivity range switching then occurs when no current flows through the sensitivity resistors so that no noise spikes are produced.

Abstract: A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line.

Abstract: An output stage of a CMOS comparator is designed to have a limited short circuit current, while maintaining maximum output voltage swing and a low quiescent current. The output stage includes a reference voltage generation circuit, which generates a gate voltage at the output transistor of limited range, so that the short circuit current of the output transistor is limited. In one embodiment, the reference voltage is generated by a plurality of serially connected diodes.

Abstract: An apparatus for suppressing voltage transients and detecting desaturation conditions in power transistor systems. A first transistor, usually a power transistor, has a first terminal, a second terminal, a drive terminal, and an avalanche breakdown voltage rating between the first mad second terminals. The cathode of a first diode is coupled to the first terminal of the first transistor. The first diode has a reverse breakdown voltage which is less than the avalanche breakdown voltage rating of the first transistor. The anode of a second diode is coupled to the anode of the first diode, and the cathode of the second diode is coupled to the drive terminal of the first transistor. Driver circuitry is also coupled to the drive terminal, and provides a drive signal to the first transistor. An RC network comprising a first resistor and a first capacitor is coupled to the driver circuitry. The base terminal of a second transistor is coupled to the driver circuitry by means of the RC network.

Abstract: In a circuit for hard driving a GTO, the conductor inductance (L1) and the internal inductance of the GTO (L2) form, together with a first capacitor (C1) situated in parallel via a switch (S), a series resonance circuit inside the gate circuit. In this connection, the chosen sizes of the first capacitor (C1) and of the first inductance (L1) are such that, if the first capacitor (C1) discharges via the two inductances (L1, L2), the gate current originating from the first capacitor (C1) exceeds half the value of a GTO anode current to be turned off within less than 5 .mu.s in the first quarter cycle of the series oscillatory circuit. Moreover, first means are provided which uncouple the first capacitor (C1) from the generation of the gate current after the first quarter cycle of the resonance circuit and allows the gate current to decay slowly in such a way that, at any time, it is greater than the tail current of the GTO.

Abstract: A GTL phased-output driver is provided which employs a pre-driver, a set of phasing elements or delay elements, and a set of output transistors. The pre-driver includes pull up devices, such as PMOS devices, and pull down devices, such as NMOS devices. The PMOS devices of the pre-driver are configured to route output transistor-triggering signals through the phasing elements in one direction whereas the NMOS devices are configured to route output transistor-releasing signals through the phasing devices in an opposite direction. Output transistors of differing sizes are employed. During a pull down operation, controlled by the PMOS pre-driver transistors, the output transistors are triggered sequentially in order from smallest to largest. During a pull up phase, controlled by the NMOS pre-driver transistors, the output transistors are released in a reverse order from largest to smallest. Hence, the largest transistor is triggered first during a pull down phase but is released last during a pull up phase.

Abstract: A CMOS output buffer circuit includes negative feedback means for significantly reducing voltage oscillation. The buffer circuit is comprised of a pull-up transistor (P1), a pull-down transistor (N1), a first reference voltage generator circuit (44), a second reference voltage generator circuit (54), a first negative feedback circuit (48), and a second negative feedback circuit (58). First and second negative feedback circuits are coupled between the internal power supply potential/ground potential nodes and the gates of the pull-up/pull-down driver transistors so as to reduce the rate of change of the transient charging/discharging currents, respectively.

Abstract: A fast turn-on electrical switch circuit includes a silicon controlled rectifier ("SCR") connected substantially in parallel with a MOS controlled thyristor ("MCT"). When the switch is turned on, the MCT turns on almost immediately and carries the circuit load during the spreading time of the SCR. The SCR subsequently carries the circuit load when it is turned fully on because it has a smaller forward drop, due in part to its larger area and/or higher carrier lifetime. The MCT and SCR may be gated simultaneously from the same or separate sources or the SCR may be gated with a portion of the current from the MCT. The switch may be integrated into a single semiconductor device with alternating MCT regions and SCR regions.

Abstract: In order to prevent a malfunction caused by an electrical noise and limit an excessive main current at a high speed while cutting off the same to a value close to zero, the main current is regulated by an IGBT (1) which is connected with a load. A part of this main current is shunted to another IGBT (2). The as-shunted current flows through a resistor (3), to be converted to a voltage across the resistor (3). When the main current is excessively increased by shorting of the load or the like, this voltage exceeds a prescribed value so that a transistor (5) and a thyristor (7) enter conducting states. Consequently, a voltage across a gate (G) and an emitter (E) of the IGBT (1) is so reduced as to cut off the main current. The transistor (5) prevents the main current from excessive increase since the same has a high speed of response, while the thyristor (7) cuts off the main current to zero since the same has lower resistance in conduction.

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage during a system's "dead" time. This is done with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial precharging with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

Abstract: An output buffer circuit for an integrated circuit comprising first and second NAND gates and first and second output drive transistors. The first NAND gate inputs a first input signal and a first control signal and the second NAND gate inputs a second input signal and the first control signal.