Abstract: An UVLO circuit according to an aspect of the present invention includes: a power-on reset (POR) circuit generating an output based on a first current that flows according to an increase of a power supply voltage and not operating in a normal state of the power supply voltage; and a logic operation unit generating a reset signal according to an output of the POR circuit and an output based on a result of comparison between a sense voltage that corresponds to the power supply voltage and a predetermined reference voltage.

Abstract: A compensation circuit configured for coupling to a voltage source and a reference circuit. The voltage source is configured for supplying a supply voltage to the compensation circuit and the reference circuit. The reference circuit includes a first circuit node and a reference output electrically coupled to the first circuit node for outputting a reference signal having a constant reference amplitude. The compensation circuit includes a transient converter for converting a first transient perturbation of the supply voltage into a first compensation electrical signal proportional to said first transient perturbation, and an adder coupled to the transient converter for adding the first compensation electrical signal to an electrical signal at the first circuit node with a first polarity opposite to a disturbance polarity of a disturbance of the electrical signal in response to the first transient perturbation.

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract: A gate driver is provided. The gate driver amplifies an input control signal to drive gates of high and low side transistors. A high side driving chip amplifies a high side control signal for controlling the high side transistor and outputs the amplified high side control signal to the gate of the high side transistor. A low side driving chip amplifies a low side control signal and outputs the amplified low side control signal to the gate of the low side transistor. An emitter terminal of the gate of the high side transistor is connected to a collector terminal of the low side transistor. The high side driving chip is separately prepared from the low side driving chip.

Abstract: The disclosed transistor switching methodology enables independent control of transistor turn-on delay and slew rate, including charging, during a pre-charge period, a transistor control input to a threshold voltage VT with a predetermined turn-on delay; and then charging, during a switch-on period, the transistor control input from VT to an operating point with a predetermined slew rate. This methodology is adaptable to load switching applications, for example, to control a high side/low side load switch such that, during the switch on period, the output voltage supplied to the load rises from zero volts to an operating load voltage with the predetermined slew rate. In one embodiment, I_delay and I_slew_rate currents are used to charge the transistor control input respectively during the pre-charge and switch-on periods.

Abstract: A method for controlling two electrically series-connected reverse-conductive (RC) IGBTs (RC-IBGT) of a half bridge is disclosed, wherein an operating DC voltage is applied across the series connection and one of the two series-connected reverse-conductive IGBTs operates in IGBT mode and another of the two series-connected reverse-conductive IGBTs operates in diode mode, and wherein each of the two reverse-conductive IGBTs has three switching states “+15V”, “0V”, “?15V”. The RC-IGBT T1 operated in diode mode does not go into the switching state (?15V) of highly charged carrier concentration, but instead into a state of medium charge carrier concentration associated with the switching state “0V”, and not into the switching state “?15V”, as is known from conventional methods. This reduces the reverse-recovery without adversely affecting the forward voltage.

Abstract: A circuit includes a delay circuit, a transition detector, a pre-driver circuit, and a controller. The delay circuit includes an input for receiving a signal and an output for providing a delayed version of the signal. The transition detector is coupled to the input of the delay circuit to detect a transition within the signal and to provide a look ahead signal to a detector output. The pre-driver circuit includes an input coupled to the output of the delay circuit, a control input, at least one signal output, and a plurality of a bias outputs. The controller is coupled to the detector output and to the control input of the pre-driver circuit and is configured to control bias signals on a plurality of bias outputs to selectively increase a driving strength of signals and biases applied to an output stage in response to the look ahead signal.

Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

Abstract: In an electronic device with a switching element, a control circuit controls the voltage at the control terminal of the switching element and drives the switching element, by controlling an ON-drive switching element and an OFF-drive switching element based on an inputted drive signal to the control circuit. The control circuit is configured to turn OFF a switching element using a switching circuit other than the OFF-drive switching element after an elapse of a predetermined period of time from a timing at which the drive signal switches from an ON instruction thereof to an OFF instruction thereof, the ON instruction giving an instruction to turn ON the switching element, the OFF instruction giving an instruction to turn OFF the switching element.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A control system includes a clock gating module and a clock comparison module. The clock gating module is configured to generate a gating signal based on an enable signal, a given period, and a base clock signal having a given frequency. The clock comparison module is configured to generate a gated clock signal based on the base clock signal and the gating signal.

Abstract: Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.

Abstract: Provided is a switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a driving section that provides the switch with the control voltage corresponding to a control signal supplied thereto; and a changing section that changes the control voltage output from the driving section, according to a designated switching time. The changing section may change power supplied as a power supply to the driving section, according to the designated switching time. The changing section may change the control voltage output from the driving section prior to switching of the switch.

Abstract: A power off circuit includes a switching unit, a detecting unit, a power management unit, a delay unit, and a control unit. The switching unit is connected to a power source. The detecting unit detects whether the switching unit is turned off and generates a detecting signal when detecting that the switching unit is turned off. The power management unit receives a supply voltage from the power source and provides an operating voltage to at least one functional module. The control unit signals the at least one functional module to be ready for being powered off according to the detecting signal. The delay unit generates a control signal after a predetermined time period from a time point when the switching unit is turned off, the power management unit stops providing the operating voltage to the at least one functional module according to the control signal.

Abstract: In an electronic device with a switching element, a control circuit controls the voltage at the control terminal of the switching element and drives the switching element, by controlling an ON-drive switching element and an OFF-drive switching element based on an inputted drive signal to the control circuit. The control circuit is configured to turn OFF a switching element using a switching circuit other than the OFF-drive switching element after an elapse of a predetermined period of time from a timing at which the drive signal switches from an ON instruction thereof to an OFF instruction thereof, the ON instruction giving an instruction to turn ON the switching element, the OFF instruction giving an instruction to turn OFF the switching element.

Abstract: An electronic device includes an optical module, a power source module powering the optical module, a processor, a controller, and a switch module. The processor generates and maintains a delay signal for a first predetermined time in response to determination that the power source module is powered on. The processor further generates a driving signal upon determination that the first predetermined time has elapsed. The controller generates and maintains a control signal for a second predetermined time in response to determination that the power source module is powered on. The switch module is turned on to establish an electrical connection between the power source module and the optical module according to the driving signal, and turned off to cut off the electrical connection according to the control signal.

Abstract: An input circuit includes an interface structured to output a logic signal from an alternating current signal of a pair of elongated conductors. A load is switchable to the elongated conductors. A processor outputs a control signal to switch the load to the elongated conductors asynchronously with respect to the alternating current signal for a first predetermined time, inputs the logic signal, determines if the input logic signal is active a plurality of times during the first predetermined time and responsively sets a first state of the alternating current signal, and, otherwise, sets an opposite second state of the alternating current signal, and delays for a second predetermined time, which is longer than the first predetermined time, for the opposite second state before repeating the output, and, otherwise, delays for a third predetermined time, which is longer than the second predetermined time, for the first state before repeating the output.

Abstract: A circuit for controlling time sequence of an electronic device, the circuit comprises a delay unit to receive a first control signal, a first switch unit connected to the delay unit to receive the first control signal after a rising edge of the first control signal, a second switch unit to promptly receive the first control signal in response to a falling edge of the first control signal, and a voltage output unit connected to the first and second switch units. The voltage output unit is selectively controlled by the first or the second switch unit to output a second or a third control signal to turn on or off the electronic device.

Abstract: An electronic device includes an optical module, a power source module powering the optical module, a processor, a controller, and a switch module. The processor generates and maintains a delay signal for a first predetermined time in response to determination that the power source module is powered on. The processor further generates a driving signal upon determination that the first predetermined time has elapsed. The controller generates and maintains a control signal for a second predetermined time in response to determination that the power source module is powered on. The switch module is turned on to establish an electrical connection between the power source module and the optical module according to the driving signal, and turned off to cut off the electrical connection according to the control signal.

Abstract: Provided is a power converter having a switching circuit wherein a surge voltage of a plurality of switching elements connected in series is suppressed and loss is not concentrated to a specific switching element. The switching circuit is provided with: a non-latching type switching element having two main terminals and one control terminal; a voltage detecting means which detects a voltage applied between the main terminals of the switching element; a control current supply for supplying the control terminal with a control signal corresponding to the voltage detected by the voltage detector; and a delay device for delaying the control signal.

Abstract: A motherboard testing apparatus for automatically turning on or off a motherboard includes a pulse signal generating circuit for outputting a pulse signal, a first control circuit for outputting a first control signal to an I/O controller on the motherboard according to the pulse signal, and a second control circuit. The first control circuit outputs a low level first control signal when it receives a low level pulse signal, the I/O controller turns the motherboard on when it receives the low level first control signal. The second control circuit outputs a second control signal to the first control circuit which controls the motherboard to turn on again when the first control circuit receives the low level pulse signal a next time.

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: A module for controlling power supply to a load in a product which includes a microchip, and an electromechanical switch and a proximity/touch sensor connected to the microchip, preferably to the same input. The switch is primarily used to activate or deactivate the load and the proximity/touch sensor to vary the effect of operating the switch, or to control additional functions such as the activation of a signal, typically a light signal, which helps to locate the product, particularly in the dark, and to vary the duration of an automatic time-out period at the end of which the load is deactivated.

Abstract: A computer having a CPU which operates with at least two operation modes, comprising: a mode signal output unit outputting an operation mode signal corresponding to the operation mode of the CPU; a CPU power supply supplying power having a voltage level corresponding to the operation mode signal outputted from the mode signal output unit to the CPU; and a control unit controlling the CPU power supply to decrease an equivalent series resistance value to power outputted from the CPU power supply for a predetermined period of time for delay from when switching the operation mode of the CPU has been sensed, based on the operation mode signal outputted from the mode signal output unit.

Abstract: A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided.

Abstract: A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a del

Abstract: A computer apparatus includes a switch, a signal generating part which generates a signal corresponding to a position of the switch, a system part which receives the generated signal and operates, and a controller to control the signal generating part so that the signal generated in the signal generating part can be prevented from being applied to the system part for a predetermined period of time, if the switch moves from a first position to a second position.

Abstract: A solid state switch that employs a controller driven input and MOSFET power switching devices is disclosed. The controller can test for a short-circuit on the load side of the MOSFET power switching devices before putting the switch in a sustained conductive state.

Abstract: A semiconductor integrated circuit includes an oscillation circuit outputting an oscillation signal, and a switch circuit switching whether the oscillation signal received from the oscillation circuit is to be output to the outside or not.

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Abstract: A self-power down circuit for a controller coupled to a battery to obtain power from the battery. The controller has a port, the state of which changes during powering up of the controller. The circuit includes a first switching device including a main current conducting path and a control terminal. The control terminal of the first switching device is coupled to the port for monitoring the state of the port. The circuit further includes a second switching device including a main current conducting path and a control terminal, and a switch. The port is coupled to the battery through the main current conducting path of the second switching device. The control terminal of the second switching device is coupled to the switch for actuation by actuation of the switch. The control terminal of the second switching device is also coupled to the main current conducting paths of the first and second switching devices through first and second voltage dropping elements, respectively.

Abstract: A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.

Abstract: When a MOS transistor is turned off, a forward current flows into a diode connected to the MOS transistor. When the MOS transistor is conducted, a reverse bias is applied to the diode. When the MOS transistor is turned on during the reverse recovery time of the diode, a short-circuit current flows into the MOS transistor, the diode, and a battery connected in series with the diode and the MOS transistor. In this case, an overcurrent flows through the wiring of the battery momentarily, and electromagnetic wave generates from the wiring. Accordingly, noise caused by the electromagnetic wave is generated in an antenna to a radio receiver. The drain current of the MOS transistor is gradually increased by a delay circuit, and the MOS transistor is shifted from a completely turned-off state to a completely turned-on state with a time period longer than a reverse recovery time of the diode. Consequently, no reverse current flows through the diode.

Abstract: An apparatus for driving a bus with low power consumption, capable of reducing power consumption by reducing the width of the change in the level of a bus driving voltage transmitted through the data bus and a method therefor are provided. In the apparatus for transmitting a first or second bus driving voltage corresponding to input data instead of the input data to a bus receiving apparatus through a data bus, a first voltage transmitter transmits the first bus driving voltage, which corresponds to input data having a high level, to the data bus in response to a first control signal. A second voltage transmitter transmits the second bus driving voltage, which has a level that is lower than the level of the first bus driving voltage by a first predetermined level and corresponds to a low level of the input data, to the data bus in response to the first control signal. A first control signal generator outputs the first control signal in response to the input data.

Abstract: An output circuit for outputting a voltage signal to a circuit working with a power supply of a voltage higher than that under which the output circuits works, having an advantage that the voltage signal quickly increases to the potential level of the power supply of the output circuit, an input circuit for receiving a voltage signal from a circuit working with a power supply of a voltage higher than that under which the output circuits works and for forwarding the voltage signal to a circuit working with a power supply of a voltage identical to that under which the input circuit works, having an advantage that the potential level of the forwarded signal is the voltage of the power supply of the input circuit and the an input/output circuit having the foregoing both advantages.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.

Abstract: An output circuit includes a first, second and third field effect transistors each having a channel of a first conductivity type. The first field effect transistor includes a gate connected to a first node, a first electrode connected to a first power supply and a second electrode connected to a second node. The second field effect transistor includes a gate connected to a third node, a first electrode connected to the second node, a second electrode connected to a fourth node and a substrate connected to a fifth node. The third field effect transistor includes a gate connected to a sixth node, a first electrode connected to the third node, a second electrode connected to the fourth node and a substrate connected to the fifth node. The output circuit further includes an inverter and a fourth field effect transistor having a channel of a second conductivity type which is opposite the first conductivity type.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: An electronic delay circuit (10) for use in a detonator (100) has a switching circuit (20) and a timer circuit (22). Switching circuit (20) controls the flow of a stored charge of electrical energy from a storage capacitor (12) to a bridge initiation element such as a semiconductor bridge (18) or a tungsten bridge. The timing of the release of this energy is controlled by timer circuit (22). Switching circuit (20) is an integrated, dielectrically isolated, bipolar CMOS (DI BiCMOS) circuit, whereas timer circuit (22) is a conventional CMOS circuit. The use of a DI BiCMOS switching circuit allows for greater efficiency of energy transfer from the storage capacitor (12) to the semiconductor bridge (18) than has previously been attained.

Abstract: A power applying circuit for an internal logic circuit includes a plurality of basic power applying units coupled to the internal logic circuit in parallel, each of the basic power applying units including a logic gate unit outputting a pulse in response to two input signals having a time interval with respect to each other, and a transmission gate coupled to the logic gate unit and receiving the pulse.

Abstract: By setting the substrate potential of a transistor of a driver means lower than the substrate potential of a transistor of a bias means in an intermediate potential generation circuit which supplies a cell plate potential of a memory cell and a precharge potential of a bit line, a flow of a through current in a transistor of the driver means is prevented. Therefore, reduction of a power consumption of the device during standby can be realized.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: A power short pulse generator for generating a pulse on a rising edge and falling edge of an input signal according to the present invention comprises an input node for receiving the input signal and an output node for supplying an output signal. A first pulldown circuit and a second pulldown circuit are connected in series between the output node and a first supply voltage potential, the first pulldown circuit and the second pulldown circuit each having an input. A third pulldown circuit and a fourth pulldown circuit are connected in series between the output node and the first supply voltage potential, the third pulldown circuit and the fourth pulldown circuit each having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.

Abstract: An integrated circuit has a plurality of circuit elements, each of which is equipped with a power saving device for conserving power. This offers design flexibility to more easily change the number of circuit elements in the integrated circuit. Each circuit element detects the input data with the aid of an input detector circuit. The input detector triggers a timer circuit to measure the time required for the circuit element to process the data. The timer circuit turns on an action flag at the start of the process, and turns off the action flag at the end of the process. When the action flag is on, a switch circuit provides either a clock signal or the power to a main circuit. This allows the main circuit to enter an activation mode. When the action flag is off, the switch circuit either provides a low-speed clock signal or suspends the supply of the clock signal or the power to the main circuit. This allows the main circuit to enter a sleep mode.

Abstract: The present invention relates to a fail-safe on-delay circuit which uses an an electronic circuit. An input signal higher than a power source potential is input to a PUT oscillating circuit and a pulse signal generated with a predetermined time constant, is once changed in a level conversion circuit to a level within a range of the power source potential, and then is phase inverted and a rising differential signal of the phase inverted signal is formed. The input signal to the PUT oscillation circuit is applied to one input terminal of a fail-safe two input window comparator, and the differential signal is input to the other input terminal, and self held. After a predetermined delay time an output of logic value 1 is generated from the window comparator. As a result a fail-safe on-delay circuit can be made wherein, in the event of a fault in the elements of the circuit the delay time is not shortened.

Abstract: In a driving circuit for generating driving signals for controlling and switching on and off a first output element employed in an output circuit for generating a high-level output signal and a second output element employed in the output circuit for generating a low-level output signal in a mutually complementary manner, the conductance of the driving circuit is controlled so that it increases gradually with the lapse of time. By sequentially controlling the conductance of the driving circuit for generating the driving signals, the rates of change of the driving signals can be controlled in a smooth and stable manner and output currents can thus be changed smoothly to result in high-speed operation of an output signal with a reduced amount of noise.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.