Abstract: A switching circuit for outputting input and output signals from a single terminal includes an I/O signal interface circuit for forming a current path in parallel with a switch when a voltage at both terminals of the switch changes from high state to low state and for opening the current path when receiving a delay signal. An I/O signal separator provides the delay signal of predetermined time width when forming the current path to the I/O signal interface circuit and for blocking the current path during the delay period. Repeated and consecutive striking of a singular switch is ignored since only the first strike is effective. In addition, a display connected to a previously pressed switch remains continuously lighted when an interval between two consecutive struck different switches is shorter than the delay period.

Abstract: An output device and method of operating it are disclosed. The output device includes a output control unit and an output buffer unit. The output control unit produces a data release (INR) signal after producing an output release (OR) signal, for example, by delaying the OR signal. The INR signal causes release of an output signal from a sense amplifier, resulting in a data signal. The output buffer includes n- and p-channel switching transistors and control units controlling their gates. In response to activation of the OR signal, the control units bring the voltage of the gates of the switching transistors to respectively slightly above and slightly below the threshold levels of their gates. In response to the data signal, the control units fully activate one of the switching transistors and deactivate the other of the switching transistors depending on the voltage level of the data signal. The speed with which the control units respond to the data signal is controlled.

Abstract: A transistor circuitry keeps its constituent transistors from being forward biased to prevent injection of large currents into the transistor substrates, and like problems. The transistor circuitry achieves this result with a control circuit which generates a substrate control voltage and switching transistors which are prevented from receiving a high constant current voltage from an input terminal until the substrate control voltage is raised up to and held at a desired voltage level.

Abstract: A power conserving integrated circuit is disclosed. The integrated circuit is coupled to its external power supply only in response to an external event. An initial power connection is made in response to the external event. An element on the integrated circuit detects the initial power connection. After detecting the initial power connection, a switch internal to the integrated circuit is closed so as to couple the power supply to the integrated circuit for a predetermined period of time sufficient for a function to be executed by the integrated circuit. Afterwards, the connection is terminated and is not re-initiated until another external event. Therefore, power is consumed only when necessary, thereby preserving the power source.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.