Abstract: A garage door status monitoring and control system for a jackshaft operator may include a control module comprising a programmable platform configured to: receive a change-door-status command to change a position of a door; in response to the change-door-status command, generate and communicate a light or sound command to a wireless controller; delay a period of time after communicating the light or sound command to the wireless controller; and only after the delay, generate a door command corresponding to said change-door-status command to change the position of the door.

Abstract: An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: A terminating resistor circuit of a USB port and an operation method thereof are provided. The terminating resistor circuit includes a terminating resistor, a terminating switch, and an energy storage control circuit. The terminating resistor and the terminating switch are connected in series between a configuration channel pin of the USB port and a first reference voltage, and the energy storage control circuit is coupled to a control end of the terminating switch. During a charging period in a configuration detection period, the energy storage control circuit stores charge from the configuration channel pin to obtain a stored electrical energy, and during a discharging period in the configuration detection period, the energy storage control circuit turns on the terminating switch by using the stored electrical energy.

Abstract: An analog-to-digital converter includes a low voltage power supply rail, a high voltage power supply rail, successive approximation circuit, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuitry is coupled to the low voltage power supply rail. The level shifter is coupled to the high voltage power supply rail and includes inputs coupled to first outputs of the successive approximation circuitry. The CDAC includes a first segment and a second segment. The first segment includes a first plurality of capacitors, and a first plurality of switches coupled to outputs of the level shifter. The second segment includes a second plurality of capacitors, and a second plurality of switches coupled to second outputs of the successive approximation circuitry.

Abstract: A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

Abstract: A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

Abstract: A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively.

Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Abstract: Provided is a power converter having a switching circuit wherein a surge voltage of a plurality of switching elements connected in series is suppressed and loss is not concentrated to a specific switching element. The switching circuit is provided with: a non-latching type switching element having two main terminals and one control terminal; a voltage detecting means which detects a voltage applied between the main terminals of the switching element; a control current supply for supplying the control terminal with a control signal corresponding to the voltage detected by the voltage detector; and a delay device for delaying the control signal.

Abstract: A multi-channel semiconductor device comprises a plurality of buffer groups each comprising at least one output buffer, a plurality of pad groups each comprising at least one output pad, and a channel switching portion that controls connection between the plurality of buffer groups and the plurality of pad groups. One of the pad groups outputs an output signal of one of the buffer groups in a first operation mode and sequentially outputs output signals of all of the buffer groups in a second operation mode.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: Four energization switching devices and positive/negative switching devices are controlled to form a path charging a positive capacitor; a path connecting a power supply with the positive capacitor in series and energizing an inductor to charge a control terminal of a target switching device; a path charging the control terminal using electromagnetism in the inductor; a path supplying circulating current to the power supply when potential of the control terminal becomes higher than voltage of the power supply; a path charging a negative capacitor; a path connecting the power supply with the negative capacitor in series and energizing the inductor to discharge the control terminal; a path discharging the control terminal using electromagnetism in the inductor; and a path supplying circulating current to the power supply when potential of the control terminal becomes lower than potential of a negative terminal of the power supply.

Abstract: A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods.

Abstract: The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal.

Abstract: Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).

Abstract: Systems, apparatus, and methods are provided for initializing a voltage bus. An exemplary system includes an input interface, a voltage bus, discharge circuitry coupled to the voltage bus, connection circuitry coupled between the voltage bus and the input interface, and a control module coupled to the connection circuitry and the discharge circuitry. The control module activates the discharge circuitry prior to activating the connection circuitry.

Abstract: The invention discloses a power gating for in-rush current mitigation. Firstly the circuit uses small power switch cells at first stage, such that those power switch cells run in saturation region. Secondly a delay unit delays a switch signal to control the dwell time of current to reduce the peak value of the current. Thirdly large power switch cells are used at the rest, such that those power switch cells operate in linear region.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current.

Abstract: An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current.

Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Abstract: A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable sequencer may use an EEPROM or other computer-readable medium to program itself with a particular image of the sequencing program. The programmable sequencer may be implemented by a Field Programmable Gate Array (FPGA).

Abstract: An exemplary circuit for turning on a motherboard comprises a first switch module comprising a first terminal arranged to receive a standby power and connected to a sixth terminal of a computer front panel header, a second terminal arranged to receive the standby power, and a control terminal; a timing circuit charged by a system power; and a second switch module comprising a first terminal connected to the control terminal of the first switch module via the timing circuit, a second terminal arranged to receive the standby power, and a control terminal arranged to receive the system power, wherein, when the system power is lost, the second switch module discharges the timing circuit for turning on the first switch module after a discharge time, and the motherboard is turned on when the first switch module is turned on to ground the sixth terminal of the computer front panel header.

Abstract: The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit.

Abstract: An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit.

Abstract: A control module includes a plurality of switching elements, a control chip, and an identification unit. The switching elements are connected to a power terminal through a corresponding resistor each, wherein the resistances of corresponding resistors or equivalent resistance of combination thereof are different. The switching elements generate an input current according to operating conditions thereof. The input current is sent to the control chip through an input/output terminal and is transformed to a digital value. The identification unit identifies the operating conditions of the switching elements according to a lookup table and the digital value, such that the control chip executes a corresponding logic operation.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A configurable logic block (“CLB”) in a programmable logic device (“PLD”), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a timing signal, such as an external clock signal, through the CLB to provide a selected delay. The timing signal is routed through selected fast or slow pins of look-up tables (“LUTs”) in the CLB. CLBs are widely available in the PLD, allowing many timing signals to be delayed, and can be configured to account for board-specific or component-specific delays.

Abstract: A solenoid control circuit that includes two switching networks that are selectively opened and closed in a current limit cycle to control the magnitude of the current flowing through the solenoid. The configuration of the switching networks is such that current flows through an energy dissipating resistor only when the solenoid is commanded off by the solenoid control circuit, and not during the current limit cycle. Thus, the energy dissipated by this resistor is reduced relative to other solenoid control circuits, making it more efficient, and reducing EMI emissions from the circuit while providing for a fast solenoid response.

Abstract: A mono-cycle generating circuit comprises a control circuit, a multiplexer, and a driver switch circuit. The control circuit generates sets of timing pulses. The multiplexer selects one of the sets of timing pulses. The driver switch circuit outputs a mono-cycle based upon the selected set of timing pulses. The driver switch circuit comprises complementary sets of switches, each complementary set of switches including complementary amplitude pull-up/pull-down functions such that the output mono-cycle is a full rail swing mono-cycle.

Abstract: A pair of C-shaped gate electrodes may define a pair of transistors and a pair of diodes for forming an input/output signal driver for electrostatic discharge protection. Because of the compact arrangement, silicon real estate may be conserved in silicon-on-insulator substrates.

Abstract: A delay locked loop having an adjustable capacitance stage is provided. The adjustable capacitance stage facilitates a selective post-silicon adjustment of capacitance amounts between a DLL loop filter capacitance and a power supply noise filter capacitance, thereby allowing a designer to reduce capacitance area space wastage and to obtain an optimal DLL performance level.

Abstract: A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may include a pull-up driver and a pull-down driver. In the pull-up driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state; In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.

Abstract: An output circuit of an integrated circuit device includes first and second MOS transistors including respective spaced apart pairs of source and drain regions in a substrate, arranged such that respective first and second channels of the first and second MOS transistors are laterally displaced with respect to one another. The output circuit further includes an isolation region in the substrate, disposed between the first and second MOS transistors. A first conductor connects the source region of the first MOS transistor to a power supply node. A second conductor connects the drain region of the first MOS transistor to the source region of the second MOS transistor. A third conductor connects the drain region of the second MOS transistor to an external signal pad of the integrated circuit device. The isolation region may comprise first and second insulation regions surrounding respective ones of the first and second MOS transistors, and a guard ring surrounding and separating the insulation regions.

Abstract: A switching circuit which facilitates electrically controlled actuation of a switching device, such as a relay, in a two-wire circuit where access may be gained only to an active conductor. The switching circuit (10) comprises an electrically actuatable switching device (19) which is arranged to be connected in series with a load in the form of a lamp (11) in a single phase ac circuit (18). A solid state second switching device (20) is connected in series with the first switching device (19). A first energy storage device (21) is connected across the first and second switching devices and arranged under controlled conditions to deliver actuating power to an actuating element (22) of the first switching device (19). Also, a second energy storage device (23) is connected across the second switching device (20) and is arranged to provide power for gating the second switching device.

Abstract: Ground bounce and power supply bounce are reduced in an output driver by utilizing a plurality of p-channel and n-channel driver transistors which are connected to an output pad, by insuring that the p-channel driver transistors are quickly and sequentially turned off before the n-channel transistors are slowly and sequentially turned on, and by insuring that the n-channel transistors are quickly and sequentially turned off before the p-channel transistors are slowly and sequentially turned on.

Abstract: An electronic device for controlling oscillation of an output voltage about a final value includes a semiconductor substrate, and at least one output stage on the semiconductor substrate. The at least one output stage includes at least one output transistor for providing an output voltage to an external load connected thereto. The output transistor includes a plurality of transistor legs connected in parallel and having different channel lengths. Each transistor leg is individually turned on and at different times for controlling oscillation of the output voltage about the final value.

Abstract: An output circuit for outputting a voltage signal to a circuit working with a power supply of a voltage higher than that under which the output circuits works, having an advantage that the voltage signal quickly increases to the potential level of the power supply of the output circuit, an input circuit for receiving a voltage signal from a circuit working with a power supply of a voltage higher than that under which the output circuits works and for forwarding the voltage signal to a circuit working with a power supply of a voltage identical to that under which the input circuit works, having an advantage that the potential level of the forwarded signal is the voltage of the power supply of the input circuit and the an input/output circuit having the foregoing both advantages.

Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.

Abstract: An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: A circuit for producing a stable CDAC reference voltage in a successive approximation analog-to-digital converter includes a circuit (27) producing an input reference voltage (VREFIN), and a buffer circuit (12) producing a stable reference voltage in response to the input reference voltage. The buffer circuit includes an amplifier (13) having a non-inverting input receiving the input reference voltage. A first buffer (13B) receives the output of the amplifier and produces output that is fed back to an inverting input of the amplifier. A second buffer (18) also receives the amplifier output. A first transistor switch (19) couples the output of the second buffer to a CDAC. A second transistor switch (29) couples the CDAC to ground. A third transistor switch (26) couples the first buffer to the CDAC. The first transistor switch (19) closes to cause an initial "coarse" charging of a first capacitance of the CDAC by the second buffer (18).

Abstract: Circuit techniques for allowing the sharing of the same output terminals between transmission line drivers that comply with differing protocols. By inserting isolation transistors at the outputs of line driver circuits, and in a preferred embodiment along the current loop of a current-output line driver circuit, the invention allows the sharing of output pins while meeting all the power on and power off requirements of different protocols.

Abstract: When turned on by an input CONTROL signal, a MOSFET transistor switch in accordance with the present invention connects a low impedance voltage source to a moderate to high impedance load. The switch includes a relatively large first MOSFET transistor (Q1), a smaller second MOSFET transistor (Q2), a resistor and a current source. Source terminals of transistors Q1 and Q2 are tied to the voltage source. The load is connected to the drain of Q1 while the current source is connected to the drain of the Q2 and also to the gates of both transistors Q1 and Q2. The resistor links the gates of transistors Q1 and Q2 to the voltage source. When the CONTROL signal is asserted, it turns on the current source, thereby quickly turning transistors Q1 and Q2 on to connect the voltage source to the load. When the control source is de-asserted, the current source turns off. Transistors Q1 and Q2 then turn off at a controlled rate in order to minimize current injection into the load.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.