Abstract: An integrated circuit in which Schmitt input circuits can be tested in a short time and a highly accurate test result can be obtained. The integrated circuit includes switches each passing outputs of Schmitt inverters with inputs connected to input-output ports to the inputs of tristate circuits with outputs connected to adjacent input-output ports. The outputs of the Schmitt inverters may be blocked by the switches from being passed to internal logical circuits. A switch passes the output of the Schmitt inverter to the adjacent tristate circuit during the test of the Schmitt inverter. Alternately, each half of the Schmitt inverters can be tested as predetermined control signals selectively control each switch and each tristate circuit.

Abstract: Circuits and method for isolating internal nodes of an integrated circuit from external signals applied to I/O terminals of the IC even under no-power conditions are disclosed. The invention senses the most positive voltage level (in case of a p-channel implementation) or the most negative voltage level (in case of an n-channel implementation) at two input or input/output (I/O) pads and uses that voltage to isolate the internal nodes of the integrated circuit from the pad, without requiring the circuit power supply for its operation.

Abstract: A functional circuit is formed in a chip. A selector circuit is provided, which connects monitor points to electrode pads for external connections for testing the monitor points of the functional circuit. A control circuit is provided for supplying to the selector circuit a control signal which determines whether or not the monitor point is to be connected to the electrode pad by the selector circuit. The control circuit includes a counter circuit having a plurality of cascade-connected flip-flops, a clock signal input terminal for supplying a clock signal to each of the flip-flops in sequence from the flip-flop at an end of the counter circuit, and a reset signal input terminal for supplying a reset signal.

Abstract: The invention relates to switching apparatus having a pair of input terminals (102, 104) and 2.sup.P pairs of output terminals (106a, 106b). The switch comprises p rows of switches K.sub.i,j with the ith row having 2.sup.i unit switches. It also comprises a control circuit (108) which enables the state of all the switches in a given row to be controlled together, thereby enabling the pair of input terminals to be connected to any pair of output terminals.

Abstract: A pipelined microprocessor is provided including a latch circuit wherein a first transmission gate is electrically coupled in series with a second transmission gate between an output line of a first pipeline stage and an input stage of a subsequent pipeline stage. The latch circuit is controlled by a single clock signal wherein a delay element is employed to simultaneously enable both transmission gates upon an edge of the clock signal. The length of time during which both transmission gates are enabled is determined by an electrical delay associated with the delay element. When both transmission gates are enabled, the input line is electrically coupled to the output line. A keeper circuit at the output of the second transmission gate retains a logical value at the output of the latch after the input line is decoupled from the output line.

Abstract: A high voltage switch in which an extended SCR is built in an insulated polysilicon layer for providing a single structure high voltage switch. The high voltage SCR is built by building unit SCRs comprising a cathode, a gate, an anode and a voltage sustaining area. The unit SCRs are built as horizontal linear devices. The unit SCRs can then be combined to form a large SCR by building each unit SCR so that the anode of one SCR is at least partially contiguous with the cathode of the next unit SCR.

Abstract: According to a first aspect of the invention, a power control switch comprises two solid state switching elements (14, 15) in parallel, the second switching element (15) having a higher resistance but faster turn-off time than the first element. In operation the switch is pulse width modulated and the first element is switched off after the second element to establish a guard period, the duration of which is controlled in dependence upon the duty cycle to provide efficient switching. According to a second aspect of the invention a power control switch comprises a switching element (14 or 15) controlled by a field programmable gate array (5) which is preferably programmed by an erasable programmable read only memory (EPROM), thereby providing a reconfigurable control means.

Abstract: A switching circuit for outputting input and output signals from a single terminal includes an I/O signal interface circuit for forming a current path in parallel with a switch when a voltage at both terminals of the switch changes from high state to low state and for opening the current path when receiving a delay signal. An I/O signal separator provides the delay signal of predetermined time width when forming the current path to the I/O signal interface circuit and for blocking the current path during the delay period. Repeated and consecutive striking of a singular switch is ignored since only the first strike is effective. In addition, a display connected to a previously pressed switch remains continuously lighted when an interval between two consecutive struck different switches is shorter than the delay period.

Abstract: A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.