Abstract: A device comprising a semiconductor substrate. The device also comprising a digital block defined on the substrate and having multiple electronic elements. The device also comprises first and second poly layers coupling to the multiple electronic elements, the first and second poly layers extending in parallel through the digital block in a first direction. The device further comprising a third poly layer coupled to the first poly layer and extending through a gap in the second poly layer in a second direction orthogonal to the first direction poly.

Abstract: The disclosed test circuit includes: an input terminal, a processing circuit, and an output terminal. The input terminal receives an input signal. The input signal includes a test command for indicating a test target circuit module and an address of the target circuit module. The processing circuit responds to the test command and the target. The address of the circuit module determines the test mode signal, the test mode signal carries the test type, the test mode signal is used to trigger the target circuit module to perform the test corresponding to the test type, and the output terminal sends the test mode signal to the target circuit module according to the address of the target circuit module. Thus, the test mode signal can be accurately transmitted to different circuit modules in the memory chip.

Abstract: A multiplexing circuit including an output terminal, a first type transistor, a second type transistor and an impedance circuit; the first type transistor is coupled to the output terminal, wherein a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the output terminal, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the output terminal, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.

Abstract: An overcurrent protection circuit and display drive device, comprising: when input current of a front end corresponding to a logic signal experiences overcurrent, preventing the input current of the front end experiencing overcurrent from being transmitted to a drive chip, thereby preventing damage to the drive chip.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.

Abstract: An array substrate comprising a plurality of pixel units and an external compensation circuit; wherein, for each pixel unit of the plurality of pixel units, the pixel unit comprises a detection switch device, and the pixel unit is connected to a corresponding input end of a multiplexer of the external compensation circuit through the detection switch device; the external compensation circuit is configured: to acquire first data in a case that the detection switch device is opened, the first data comprising noise data caused by a level jump of the multiplexer of the external compensation circuit; to acquire second data in a case that the detection switch device is closed, the second data comprising the noise data and electrical data of the pixel unit; and to obtain the electrical data according to the first data and the second data.

Abstract: A DC-side soft switching device for a converter includes a battery, a bus capacitor, a first relay switch, a first resistor, a second relay switch, a second resistor, and a third resistor. The first relay switch is arranged between an anode of the battery and the bus capacitor. The first resistor is electrically connected in parallel to the first relay switch. The second relay switch is arranged between a cathode of the battery and the bus capacitor. The second resistor is electrically connected in parallel to the second relay switch. The third resistor is electrically connected in parallel to the bus capacitor.

Abstract: The present invention concerns a method for controlling the temperature of a multi-die power module, a multi-die temperature control device. The multi-die temperature control: obtains a signal that is representative of the temperature of one die among the dies of the multi-die power module when the die is not conducting, obtains signals that are representative of a reference temperature that is dependent of the temperature of all the dies of the multi-die power module when the dies are not conducting, compares the signal that is representative of the temperature of one die to the signal that is representative of the reference temperature, reduces the duration of the conducting time of the die or reducing the duration of the conducting time of the other dies of the multi-die power module according to the comparison result.

Abstract: In accordance with a first aspect of the present disclosure, a power converter is disclosed, comprising: an input configured to receive an input voltage; an output configured to provide an output voltage; a power switching block coupled between the input and the output; a controller configured to control the power switching block, wherein the controller is configured to open and close switches comprised in the power switching block, wherein the controller is further configured to control a resistance of the power switching block. In accordance with a second aspect of the present disclosure, a corresponding method of operating a power converter is conceived.

Abstract: A hysteretic controller coupled to a first inductor and a second inductor, the first inductor is coupled to a secondary side of a transformer, the second inductor is coupled to the secondary side of the transformer and the hysteretic controller includes: a hysteretic comparator including a first input, a second input, and an output, the first input configured to receive a sensed current from the first inductor and the second inductor, the second input configured to receive a differential voltage representing a potential difference between an output voltage of a power converter and a reference voltage; a pulse sequencer coupled to the output of the hysteretic comparator; and a dead-time generation circuit configured to provide a first on-time signal to a first switch coupled to a primary side of the transformer and a second on-time signal to a second switch coupled to the secondary side of the transformer, the first and second on-time signals based on a pulse signal received from the pulse sequencer.

Abstract: A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N?1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N?1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.

Abstract: An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.

Abstract: A reciprocal quantum logic (RQL) phase-mode D flip-flop accepts a data input and a logical clock input. A D flip-flop with an enable input further accepts enable input and further requires that the enable be asserted high to allow the data input to change the output on the logical clock pulse. The flip-flop includes a storage loop and a comparator, each of which includes Josephson junctions (JJs). The storage loop stores the data input, provided as a positive or negative single flux quantum (SFQ) pulse, is stored in the storage loop as positive or negative state, respectively, effectively biasing a JJ shared between the storage loop and the comparator. The data input is captured to the output upon clocking (or enabled clocking), when a clock pulse causes the shared JJ to preferentially trigger over an escape JJ in the comparator, the shared JJ having been biased by storage loop current.

Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.

Abstract: An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.

Abstract: An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node.

Abstract: A field device for determining or monitoring a process variable in automation technology. The field device meets a safety standard, which is required in a predetermined safety-critical application, comprising: a sensor, which works according to a defined measuring principle; and a control/evaluation unit, which processes and evaluates measurement data delivered by the sensor along at least three redundant and/or diversely designed measurement channels, wherein a redundant analog electrical current interface is provided, via which an electrical current representing the process variable is settable in a two-wire line.

Abstract: A filtered electromagnetic coupler includes a main transmission line extending between an input port and an output port, and a coupled line section extending between a coupled port and an isolation port. The coupler is configured to couple signal power from the main transmission line to provide coupled signals at the coupled port, and a filter subsystem is connected to the coupled port to filter the coupled signals. The filter subsystem includes filters configured to pass or reject coupled signals by frequency, and the filter subsystem provides the filtered output signal to a measurement node.

Abstract: A circuit includes an evaluation node through which current flows from a voltage source node to a sensed switch when the sensed switch is closed. First and second control switches are disposed between the voltage source node and the evaluation node to switch between first and second current paths for the current. The current passes through the first control switch when flowing along the first current path. The second control switch is coupled to a control terminal of the first control switch to deactivate the first control switch and allow the current to flow through the second current path. Multiple passive circuit elements are configured to establish first and second current levels for the current. The passive circuit elements are disposed between the voltage source node and the evaluation node in a circuit arrangement in which no current path to ground is present when the sensed switch is open.

Abstract: A switching circuit a multiplexer includes an NMOS switch module and a PMOS switch module connected in parallel between an input and an output. A first control module powered from a first power supply voltage operates to reduce leakage currents of the NMOS switching module when in the non-conducting state. A second control module powered from a second power supply voltage operates to reduce leakage currents of the PMOS switching module when in the non-conducting state. A voltage selection circuit is configured to deliver a voltage as the second power supply voltage equal to the greater of the first power supply voltage and the voltages present at the input and at the output.

Abstract: A circuit includes an electronic switch with an isolated gate, a measuring device for determining a charge at the isolated gate, and an energy supply for providing charge to the isolated gate based on the charge determined by the measuring device.

Abstract: A circuitry is suggested, in particular a power switch, comprising a first electronic switch with an isolated gate; a second electronic switch with an isolated gate; a measuring device for determining a charge at the isolated gate of the first electronic switch and at the isolated gate of the second electronic switch; an energy supply for providing charge to the isolated gate of the first electronic switch and to the isolated gate of the second electronic switch based on the charge determined by the measuring device; a logic unit for activating either the first electronic switch, both or none of the electronic switches.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

Abstract: An apparatus relating generally to a current steering cell includes a first bleeder circuit, a second bleeder circuit, a steering circuit, and an output circuit. The first bleeder circuit and the second bleeder circuit are coupled to receive a first current-source bias voltage. The steering circuit is coupled to receive a second current-source bias voltage independent from the first current-source bias voltage.

Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.

Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.

Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract: A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: A multiplexer includes a filter channelizer having at least two output filters, each output filter being coupled with a respective hybrid coupler. The multiplexer channelizes an input radio frequency (RF) band of electromagnetic energy into a set of output ports. Each hybrid coupler includes an input port (port 1), two output ports and an isolated port (port 4). Each output filter is coupled to a first one of the two output ports of a respective hybrid coupler, a second one of the two output ports being connected to an open stub microstrip transmission line. The respective hybrid coupler is coupled in a daisy chain, by way of port 1 and port 4, with one or more of the input of the multiplexer, and at least one other hybrid coupler. Advantageously, each output channel may include no more than one filter and no more than one hybrid coupler.

Abstract: A driver circuit is used for driving a plurality of switch elements connected between a power supply terminal and a common terminal. Each switch element includes an anode connected to the power supply terminal, a cathode, and a gate. The cathode is connected to a common terminal. The gate controls electrical conduction between the anode and the cathode. The driver circuit includes a switch circuit connected between the power supply terminal and the common terminal, and a driver into which a drive current flows. The switch circuit is in parallel with the switch elements, and electrically connects or disconnects the power supply terminal and the common terminal in response to a control signal supplied thereto. A transmission line, having a specific characteristic impedance, is connected between the common terminal and the driver circuit.

Abstract: An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin.

Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.

Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit.

Abstract: A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator.

Abstract: An industrial field bus communication cable breaking apparatus includes a housing, a first electrical connector coupled to the housing and configured to be connected to a first field bus communication cable, a first plurality of contacts disposed in the first electrical connector, a second electrical connector coupled to the housing and configured to be connected to a second field bus communication cable, a second plurality of contacts disposed in the second electrical connector, a control input configured to receive a control signal, and a plurality of switches. Each of the plurality of switches has a first end coupled to a respective one of the first plurality of contacts and a second end coupled to a respective one of the second plurality of contacts. Each of the plurality of switches is configured to simultaneously open and close based on the control signal.

Abstract: An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.

Abstract: A multiplexer is provided. The multiplexer includes an output coupled to a complementary driving unit and a plurality of switch circuits. Each switch circuit includes a channel unit and two switches. The two switches respectively conduct two input signals to a channel end of the channel unit during different switch conduction periods, and the channel unit conducts the channel end to an output end during a channel conduction period. The switch conduction period of the first switch in the first switch circuit equals the switch conduction period of the second switch circuit, the switch conduction period of the second switch in the second switch circuit equals the switch conduction period of the first switch circuit, and the first and second switches are coupled to the same input signal.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.