Field-effect Transistor Patents (Class 327/404)
  • Patent number: 10770984
    Abstract: A drive circuit is connected to a gate terminal of an FET connected to a DC power supply to be transformed and controlled to be turned on or off, and applies a voltage to the gate terminal to turn on the FET, the FET including a drain terminal to which a current is input, a source terminal that outputs the current input from the drain terminal, and the gate terminal that controls the current flowing from the drain terminal to the source terminal. A reverse bias circuit includes a capacitor connected to the source terminal of the FET, and a coil having one end connected between the drive circuit and the gate terminal and the other end connected between the capacitor and the source terminal.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 8, 2020
    Assignee: YAZAKI CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 10560061
    Abstract: A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds. A semiconductor region that is separated from a body region of a pass field-effect transistor (FET), such as by an insulator, can be coupled to or driven to a voltage similar to the input voltage or other desired bias voltage (e.g., an operational amplifier output) to help reduce parasitic capacitance of the switch or T-gate. The switch or T-gate can help provide improved frequency bandwidth or frequency response. The switch can be useful in a programmable gain amplifier (PGA) or programmable gain instrumentation amplifier (PGIA) or other circuit in which excessive switch capacitance could degrade circuit performance.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Sandro Herrera, Alan K Jeffery
  • Patent number: 10483965
    Abstract: Examples of a semiconductor device includes a first switching element including a first gate, a first source connected to a common terminal via a first connection line, and a first drain, a second switching element including a second gate, a second source that is connected to the first source via a second connection line and connected to the common terminal via the first connection line and the second connection line, a first capacitor for connecting the first source and a high voltage side of a power supply, a first circuit element having first end connected between the high voltage side of the power supply and the first capacitor, and a second capacitor for connecting the second source and second end of the first circuit element.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Miyazaki
  • Patent number: 10200029
    Abstract: A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds, such as one or more switch control signal inputs or supply voltages. A semiconductor region that is separated from a body region of a pass field-effect transistor (FET) can be coupled to or driven to a voltage similar to the input voltage or other desired voltage to help reduce parasitic capacitance of the switch or T-gate. The switch or T-gate can have improved frequency bandwidth or frequency response. The switch can be useful in a programmable gain amplifier (PGA) or programmable gain instrumentation amplifier (PGIA) or other circuit in which excessive switch capacitance could degrade circuit performance.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Sandro Herrera, Alan K Jeffery
  • Patent number: 10187108
    Abstract: The present invention relates to a low loss antenna switch. The antenna switch comprises a plurality of switch module and a plurality of transmitting/receiving terminals, wherein one end of each switch module is connected to an antenna unit and the other end of each switch module is connected to each transmitting and receiving end respectively. Further, each switch module comprises a plurality of switch units in series, wherein the width of at least one switch unit is smaller than other switch units of each switch module. Thus, the parasitic capacitance of the off-stage switch modules can be reduced, and VSWR (Voltage Standing Wave Ratio) of the antenna switch also can be improved.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: January 22, 2019
    Assignee: Airoha Technology Corp.
    Inventors: Heng-Chih Lin, Chien-Kuang Lee, Ping-Han Ho
  • Patent number: 10145930
    Abstract: A method is provided for calibrating a multiport measurement system having a local oscillator and a respective receiver associated with each port. The method includes performing a relative calibration by vector calibrating ports of the multiport measurement system and generating relative error-correction terms for the ports. Further, the method includes performing an absolute calibration by calibrating an amplitude response of the receivers of the multiport measurement system, and removing a local oscillator unknown phase response using a single phase reference coupled to a vector calibrated port and transferring cross-frequency phase correction terms from this vector calibrated port to the receivers of the other vector calibrated ports.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 4, 2018
    Assignee: Keysight Technologies, Inc.
    Inventors: Loren C. Betts, Joel P. Dunsmore
  • Patent number: 10116300
    Abstract: A switching component, in particular a domestic-appliance switching component, includes a series circuit of at least two field effect transistors, and at least one driver circuit, which is associated with one of the at least two field effect transistors. The driver circuit has at least one switching element, which short circuits two control contacts of the field effect transistor in at least one operating state.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 30, 2018
    Assignee: BSH Hausgeräte GmbH
    Inventors: Pablo Jesus Hernandez Blasco, Sergio Llorente Gil, Oscar Lucia Gil, Arturo Mediano Heredia, Daniel Palacios Tomas, Hector Sarnago Andia
  • Patent number: 10103728
    Abstract: In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 16, 2018
    Assignee: Exar Corporation
    Inventors: Vinit Jayaraj, Pekka Ojala, John Tabler
  • Patent number: 10056895
    Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: August 21, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Marcus Granger-Jones, Christian Rye Iversen
  • Patent number: 9973833
    Abstract: Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer; send a second correction signal to the second row buffer; receive an indication that the first switch is closed; send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 15, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Michael C. St Germain, Kimo Tam, Mohammad Hassan Ghaed
  • Patent number: 9954215
    Abstract: The present disclosure relates battery with an integrated power management system and scalable cutoff component, the battery system including a battery housing with first and second voltage output terminals, a plurality of rechargeable battery cells within the battery housing and having first and second voltage terminals; a power management system for generating an external control signal and an internal control signal based upon monitored operating parameters of the plurality of rechargeable battery cells, said external control signal for controlling an external power source and/or an external load, said power management system forming an integral part of the battery system; and a cutoff switch circuit within the battery housing and for making and breaking a conductive path between the first voltage terminal of the plurality of battery cells and the first voltage output terminal of the battery housing in response the internal control signal from the battery management system.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 24, 2018
    Assignee: A123 Systems, LLC
    Inventor: Brian J. Pevear
  • Patent number: 9906010
    Abstract: A driving device is configured to drive a power semiconductor switch module based on a main control signal. The driving device includes a voltage-modulating unit and a driving module. When the voltage-modulating unit receives a protection signal, the voltage-modulating unit generates a turn-off pulse signal based on the protection signal. Moreover, the driving module is configured to turn off the power semiconductor switch module based on the turn-off pulse signal. Also disclosed herein is a driving method.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 27, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Tao Jiang, Li-Feng Qiao, Jian-Gang Huang, Yang-Yang Tao, Hong-Jian Gan
  • Patent number: 9787318
    Abstract: A signal control device includes: a terminal of an input signal; a capacitor between the terminal and a reference potential; a charge/discharge circuit having a switch for switching connection between the charge/discharge circuit and the capacitor; an AD conversion circuit digitally converting an analog voltage in the capacitor; a switch control circuit controlling the switch and an AD conversion timing; a control arithmetic operation device performing a control arithmetic operation using an AD conversion value; and a malfunction determination device determining a terminal malfunction when the AD conversion value is not within a range.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 10, 2017
    Assignee: DENSO CORPORATION
    Inventor: Masaya Taki
  • Patent number: 9602748
    Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 21, 2017
    Assignee: Sony Corporation
    Inventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
  • Patent number: 9595945
    Abstract: A switch control circuit includes a plurality of first voltage generation circuits that generate a plurality of second control signals by level-shifting a plurality of first control signals using a reference voltage. A plurality of cut-off circuits controlling whether or not to supply the reference voltage to a corresponding one of the plurality of first voltage generation circuits. A control circuit is configured to control the cut-off circuits in such a manner that the reference voltage supplied to at least one first voltage generation circuit is cut off to the other first voltage generation circuits after a state of the first control signal supplied to the at least one first generation circuit is changed. In some embodiments, the reference voltage to the other first generation circuits is cut-off for a predetermined time period.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yugo Kunishi, Toshifumi Ishimori, Toshiki Seshita
  • Patent number: 9356597
    Abstract: A bidirectional data exchange circuit (10) includes a buffer (16) having paired terminals (A1 . . . A8, B1 . . . B8), a transfer direction input (20), an input (42) for controlling the transfer direction, and a logic gate (50). In the logic gate (50), the output is connected to the transfer direction input (20), an input is connected to the input (42) for controlling the transfer direction, this input being further connected to a first reference potential (Vcc) through a resistor (52), and the other input is connected to a terminal (A1) of the buffer (16) and to the first reference potential (Vcc) through a resistor (54; 154), and the terminal (B1) of the buffer (16), matched with the terminal (A1) of the buffer to which is connected the other input of the logic gate (50) being connected to a second reference potential through a resistor (56).
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: May 31, 2016
    Assignee: THALES
    Inventors: Laurent Pubert, Jerome Pichet, Benjamin Grimonprez, Thierry Collange
  • Patent number: 9356591
    Abstract: A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 31, 2016
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Poupak Khodabandeh, Merrick Brownlee
  • Patent number: 9329669
    Abstract: A power gating circuit including a first chain buffer that generates a first sleep signal by buffering an input sleep signal, a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a first switch block including a plurality of first switch cells controlled according to the first sleep signal.
    Type: Grant
    Filed: November 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Han Jeon
  • Patent number: 9324396
    Abstract: A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a first driving signal. The driving unit may also be configured to apply a second voltage to the sense amplifier in response to a second driving signal. In addition, the driving unit may also be configured to apply a third voltage to the sense amplifier in response to a third driving signal. A switching unit may be configured to electrically couple a first node to a second node in response to a control signal. The first driving signal is output to the first node, and the second driving signal is output to the second node.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 26, 2016
    Assignee: SK hynix Inc.
    Inventor: Kyeong Pil Kang
  • Patent number: 9094008
    Abstract: A high voltage analog switch operable by a binary signal is implemented in a low voltage semiconductor process. The switch has three parallel circuit paths, with each path comprising at least three series connected transistors. Control signals are selectively applied to the control terminals of the transistors to control the switch and selectively turn on or turn off each of the three circuit paths depending on the input voltage range, so that the breakdown voltage of all of the transistors is never exceeded in any mode of operation.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: July 28, 2015
    Assignee: Alfred E. Mann Foundation For Scientific Research
    Inventor: Edward K. F. Lee
  • Patent number: 9013212
    Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Vinod Kumar
  • Patent number: 9000812
    Abstract: An apparatus relating generally to a current steering cell includes a first bleeder circuit, a second bleeder circuit, a steering circuit, and an output circuit. The first bleeder circuit and the second bleeder circuit are coupled to receive a first current-source bias voltage. The steering circuit is coupled to receive a second current-source bias voltage independent from the first current-source bias voltage.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: April 7, 2015
    Assignee: Xilinx, Inc.
    Inventors: Donnacha Lowney, Christophe Erdmann
  • Patent number: 8963613
    Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Manas Behera, Yanping Ding, Junxiong Deng
  • Patent number: 8896363
    Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Da Chen, Zhengwei Zhang, Wei Mao
  • Publication number: 20140340946
    Abstract: In one embodiment, a power switch driving circuit can include: (i) an upper switch having a first power terminal coupled to a voltage source, and a second power terminal coupled to a driving signal; (ii) a lower switch having a first power terminal coupled to the driving signal, and a second power terminal coupled to a first voltage level, where the first voltage level is higher than a first ground potential; (iii) an upper switch driving sub circuit configured to receive a control signal, and to drive the upper switch in response thereto; and (iii) a lower switch driving sub circuit configured to receive the control signal, and to drive the lower switch in response thereto, where the upper and lower switch driving sub circuits are coupled to a second ground potential.
    Type: Application
    Filed: August 6, 2014
    Publication date: November 20, 2014
    Inventors: Wei Chen, Xiaoru Xu
  • Patent number: 8874401
    Abstract: In a measuring device, the measured data of a data recording component (10) are transmitted to an evaluating component via an output device (12). Parameters of the measuring device are stored in a memory (18). For the purpose of parameterization, parameters from the evaluating component can be stored in the memory (18) over a data cable for transmitting the measured data. To this end, the output device (12) for this data cable (Z) is operated at high impedance.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 28, 2014
    Assignee: Sick Stegmann GmbH
    Inventors: Josef Siraky, Willibald Stobbe, Ralf Steinmann
  • Patent number: 8872570
    Abstract: A multiple power domain circuit includes a trigger circuit, a high threshold voltage circuit electrically connected to an output terminal of the trigger circuit, and a low threshold voltage circuit electrically connected to the output terminal of the trigger circuit and an output terminal of the high threshold voltage circuit. The low threshold voltage circuit comprises a pulse generator electrically connected to the output terminal of the trigger circuit, and an inverter electrically connected to an output terminal of the pulse generator, and the output terminal of the high threshold voltage circuit.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jui-Jen Wu
  • Patent number: 8847655
    Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Mu-Shan Lin
  • Patent number: 8836383
    Abstract: The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: September 16, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Wei-Lun Hsieh, Hung-Sung Chu, Chung-Hsien Tso
  • Patent number: 8836381
    Abstract: A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 16, 2014
    Assignee: MoSys, Inc.
    Inventors: Charles W. Boecker, Eric Groen
  • Patent number: 8829975
    Abstract: A method and corresponding circuits for operating a parallel DMOS switch that includes a pair of P-type DMOS devices connected in series with each other and in parallel with a pair of N-type DMOS devices connected in series with each other. The method and circuits involve turning the switch on by applying gate signals to the DMOS device pairs which are generated using at least one source voltage of a DMOS device pair. The switch is turned off by setting the gate signals equal to the respective source voltages of the DMOS device pairs.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: September 9, 2014
    Assignee: Analog Devices, Inc.
    Inventor: David Aherne
  • Publication number: 20140240028
    Abstract: The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Inventor: Jeng-Jye Shau
  • Patent number: 8816740
    Abstract: A buffer circuit includes a first inverter circuit that inverts an input signal, a second inverter circuit that inverts the output signal of the first inverter circuit, an impedance element connected between the first inverter circuit and the second inverter circuit, a first conductivity type switching element that increases a potential of the output node of the second inverter circuit when the input signal exceeds a first threshold voltage, and a second conductivity type switching element that decreases a potential of the output node of the second inverter circuit when the input signal is lower than a second threshold voltage.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Patent number: 8806229
    Abstract: An integrated circuit device may include a plurality of external connections, any one of the connections providing both a power voltage path for the integrated circuit (IC) as well as an information signal path for the IC. At least one switch may be coupled to provide a power supply voltage to one of the external connections.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 12, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • Patent number: 8723612
    Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiuqiang Xu, Jie Jin, Yizhong Zhang
  • Publication number: 20140111269
    Abstract: A through-silicon via self-routing circuit includes a plurality of through-silicon vias (TSVs) and a plurality of planar die. The plurality of planar die are connected by the plurality of TSVs. And each one of the plurality of planar die includes a built-in self-tester, a built-in self-routing switching network, and a core circuit. The built-in self-tester has a plurality of valid-bit leads and a plurality of through-silicon via leads to connect the plurality of TSVs. The built-in self-routing switching network is connected to the built-in self-tester, for selecting from the plurality of TSVs for conducting. The core circuit has a to plurality of I/O leads linked to the built-in self-routing switching network.
    Type: Application
    Filed: March 17, 2013
    Publication date: April 24, 2014
    Applicant: NATIONAL CHANGHUA UNIVERSITY OF EDUCATION
    Inventor: NATIONAL CHANGHUA UNIVERSITY OF EDUCATION
  • Patent number: 8704584
    Abstract: A driver device drives a load circuit by a common output signal from a first driver transistor and a second driver transistor. The driver device includes a first pre-driver unit that outputs a first driver control signal to the first driver transistor in response to the input signal; and a second pre-driver unit that outputs a second driver control signal to the second driver transistor in response to the input signal. The first pre-driver unit controls the first driver control signal in such a manner that the first driver control signal is rounded in the vicinity of a threshold of the first driver transistor and is sharply changed in a region exceeding the threshold.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoji Shimazaki, Naoya Shibayama
  • Publication number: 20140077863
    Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiki SESHITA
  • Publication number: 20140035655
    Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.
    Type: Application
    Filed: October 2, 2013
    Publication date: February 6, 2014
    Inventors: Boris RESHETNYAK, Dante E. Piccone, Victor Temple
  • Publication number: 20140035499
    Abstract: There are provided a driving apparatus having a current detection function and a motor driving apparatus having a current detection function that are capable of detecting current without a voltage drop by using a dummy transistor connected to a driving transistor in parallel. The driving apparatus includes: a driving unit including at least one transistor connected between a driving power terminal supplying driving power and a ground and switched according to a switching control signal to drive a preset device; and a detecting unit including at least one dummy transistor connected to the at least one transistor in parallel and switched together with the at least one transistor according to the switching control signal to detect current flowing in the at least one dummy transistor.
    Type: Application
    Filed: October 25, 2012
    Publication date: February 6, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Joo Yul KO
  • Publication number: 20140002172
    Abstract: A voltage generating circuit includes a first supply voltage node, a first switching device, a sub voltage generating circuit, and a second switching device. The first supply voltage node is configured to have a first supply voltage value, and is coupled with the first switching device. The sub voltage generating circuit is coupled in between the first switching device and the second switching device. The first switching circuit and the second switching circuit are configured to receive a control signal behaving based on the first supply voltage value and a second supply voltage value different from the first supply voltage value.
    Type: Application
    Filed: February 5, 2013
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Wen-Han WANG
  • Publication number: 20130335134
    Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 19, 2013
    Inventors: Takamitsu KANAZAWA, Satoru AKIYAMA
  • Patent number: 8582334
    Abstract: Disclosed is a semiconductor device which includes: a semiconductor element 200 including a first metal-insulator-semiconductor field-effect transistor 200a and a second metal-insulator-semiconductor field-effect transistor 200b which is connected in parallel with the first metal-insulator-semiconductor field-effect transistor; and a control section which controls the operation of the semiconductor element. The control section controls the semiconductor element so that in a forward direction mode, current flows in a forward direction through the first and second metal-insulator-semiconductor field-effect transistors but that in a reverse direction mode, current flows in the reverse direction through the first metal-insulator-semiconductor field-effect transistor but does not flow through the second metal-insulator-semiconductor field-effect transistor.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Masashi Hayashi, Masanori Ogawa
  • Patent number: 8575989
    Abstract: A switch is provided. The circuit includes a plurality of transistors configured to electrically isolate the input of the switch from the output of the switch. In one embodiment, for example, the plurality of transistors may be configured to provide at least one path between the input and the output of the switch, and to provide at least three layers of electrical isolation between the input and the output of the switch when the switch is open.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas A. Garrity, Chunhe Zhao
  • Publication number: 20130257513
    Abstract: In accordance with at least one embodiment, an improved voltage headroom self-biased receiver is provided. In accordance with at least one embodiment, tail current sources are biased so as to be cross-coupled with respect to each other. In accordance with at least one embodiment, startup control is provided to counter defect-induced current and to ensure the circuit can function properly even with large amounts of defect current. In accordance with at least one embodiment, a positive type (p type) channel metal oxide semiconductor (PMOS) tail current transistor is modulated by a negative type (n type) channel metal oxide semiconductor (NMOS) differential pair virtual negative supply voltage and a NMOS tail current transistor is modulated by a PMOS differential pair virtual positive supply voltage. The amplifier's output common mode is thus self correcting to p type to n type transistor strength differences.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Hector Sanchez
  • Patent number: 8547143
    Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 1, 2013
    Assignee: Yaskawa America, Inc.
    Inventors: Mahesh M. Swamy, Tsuneo Joe Kume
  • Patent number: 8547156
    Abstract: Apparatus and methods are disclosed related to using one or more field effect transistors as a resistor. One such apparatus can include a field effect transistor (FET), averaging resistors and a bidirectional current source. The averaging resistors can apply an average of a voltage at the source of the FET and a voltage at the drain of the FET to the gate of the field effect transistor. The bidirectional current source can turn the FET on and off. The FET can operate in the ohmic region when on. Such an apparatus can improve the linearity of the FET as a resistor, for example, at lower frequencies near or at direct current (DC). In some implementations, the apparatus can include one or more current sources to remove an offset introduced by the bidirectional current source at the source and/or the drain of the FET.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: October 1, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Omid Foroudi
  • Patent number: 8542055
    Abstract: A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 24, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Patent number: 8525582
    Abstract: A current-source circuit includes a plurality of input-side transistors; a plurality of output-side transistors current-mirror-coupled to the plurality of input-side transistors; an output terminal from which an output current is output; and a switching control circuit to switch the plurality of input-side transistors and activate at least one of the plurality of input-side transistors sequentially.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: September 3, 2013
    Assignee: Fujitsu Limited
    Inventor: Satoshi Matsubara
  • Publication number: 20130214844
    Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.
    Type: Application
    Filed: May 31, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiki SESHITA