Abstract: A driver circuit for high frequency transistor type switches, comprising two sections; a positive (+) drive and a negative (-) drive, both sections being supplied with a high frequency signal by a square wave oscillator source. The sections are connected in parallel to a control generated input drive signal. In the negative drive section, the input drive signal is first inverted before being processed. Each section contains precise circuits for routing a high frequency carrier signal, for increasing input drive signal power gain, for providing independent positive and negative slope control, for providing exceptionally high voltage and noise isolation to avoid transmission of harmful voltages or noise, and for delivering a positive or negative drive signal to the gate/emitter of an external transistor under drive. The invention is characterized by its high voltage and noise isolation, using few components and being small in size.

Abstract: A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32,MP33), a variable input current source (I.sub.CS), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit 212. The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).

Abstract: A binary relative delay line device having two delay lines, each of which delays, during a time interval, an input signal by a substantially equal amount of time. Each delay line requires a settling time before it is selected during a next time interval. A selection and delay determining circuit is coupled to the two delay lines to select one of them to provide an output signal. A clock is coupled to the selection and delay determining circuit to operate the selection and delay determining circuit at a lower frequency than the frequency of the input signal, the lower frequency being chosen so that any selected delay line has settled before it is selected.

Abstract: A combined voltage and current source for measurement systems including a single reference amplifier provided at the front end which receives a reference voltage for determining the level of the voltage or current source signal supplied at the output. CMOS switches or similar logic selects between current and voltage portions of the combined circuit. If the voltage function is selected, the reference amplifier controls a voltage regulator to maintain the output voltage approximately equal to the reference voltage applied at the input. If the current function is selected, the reference amplifier is configured as a voltage to current converter to establish a current through a precision resistor. A voltage follower circuit provides the current source signal referenced to a supply voltage for providing a positive current. In this manner, a single reference amplifier is used at the front end rather than two separate reference amplifiers provided in prior art.

Abstract: The integrated circuit includes at least one conductance (6) which is adjustable by a digital control signal (17) which encodes steps in value for quantizing an exact value to within a fixed relative accuracy .DELTA.p. The conductance (6) includes elementary conductances which each define a step in value such that each elementary conductance is dimensioned so that a single level in value of the conductance (6) corresponds to two successive levels of the value of the digital control signal (17). If the result from the first of the two levels of value of the digital control signal (17) is a value which is lower, or respectively higher, than the exact value, the corresponding elementary conductance is enabled, or respectively disabled. Accordingly, the adjusted total value of the conductance (6) is equal to the exact value to within the same relative accuracy .DELTA.p, without oscillating between two values straddling this exact value.

Abstract: An integrated circuit (IC) with metal-oxide semiconductor field effect transistor (MOSFET) circuitry and on-chip protection against oxide damage caused by plasma-induced electrical charges includes a MOSFET circuit for receiving and processing an input signal and a complementary MOSFET pass gate coupled to the input thereof for receiving and passing the input signal thereto. The complementary MOSFET pass gate includes complementary MOSFETs with control terminals, input terminals and output terminals, with the control terminals being connected for receiving the IC power supply voltage and ground potentials, the input terminals connected together for receiving the input signal and the output terminals connected together and to the input of the MOSFET circuit for passing the input signal thereto in response to the receiving of the IC power supply voltage and ground potentials.

Abstract: A delay circuit is mainly configured by a plurality of paths, each having a different amount of delay, and at least selector. The selector selects one of the paths on the basis of delay data in such a way that a desired amount of delay is obtained. When an input pulse signal is applied to the delay circuit, the input pulse signal is delivered to the paths, so that pulses respectively transmit through the paths with being delayed by different delay times. For this reason, the pulses should arrive the selector at different timings which are affected by manufacturing process of circuit elements, variation of temperature and deviation of power-supply voltage. The selector is designed to cope with a problem due to different arrival timings of the pulses.

Abstract: A power driving circuit of a thin film transistor liquid crystal display includes Darlington circuits for generating voltages corresponding to the gate driving voltages required in the displays. Analog switching circuits control the application of voltages used to form the Von and Voff driving waveforms, which have driving voltage levels generated from the Darlington circuits. The phasing of the driving waveforms is controlled by a phasing signal which is received by the analog switching circuits. The power driving circuit of the present invention consumes less power than conventional driving circuits.

Abstract: In a charge pumping circuit capable of setting a wide output voltage range, a current mirror circuit (4) is provided with a transistor (T5) having an emitter which is grounded through a resistance (R1) and a collector (base) which is connected to that of a transistor (T2), and a transistor (T6) having an emitter which is grounded through a resistance (R2), and a collector which is connected to an output terminal (3). The transistor (T2) has a base which receives an inverted down signal/DOWN, and an emitter which is connected to a constant current source (1). A current mirror circuit (5) is provided with a transistor (T7) having an emitter which is connected to a power source (VDD) through a resistance (R3) and a collector (base) which is connected to that of a transistor (T4), and a transistor (T8) having an emitter which is connected to the power source (VDD) through the resistance (R2) and a collector which is connected to the output terminal (3).

Abstract: An electronic switch having a reduced body effect includes first and second switch terminals. A first transistor of a first type has a control terminal, a first substrate coupled to a first voltage level, and first and second drive terminals respectively coupled to the first and second switch terminals. A second transistor of a second type has a control terminal, a second substrate, a first drive terminal coupled to the second substrate and to the first switch terminal, and a second drive terminal. A third transistor of the second type has a control terminal, a third substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the third substrate and to the second switch terminal. A fourth transistor of a first type has a control terminal, a fourth substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the fourth substrate and a first voltage level.

Abstract: According to a first aspect of the invention, a power control switch comprises two solid state switching elements (14, 15) in parallel, the second switching element (15) having a higher resistance but faster turn-off time than the first element. In operation the switch is pulse width modulated and the first element is switched off after the second element to establish a guard period, the duration of which is controlled in dependence upon the duty cycle to provide efficient switching. According to a second aspect of the invention a power control switch comprises a switching element (14 or 15) controlled by a field programmable gate array (5) which is preferably programmed by an erasable programmable read only memory (EPROM), thereby providing a reconfigurable control means.

Abstract: A current source gate drive circuit for simultaneous firing of a set of series or parallel thyristors is described. The circuit includes two current loops, each of which serves as a current transformer primary. Electrically insulating tubes enclose the current loops. Current transformer cores, around which are wound a certain number of secondary turns, surround the current loops, thus magnetically coupling the primary current of the current transformer to the secondary turns. Thyristor gate driver circuits are electrically coupled to the current transformer cores. Each of the thyristor gate driver circuits receives and rectifies ac current signals from the current loops and forms a current pulse train firing signal. Each thyristor gate driver circuit has a corresponding thyristor that is fired by the current pulse train firing signal. The thyristors operate at a high voltage, but are electrically isolated from the current loops by the insulating tubes.

Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor.

Abstract: According to the present invention, the delay associated with a logic stage external to a sense amplifier is eliminated by absorbing the logic state into the sense amplifier circuitry. The sense amplifier inputs are swapped based on a sense enable signal which may be a derivative signal of a Data In signal. The sense amplifier may sense continuously or it may be clocked. The sense enable circuitry may be applied to various types of sense amplifiers such as dynamic, current mirror, differential, cross coupled, and level shifting sense amplifiers.

Abstract: A signal switching circuit is provided to output signal switching between a first and a second input signal. The circuit includes a first analog switch transistor, a first switch transistor, a second analog switch transistor, a second switch transistor and a third switch transistor. The interference between the first input signal and the second input signal is reduced to a possible minimum through the invention.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: The contrasting requirements of low power consumption during operation and ability to function under drastic drops of the supply voltage at start-up of output power stages of an electric system of self-generation and recharge of a storage battery, are satisfied by an output power driving stage composed of a bipolar transistor and a field effect transistor, functionally connected in parallel to each other and having independent control terminals. A control signal is selectably switched either to the base of the bipolar output transistor or to the gate of the field effect output transistor, depending on the level of the supply voltage. A comparator comparing the voltage present on the supply node with a reference voltage controls a selection switch. The low threshold of the bipolar transistor ensures functioning at start-up, while the field effect transistor provides a low power consumption during normal running conditions.

Abstract: In a flag control circuit successively supplied with first and second input flag signals produced in relation to first and second results of calculations in an arithmetic and logic unit to produce a final output flag signal, the first input flag signal is latched by a primary flag signal latching circuit while the second input flag signal is latched by the secondary flag signal latching circuit. The first latched flag signal and the second latched flag signal are ANDed by an AND gate circuit to produce the final output flag signal.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A balanced driver circuit which essentially eliminates inductive noise without a power dissipation penalty is disclosed. The balanced driver circuit is similar to a conventional balanced driver circuit however the circuit is impedance matched at both ends and has resistors connected in series with the outputs of the emitter followers in the chip. The resistors are equal in value to a termination resistor less the output impedance of the emitter followers. The impedance between the pair of signal leads, referred to as the primary and secondary leads is equal to the sum of the termination resistors. The current traversing the secondary lead has the same amplitude, but the opposite sign as the current traversing the primary lead. Thus, there is negligible current return through the common ground leads.

Abstract: A switching circuit that includes two parallel connected switching transistors. A primary winding of a transformer is connected across the drain electrodes of each of the switching transistors and a secondary winding of the transition transformer is connected to the gate electrodes of the transistor. A capacitor is connected in series with the primary winding to isolate the primary winding from the switching circuit when in a steady state operation. The secondary winding shorts the commonly connected gate electrodes in the steady state condition. The differential in voltage between the drain electrodes is used to activate the primary winding of the transformer which induces a correction voltage in the secondary winding to cause the transistors to operate at the same rate.

Abstract: An apparatus for enabling an IC pin to function in a dual mode, which apparatus includes a first switch for coupling the IC pin to an input terminal when the IC pin operates in an input mode, and a charging circuit for sourcing current to the IC pin during a charging cycle of a timer mode. The inventive apparatus further includes a discharging circuit for sinking current from the IC pin during a discharging cycle of the timer mode. In one embodiment, the inventive apparatus further includes a comparator for generating an activation signal, the activation signal being activated when a potential at the IC pin equals or exceeds a predefined voltage in the timer mode. In another embodiment, the comparator is disabled during the input mode.

Abstract: A low noise charge-pump circuit with low power consumption and operating in a cyclic mode comprises two current sources connected in parallel, and a current mirror for transforming the current supplied by one of the current sources and coupling it to the output of the other current source. Each of the current sources essentially comprises a transistor controlled from the output (VB) of a reference voltage generator via a respective transistor switch. The reference voltage generator essentially comprises a third transistor similar to the two first-mentioned transistors and in series with a further current source supplying a current Io, and means for making the current through the third transistor equal to the current Io.

Abstract: An electric multiple-valued register for electrically maintaining a multiple-valued digital signal of a ternary value of (0, 1/2, 1), quaternary value of (0, 1/3, 2/3, 1) or quinternary value of (0, 1/4, 2/4, 3/4, 1) instead of a binary digital signal such that 1 digit is of 0 or 1 is realized by inserting an element having a stair shaped voltage-current characteristic into a coupling circuit of a conventional flip-flop circuit. It may be used for a quantization circuit with the aid of a step characteristic, a multivalued memory, a multivalued register, a multivalued loop memory, a multivalued pattern matching circuit, a voice recognition divide, pattern recognition device, or a associative memory device.

Abstract: The apparatus includes first, second and third connectors, a control signal generator (5.11) and first and second switches (5.9, 5.10). The first and second connectors each have a signal input terminal, a signal output terminal and a control signal terminal. The third connector has a signal input terminal (5.7) and eventually a control signal terminal (5.8). The first and second switching means each have first (a), second (b) and third (c) terminals, the first terminal (a) of the first switches (5.9) being coupled to the signal output terminal (5.5) of the second connector, the second terminal (b) of the first switches (5.9) being coupled to the signal input terminal (5.1) of the first connector, the first terminal (a) of the second switching means (5.10) being coupled to the signal output terminal (5.2) of the first connector, the second terminal (b) of the second switching means (5.10) being coupled to the signal input terminal (5.4) of the second connector. The first and second switches (5.9, 5.

Abstract: In order to prevent a malfunction caused by an electrical noise and limit an excessive main current at a high speed while cutting off the same to a value close to zero, the main current is regulated by an IGBT (1) which is connected with a load. A part of this main current is shunted to another IGBT (2). The as-shunted current flows through a resistor (3), to be converted to a voltage across the resistor (3). When the main current is excessively increased by shorting of the load or the like, this voltage exceeds a prescribed value so that a transistor (5) and a thyristor (7) enter conducting states. Consequently, a voltage across a gate (G) and an emitter (E) of the IGBT (1) is so reduced as to cut off the main current. The transistor (5) prevents the main current from excessive increase since the same has a high speed of response, while the thyristor (7) cuts off the main current to zero since the same has lower resistance in conduction.

Abstract: A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.

Abstract: A programmable analog N.times.M switching network that includes a charge-coupled-device (CCD) multiplexer switch means having a plurality of N input leads. The input leads contain signals from typical devices such as video cassette recorders, televisions, video cameras, cable TV telephones or the like. The CCD multiplexer switch means also includes a plurality of M output leads that provide signals to other typical devices which also may be video cassette recorders, televisions, telephones, etc. A programmable read-only memory (PROM) clock generator provides signals to CCD gates in the CCD multiplexer switch means to enable the multiplexer switch means 10 to selectively connect the input signals and leads to the output leads. The programmable PROM is controlled by means of programming request means which may be a computer or an operator console.

Abstract: A wide-band sample and hold circuit comprising an input buffer for inputting an analog input signal and buffering the inputted analog input signal, 1/2 frequency divider for frequency-dividing a sample and hold clock signal by two and outputting a 1/2 frequency clock signal, first switching circuit for switching in turn an output signal from said input buffer to sample and hold condensers in accordance with the 1/2 frequency clock signal, second switching circuit for switching selectivel sample and hold signals from the sample and hold condensers in accordance with said 1/2 frequency clock signal and transferring or block the selectively switched sample and hold signals in accordance with an inverted sample and hold clock signal, and an output buffer for buffering an output signal from said second switching circuit and outputting the buffered signal as an output signal of the sample and hold circuit.

Abstract: A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.