Abstract: A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.

Abstract: A circuit for multiplexing a selected one of a plurality of input signals to an output conductor includes a plurality of diamond follower input buffers each having an input terminal coupled to receive an input signal, respectively. A diamond follower output buffer has an output coupled to the output conductor. A feedback resistor is coupled between the output conductor and the outputs of the input buffers. A first current mirror has a control input coupled to a first current bias terminal of each input buffer, and a second current error has a control input coupled to a second current bias terminal of each input buffer. The first and second current mirrors have outputs connected to drive the input of the output buffer and bias current terminals of the output buffer to provide a high slew rate.

Abstract: A complementary multiplexer with low disabled output capacitance and method in which a plurality of switched buffers are packaged together to avoid the capacitance of a plurality of switched buffers applied to the printed-circuit board transmission lines.

Abstract: A circuit for generating an output signal used for driving a grounded load is provided. The circuit provides an output signal without glitches or spikes. The circuit also outputs a drive signal with enhanced responsiveness in transitioning from one output value level to another output value level. The circuit includes a plurality of control devices for providing respective output signals responsive to respective control signals. The base of a PNP transistor is coupled to the output of the control devices and acts as a buffer. The emitter of the PNP transistor is coupled to a voltage source and the collector is coupled to a grounded load for providing the drive current. Alternatively, an NPN transistor and current source provides the drive current to the grounded load. The circuitry may be used in an optical disk drive with the load and ground being a laser diode used for providing a laser beam in reading/writing an optical disk.