Converging With Plural Inputs And Single Output Patents (Class 327/407)
  • Patent number: 10436836
    Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-Su Kim
  • Patent number: 10411588
    Abstract: A power converter includes one or more first conversion circuits, one or more second conversion circuits, and a controller. The first conversion circuit is configured to use a trench type transistor. The second conversion circuit is configured to use a planar type transistor. All the one or more first conversion circuits and all the one or more second conversion circuits are connected in parallel to each other or connected in series to each other. The controller stops all the one or more second conversion circuits and operates at least one of the one or more first conversion circuits while an output command value is lower than a predetermined output threshold value. The controller operates all the one or more first conversion circuits and operates at least one of the one or more second conversion circuits when the output command value exceeds the predetermined output threshold value.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 10, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroki Miyake
  • Patent number: 10411720
    Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: MAX-PLANCK-GESELLSCHAFT ZUR FÖRDERUNG DER WISSENSCHAFTEN E.V.
    Inventors: Christoph Lenzen, Matthias Függer, Attila Kinali, Stephan Friedrichs, Moti Medina
  • Patent number: 10374598
    Abstract: A power on reset circuit according to the present disclosure includes: a reference voltage generating circuit that generates a reference voltage, and also outputs, as a control voltage, a voltage at a node at which a voltage rise is slower than the reference voltage; a comparison voltage generating circuit that operates in response to the control voltage output from the reference voltage generating circuit, and outputs a comparison voltage depending on a power source voltage; and a comparison circuit that compares the comparison voltage output from the comparison voltage generating circuit to the reference voltage output from the reference voltage generating circuit, and outputs an operation signal while the comparison voltage exceeds the reference voltage.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 6, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kentaro Yasunaka
  • Patent number: 10355477
    Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 16, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Mohamed Elsayed, Matthew Powell, Nicholas M. Atkinson, Praveen Kallam
  • Patent number: 10340904
    Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventor: Yanjing Ke
  • Patent number: 10270459
    Abstract: The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 23, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Shuo Fan
  • Patent number: 10261932
    Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 16, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Warren S. Snyder, Monte Mar
  • Patent number: 10248604
    Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Warren S. Snyder, Monte Mar
  • Patent number: 10218332
    Abstract: A matching circuit provides broadband impedance matching of first and second devices for processing RF signals in a broadband frequency range, the first device being inherently capacitive. The matching circuit includes a shunt inductor that transforms impedance of the first device to matching impedance at a matching resonance frequency in a middle portion of the broadband frequency range, and a series resonance circuit that has a series resonance frequency approximately the same as the matching resonance frequency. The series resonance circuit includes an inductor and a capacitor connected in series to the first device, and further transforms the matching impedance of the first device and the shunt inductor to a design matching impedance corresponding to the broadband frequency range. One end of the shunt inductor is connected to the first device, between the series resonance circuit and the first device or to an opposite side of the first device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 26, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Martin Fritz, Hongya Xu, Usman Javaid, Jonathan Bamford
  • Patent number: 10205454
    Abstract: Apparatus for glitch-free switching between multiple asynchronous clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different, asynchronous clocks without causing erratic behavior.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: February 12, 2019
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Giuseppe A. Lapiana
  • Patent number: 10156593
    Abstract: Transistor arrays are disclosed herein. An example transistor array includes a first node for coupling the transistor array to a circuit. A first transistor and a second transistor are coupled to the first node. A gate controller is coupled to the gate of the first transistor and the gate of the second transistor and is for selectively turning on the first transistor and the second transistor. A current source is coupled to the first node and is active when the second transistor is off. Calibration circuitry measures the voltage of the first node when the current source is active.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 18, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert A. Neidorff
  • Patent number: 10158341
    Abstract: A filter device includes first, second and third filter circuits that are connected to a common terminal. The first filter circuit includes a first inductor that is closest to the common terminal along a first signal line and a first capacitance element that is connected in parallel with the first inductor, the second filter circuit includes a series arm resonator, which is a second acoustic resonator, that is closest to the common terminal along a second signal line, and the third filter circuit includes a third acoustic resonator that is closest to the common terminal along a third signal line.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Koji Nosaka
  • Patent number: 10146679
    Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Jose M. Rodriguez, Animesh Mishra, Naveen Doddapuneni
  • Patent number: 10088525
    Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 2, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Mudasir Shafat Kawoosa, Rajesh Kumar Mittal
  • Patent number: 10014876
    Abstract: System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 3, 2018
    Assignee: MACOM Connectivity Solutions, LLC
    Inventor: Nanda Govind Jayaraman
  • Patent number: 10007636
    Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 26, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Warren S. Snyder, Monte Mar
  • Patent number: 9970987
    Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
  • Patent number: 9972368
    Abstract: Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 15, 2018
    Assignee: Altera Corporation
    Inventors: Bee Yee Ng, Gaik Ming Chan, Ping-Chen Liu, Thien Le
  • Patent number: 9899988
    Abstract: A switch, an antenna tuner, and a radio frequency apparatus are provided. The switch includes: 2N successively serially connected transistors. In the 2N successively serially connected transistors, control ends of any two transistors with closest odd sequence numbers are coupled to each other through a first resistor, and control ends of any two transistors with closest even sequence numbers are coupled to each other through a second resistor; a control end of an n-th transistor is coupled to a first control signal in a switch control signal, and a control end of an (n+1)-th transistor is coupled to the first control signal, where n is an integer that is greater than or equal to 1 and is less than or equal to 2N?1, N is an integer greater than or equal to 2, and the first control signal is used to control turn-on or turn-off of the switch.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: February 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yongchang Yu, Tao Liu, Weinan Li
  • Patent number: 9893713
    Abstract: A wide bandwidth multiplexer (MUX) is provided that performs carrier aggregation. The MUX combines at least a first LC filter that acts as a low band filter, at least a first composite filter that acts as a middle band filter, and at least one other LC or composite filter that acts as a high band filter. The wide bandwidth MUX has low insertion loss and provides sufficient attenuation at adjacent edges of adjacent pass bands to prevent overlap between adjacent pass bands.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 13, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Andriy Yatsenko, Hongya Xu, Paul Bradley
  • Patent number: 9835660
    Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Soma, Akira Uemura, Kenji Amada
  • Patent number: 9825629
    Abstract: Apparatus comprises a switch feature configured to restrict an electrical signal transmitted from a peripheral device, and received through an electrical contact, from being transferred to one of first and second circuit modules coupled to the electrical contact, depending on the voltage amplitude of the electrical signal.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 21, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Zhen Cui, Zhigang Chen
  • Patent number: 9791873
    Abstract: A semiconductor integrated circuit device includes a PMOS output element having a source electrode connected to a power supply terminal and a drain electrode connected to an output voltage terminal from which an output voltage is supplied. A voltage dividing circuit has resistors for dividing the supplied output voltage to produce a divided voltage. A reference voltage circuit generates a reference voltage and has a memory element whose threshold voltage determines the reference voltage. The reference voltage circuit has a regulating input terminal connected to the memory element to change the threshold voltage of the memory element. An error amplifier is supplied with the divided voltage and the reference voltage to generate a voltage that is applied to a gate electrode of the PMOS output element. The voltage is amplified depending on a difference between the divided voltage and the reference voltage.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: October 17, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Shinjiro Kato
  • Patent number: 9762287
    Abstract: Multiplexers are described in which differential signals on the signal paths associated with unselected differential inputs are converted to common mode signals to reduce crosstalk between unselected signal paths and the multiplexer's active signal path.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 12, 2017
    Assignee: Pericom Semiconductor Corporation
    Inventors: Tony Yeung, Michael Y. Zhang
  • Patent number: 9755727
    Abstract: An interference-suppression circuit produces an interference-reduced signal from output signals of a plurality of redundant functional blocks. A first extreme-value determination unit determines the specific output signal that represents a first extreme value from the output signals of the functional blocks. A processing unit offsets the output signals of the plurality of functional blocks against one another in such a manner that the interference-reduced signal is determined. The processing unit omits from consideration the first extreme value in determining the interference-reduced signal.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 5, 2017
    Assignee: Tesat-Spacecom GmbH & Co. KG
    Inventor: Volker Lueck
  • Patent number: 9660846
    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Weiqi Ding, Mengchi Lui, Wilson Wong, Sergey Y. Shumarayev
  • Patent number: 9542354
    Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Clements, John F. Ewen, Giri N. K. Rangan, Shridha Tyagi, Arun R. Umamaheswaran
  • Patent number: 9517737
    Abstract: Electrical devices in a vehicle engine compartment are controlled from the vehicle passenger compartment over a serial data bus that extends between a relay controller located in the engine compartment and a body control module located in the passenger compartment and which receives commands from various passenger compartment devices. A serial data link passing through the firewall couples the body control module to the relay controller.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 13, 2016
    Assignee: Continental Automotive Systems, Inc.
    Inventors: Thomas Scott Schaffer, Randolph W. Scott, Scott James Lucy
  • Patent number: 9507742
    Abstract: In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 29, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Jun Zhu, Joseph Jun Cao, Sheng Lu
  • Patent number: 9462242
    Abstract: An external micro projector comprises a micro projector body. A magnetic block is disposed in the micro projector body. The magnetic block is used for magnetically adhering with a magnetic adhesion device in a smartphone. A Pogo Pin connector is disposed on the micro projector body. The Pogo Pin connector is used for being electrically connected to the smartphone.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 4, 2016
    Assignee: HUIZHOU TCL MOBILE COMMUNICATION CO., LTD.
    Inventors: Jinai Lin, Cheol Woo Park, Hongxia Leng
  • Patent number: 9390669
    Abstract: A display device according to an embodiment of the present invention includes: a pixel including a first subpixel and a second subpixel; a first signal line connected to the first subpixel and transmitting a first signal; a second signal line connected to the second subpixel and transmitting a second signal; a third signal line intersecting the first and the second signal lines, connected to at least one of the first and the second subpixels, and transmitting a third signal; and a fourth signal line intersecting the first and the second signal lines and transmitting a fourth signal, wherein the first subpixel and the second subpixel are supplied with data voltages having different magnitude, and the data voltages applied to the first and the second subpixels are originated from a single image information.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang-Soo Kim, Dong-Gyu Kim, Seung-Hwan Moon, Seung-Woo Lee, Seung-Soo Baek
  • Patent number: 9337660
    Abstract: Some of the embodiments of the present disclosure provide a system comprising a functional block; a plurality of power sources, each of the plurality of power sources being maintained at a corresponding voltage; and a switching module having a plurality of switches, the switching module configured to supply power from at least one of the plurality of power sources to the functional block, each of the plurality of switches being controlled by a corresponding switching signal having a voltage value that is one of (i) a ground voltage and (ii) a high max voltage, the high max voltage corresponding to a highest voltage among the voltages of the plurality of power sources. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 10, 2016
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Ido Bourstein
  • Patent number: 9320886
    Abstract: An implantable lead connector configured for long term implantation and to electrically interconnect multiple medical devices and to channel electrical signals between said interconnected devices and a target organ, comprising: a first port adapted to receive a first signal suitable to stimulate a target tissue, a second port adapted to receive a second signal suitable to stimulate a target tissue, and a third port configured to connect to a target organ, wherein at least one of said first and second ports is configured to connect to a signal generator not integrated with said connector.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 26, 2016
    Assignee: Impulse Dynamics NV
    Inventors: Benny Rousso, Yuval Mika, Shlomo Ben-Haim, Daniel Burkhoff, David Prutchi
  • Patent number: 9276615
    Abstract: A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: March 1, 2016
    Assignee: Hypres, Inc.
    Inventors: Timur V. Filippov, Alexander F. Kirichenko, Deepnarayan Gupta
  • Patent number: 9258503
    Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: February 9, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Tokunaga, Yasuhiro Tatewaki
  • Patent number: 9130556
    Abstract: Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 8, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Chiaki Dono, Takenori Sato, Shinya Miyazaki
  • Patent number: 9083394
    Abstract: A high-frequency switch module includes a switch element, high-frequency circuits, and a GND circuit. The switch element includes an antenna port, switch ports, and an FET switch. The FET switch switches connection between the switch ports and the antenna port. The high-frequency circuits connect any of the switch ports to a signal processing circuit. In the GND circuit, the switch port, which is not connected to the high-frequency circuits, is directly connected to a GND electrode.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 14, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takanori Uejima, Shinya Watanabe
  • Patent number: 9013210
    Abstract: A semiconductor integrated circuit may include a plurality of fuse boxes, each suitable for selectively outputting a first input signal and a reverse input signal obtained by inverting the first input signal; and a first output signal generator suitable for selectively receiving the first input signal and the reverse input signal from the fuse boxes, and generating a first output signal by performing a logical combination operation on the received input signals, a second input signal, and a third input signal.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jee Yul Kim
  • Patent number: 9007089
    Abstract: An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: April 14, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Tung-Cheng Kuo, Sheng-Kai Chen
  • Publication number: 20150091635
    Abstract: Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventor: Chengming He
  • Patent number: 8994440
    Abstract: A voltage select circuit includes a plurality of first transfer elements configured to transfer respective operating voltages to a first output terminal, a transfer select circuit unit configured to output a first voltage necessary to transfer an operating voltage, selected from among the operating voltages, to at least one first transfer element in response to a plurality of enable signals, and a control circuit configured to boost the first voltage to a second voltage in response to the plurality of enable signals.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: Je Il Ryu
  • Patent number: 8982657
    Abstract: A semiconductor device includes: a plurality of target lines to be driven; a plurality of target line drivers configured to drive the corresponding target lines in a logic level corresponding to a plurality of target line selection signals; a plurality of booster enable units configured to generate a booster enable signal by sensing whether a group of target lines that is obtained by grouping the target lines by a predetermined number is enabled or not; and a plurality of self-boosters configured to boost corresponding target lines by sensing levels of the corresponding target lines in response to the booster enable signal.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jeongsu Jung
  • Patent number: 8963613
    Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Manas Behera, Yanping Ding, Junxiong Deng
  • Patent number: 8952732
    Abstract: A signal processor includes: a plurality of frequency converters which perform frequency conversion of input signals to output converted signals; and an output section which combines the converted signals output from the plurality of frequency converters and outputs a composite signal, wherein the plurality of frequency converters are formed in a one-chip semiconductor chip, and the plurality of frequency converters perform frequency conversion into converted signals in different frequency bands.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventor: Kenichi Kawasaki
  • Patent number: 8901991
    Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
  • Patent number: 8884660
    Abstract: In a driver, a charging module electrically charges the on-off control terminal of the switching element for turning on the switching element, and a limiting module performs a task of limiting a voltage at the on-off control terminal of the switching element by a predetermined voltage to thereby limit an increase of a current flowing between the input and output terminals of the switching element. A determining module determines whether the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage while the limiting module is performing the limiting task. A correcting module corrects the voltage at the on-off control terminal of the switching element to be close to the predetermined voltage when it is determined that the voltage at the on-off control terminal of the switching element deviates from the predetermined voltage.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 11, 2014
    Assignee: Denso Corporation
    Inventors: Junichi Fukuta, Kazunori Watanabe, Tsuneo Maebara
  • Patent number: 8860493
    Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Chulmin Jung, Sei Seung Yoon, Esin Terzioglu, Hari Ananthanarayanan, Venugopal Boynapalli
  • Patent number: 8854111
    Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 7, 2014
    Assignee: RichWave Technology Corp.
    Inventor: Chen Chih-Sheng
  • Patent number: 8847666
    Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 30, 2014
    Assignee: RichWave Technology Corp.
    Inventor: Chen Chih-Sheng