Abstract: A current sense circuit includes channels a detection terminal, a feedback circuit and third-type switches. The channels respectively have first-type switches and second-type switches. Each of the first-type switches supplies an electric power to a load when the first-type switch is turned on. The second-type switches are respectively connected to the first-type switches in parallel, and respectively detect currents flowing through the first-type switches. The detection terminal is connected to the second-type switches. The feedback circuit includes a single operational amplifier having a first input terminal and a second input terminal. The first input terminal is connected to respective electrodes of the first-type switches close to the load. The second input terminal is connected to respective electrodes of the second-type switches close to the detection terminal. The third-type switches are connected to the electrodes of the first-type switches and the first input terminal.

Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: The present disclosure relates to a technology of sensing a touch. According to the present disclosure, touch sensors are driven in a time division way using multiplexers disposed on a panel and auxiliary signals, with a same phase as that of driving signals, are supplied to electrodes around a touch sensor in driving so as to reduce the introduction of noises from the neighboring electrodes.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Abstract: A lidar photosensor amplification circuit may include light sensors; amplifiers corresponding respectively to the light sensors, in a powered-on state, to amplify output signals of the respective light sensors as amplified outputs; and switches corresponding respectively to the amplifiers, where individual switches may be controlled to pass a respective amplified output in a closed state or disconnect the amplified output in an open state. The lidar photosensor amplification circuit may be controlled by a controller according to timing rules that conserve power supplied to photosensor amplification circuit, reduce heat produced by the light sensor board, and do not aggravate cross-talk between sensors. The timing rules include staging an amplifier for a staging time before the corresponding light sensor is to be read, closing a switch after the staging time has passed, and powering down the amplifier and opening the switch after a reading time passes.

Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

Abstract: A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Abstract: A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage VHI for a fuse programing period or a first non-zero intermediate voltage VMID1 for a non-fuse programming period.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Abstract: Certain aspects of the present disclosure generally relate to a driver circuit for a serializer/deserializer (SerDes) transmitter and techniques for operating such a driver circuit. One example driver circuit generally includes a pre-driver circuit, an output stage circuit, and a common-gate buffer circuit coupled between an output of the pre-driver circuit and a first input of the output stage circuit.

Abstract: Disclosed embodiments include a serial buffer device comprising first and second serial input/output (I/O) ports, first and second comparators, and a multiplexer having a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. There is also a transistor, a third comparator having first and second inputs and an output, wherein the first input is coupled to the second serial I/O port, the second input is coupled to a third reference voltage source, and the output is coupled to the control terminal of the multiplexer. Additionally, the embodiment includes an impedance controlled driver circuit having an input and an output, wherein the input is coupled to the output of the third comparator and the output is coupled to the first serial I/O port.

Abstract: Techniques and apparatus for selecting a maximum input supply voltage from multiple input power supplies. An example maximum input supply selection circuit includes a parallel array of comparators and selection logic to select the maximum input supply voltage, supply present detectors, comparator settling logic including a warm-up delay timer to provide for comparator settling, and comparator enable logic for disabling all comparators and entering an ultra-low power mode.

Abstract: A highly efficient three-dimensional image acquisition method based on multi-mode composite encoding and epipolar constraint, respectively using a fast imaging mode or a high-precision imaging mode, wherein in the fast imaging mode, two phase maps having different frequencies are obtained by four stripe gratings, and a high-frequency absolute phase is obtained by means of the epipolar constraint and a left-right consistency check, and the three-dimensional image is obtained by means of a mapping relationship between the phase and three-dimensional coordinates; and in the high precision imaging mode, two phases having different frequencies are obtained by means of N+2 stripe gratings, a low-frequency absolute phase is obtained by the epipolar constraint, and the unwrapping of a high-frequency phase is assisted by means of the low-frequency absolute phase, so as to obtain the high-frequency absolute phase, and finally, the three-dimensional image is obtained by the mapping relationship between the phase and the

Abstract: A sensor includes an output circuit configured to generate a sensor output signal based on an input signal having a logic high or low level, as may be provided by a Schmitt trigger circuit. During normal operation, the output switches between a first percentage of the supply voltage for logic high and a second percentage of the supply voltage for logic low. To convey a failure at the output, an output signal is output as either ground or the supply voltage when a fault is detected. As such, a fault can be communicated any time the output voltage is not equal to the first percentage or the second percentage of the supply voltage.

Abstract: A receiver circuit includes a first amplifier circuit, a second amplifier circuit, and a selector circuit. The first amplifier circuit is configured to receive a pair of receiving signals. The second amplifier circuit is configured to receive the pair of receiving signals. Based on a selection signal, the first amplifier circuit generates a pair of first amplifying signals according to the pair of receiving signals or the second amplifier circuit generates a pair of second amplifying signals according to the pair of receiving signals. The selector circuit is configured to output the pair of first amplifying signals or the pair of second amplifying signals according to the selection signal.

Abstract: A power switch circuit includes a voltage selection unit, a first level shift circuit, a second level shift circuit, a first transistor, a second transistor, and a leakage control unit. The voltage selection unit outputs a greater one of a first variable voltage and a system voltage as an operation voltage. The first level shift circuit outputs a first control signal by shifting a voltage of a first input signal. The second level shift circuit outputs a second control signal by shifting a voltage of a second input signal. The first transistor outputs the first variable voltage according to the first control signal. The second transistor outputs the system voltage according to the second control signal. The leakage control unit establishes an electrical connection between first terminal of the first transistor and the control terminal of the second transistor according to the operation voltage.

Abstract: A multiplexer circuit, of power supply (PS) voltages, includes: finger circuits correspond to the PS voltages, each selectable finger circuit (A) having an input node which is finger-circuit-specific and an output node which is common to the finger circuits, (B) including an anti-leak transistor of a first conductivity (C1) type, a selector transistor and a driver transistor transistors of a second conductivity (C2) type connected in series between the input node and the output node, and (C) being configured to receive a corresponding one of the PS voltages from the input node, and provide, if selected, a first version of the corresponding PS voltage to the output node.

Abstract: An image detector comprises a sensor produced on a first monolithic substrate comprising a set of pixels organized in a matrix on rows and columns and configured to generate signals as a function of a radiation striking the detector, column conductors, each linking the pixels of a same column and intended to convey the signals generated by the pixels, at least one bump contact situated at the periphery of the first substrate and outside of the matrix of pixels and linked to the column conductors. At least two column conductors are connected together on the first substrate outside of the matrix of pixels and the column conductors connected together converge toward the at least one bump contact.

Abstract: A visible light communication apparatus includes: an on/off switch connected in series to a load circuit including a light emitting diode; an impedance circuit connected in series to the on/off switch; a feedback circuit that feeds back an error between a voltage drop across the impedance circuit and a reference voltage potential to a voltage source as a feedback signal; a drive circuit that turns on and off the on/off switch in accordance with a communication signal which is a binary signal; an isolation circuit that transmits power while being electrically isolated; and an auxiliary power supply circuit that is connected between two output terminals of the voltage source, generates an auxiliary supply voltage, and supplies power based on the auxiliary supply voltage generated to the on/off switch and the drive circuit via the isolation circuit.

Abstract: Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M0 of a type that turns OFF when the applied VGS is essentially zero volts.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

Abstract: The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.

Abstract: A power converter includes one or more first conversion circuits, one or more second conversion circuits, and a controller. The first conversion circuit is configured to use a trench type transistor. The second conversion circuit is configured to use a planar type transistor. All the one or more first conversion circuits and all the one or more second conversion circuits are connected in parallel to each other or connected in series to each other. The controller stops all the one or more second conversion circuits and operates at least one of the one or more first conversion circuits while an output command value is lower than a predetermined output threshold value. The controller operates all the one or more first conversion circuits and operates at least one of the one or more second conversion circuits when the output command value exceeds the predetermined output threshold value.

Abstract: A power on reset circuit according to the present disclosure includes: a reference voltage generating circuit that generates a reference voltage, and also outputs, as a control voltage, a voltage at a node at which a voltage rise is slower than the reference voltage; a comparison voltage generating circuit that operates in response to the control voltage output from the reference voltage generating circuit, and outputs a comparison voltage depending on a power source voltage; and a comparison circuit that compares the comparison voltage output from the comparison voltage generating circuit to the reference voltage output from the reference voltage generating circuit, and outputs an operation signal while the comparison voltage exceeds the reference voltage.

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

Abstract: The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: A matching circuit provides broadband impedance matching of first and second devices for processing RF signals in a broadband frequency range, the first device being inherently capacitive. The matching circuit includes a shunt inductor that transforms impedance of the first device to matching impedance at a matching resonance frequency in a middle portion of the broadband frequency range, and a series resonance circuit that has a series resonance frequency approximately the same as the matching resonance frequency. The series resonance circuit includes an inductor and a capacitor connected in series to the first device, and further transforms the matching impedance of the first device and the shunt inductor to a design matching impedance corresponding to the broadband frequency range. One end of the shunt inductor is connected to the first device, between the series resonance circuit and the first device or to an opposite side of the first device.

Abstract: Apparatus for glitch-free switching between multiple asynchronous clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different, asynchronous clocks without causing erratic behavior.

Abstract: Transistor arrays are disclosed herein. An example transistor array includes a first node for coupling the transistor array to a circuit. A first transistor and a second transistor are coupled to the first node. A gate controller is coupled to the gate of the first transistor and the gate of the second transistor and is for selectively turning on the first transistor and the second transistor. A current source is coupled to the first node and is active when the second transistor is off. Calibration circuitry measures the voltage of the first node when the current source is active.

Abstract: A filter device includes first, second and third filter circuits that are connected to a common terminal. The first filter circuit includes a first inductor that is closest to the common terminal along a first signal line and a first capacitance element that is connected in parallel with the first inductor, the second filter circuit includes a series arm resonator, which is a second acoustic resonator, that is closest to the common terminal along a second signal line, and the third filter circuit includes a third acoustic resonator that is closest to the common terminal along a third signal line.

Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract: A switch, an antenna tuner, and a radio frequency apparatus are provided. The switch includes: 2N successively serially connected transistors. In the 2N successively serially connected transistors, control ends of any two transistors with closest odd sequence numbers are coupled to each other through a first resistor, and control ends of any two transistors with closest even sequence numbers are coupled to each other through a second resistor; a control end of an n-th transistor is coupled to a first control signal in a switch control signal, and a control end of an (n+1)-th transistor is coupled to the first control signal, where n is an integer that is greater than or equal to 1 and is less than or equal to 2N?1, N is an integer greater than or equal to 2, and the first control signal is used to control turn-on or turn-off of the switch.

Abstract: A wide bandwidth multiplexer (MUX) is provided that performs carrier aggregation. The MUX combines at least a first LC filter that acts as a low band filter, at least a first composite filter that acts as a middle band filter, and at least one other LC or composite filter that acts as a high band filter. The wide bandwidth MUX has low insertion loss and provides sufficient attenuation at adjacent edges of adjacent pass bands to prevent overlap between adjacent pass bands.

Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.

Abstract: Apparatus comprises a switch feature configured to restrict an electrical signal transmitted from a peripheral device, and received through an electrical contact, from being transferred to one of first and second circuit modules coupled to the electrical contact, depending on the voltage amplitude of the electrical signal.

Abstract: A semiconductor integrated circuit device includes a PMOS output element having a source electrode connected to a power supply terminal and a drain electrode connected to an output voltage terminal from which an output voltage is supplied. A voltage dividing circuit has resistors for dividing the supplied output voltage to produce a divided voltage. A reference voltage circuit generates a reference voltage and has a memory element whose threshold voltage determines the reference voltage. The reference voltage circuit has a regulating input terminal connected to the memory element to change the threshold voltage of the memory element. An error amplifier is supplied with the divided voltage and the reference voltage to generate a voltage that is applied to a gate electrode of the PMOS output element. The voltage is amplified depending on a difference between the divided voltage and the reference voltage.

Abstract: Multiplexers are described in which differential signals on the signal paths associated with unselected differential inputs are converted to common mode signals to reduce crosstalk between unselected signal paths and the multiplexer's active signal path.

Abstract: An interference-suppression circuit produces an interference-reduced signal from output signals of a plurality of redundant functional blocks. A first extreme-value determination unit determines the specific output signal that represents a first extreme value from the output signals of the functional blocks. A processing unit offsets the output signals of the plurality of functional blocks against one another in such a manner that the interference-reduced signal is determined. The processing unit omits from consideration the first extreme value in determining the interference-reduced signal.