Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: There is provided a system using an analog receptor for passage of signals (either input or output of signals). The system includes a signal switch device coupled to the analog receptor; and a microcontroller controlling the signal switch device, the microcontroller being for the control of the signal switch device when a determination of a type of input signal through the analog receptor is received by the microcontroller. It is advantageous that the signal switch device allows connection to an analog circuit unless the microcontroller causes the signal switch device to divert digital signals input through the analog receptor to the microcontroller. The system may be used in an apparatus such as, for example, a media player docking station, a media player, a PDA, a portable games console, and a mobile phone. It is preferable that the analog circuit may be selected from for example, an operational amplifier, an analog-to-digital convertor, or a digital-to-analog convertor.

Abstract: A method and associated apparatus for enabling a plurality of functions of an integrated circuit to be controlled on a single pin of the circuit. The method includes the steps of providing each of the functions with a designated periodically recurring sampling instance during which time the status of a signal on the single pin will be considered to relate to the function designated to that sampling instance, and controlling each of the functions according to the status of the signal on the single pin during each of the plurality of functions' corresponding designated sampling instance.

Abstract: Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

Abstract: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: Methods and systems are described for converting single-ended signals to differential signals. In one exemplary embodiment, an input single-ended signal is received and converted into a differential signal having minimized jitter without using a DC-cancellation loop.

Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: A relay connector unit for communicating an electronic control unit with a plurality of electronic devices includes: a first connecting unit connected to the electronic control unit; a second connecting unit having a plurality of circuits connected to the electronic devices respectively; and a transferring unit connected to the first connecting unit and the second connecting unit. The transferring unit transmits first information received by the first connecting unit from the electronic control unit to at least one of the electronic devices through a corresponding circuit, on the basis of circuit identifying data included in first information, the circuit identifying data indicating the corresponding circuit to be transferred to or from. The transferring unit appends the circuit identifying data to second information received from one of the electronic devices through the corresponding circuit to transmit the second information to the electronic control unit through the first connecting unit.

Abstract: A signal splitting apparatus which improves the noise figure (NF) characteristic when an input signal is split and transmitting the input signal to another device even when the set does not operate, a video apparatus including the signal splitting apparatus, and a signal splitting method thereof The signal splitting apparatus which splits and outputs an input signal fed to an input port to a plurality of output ports, includes a signal amplifying part which amplifies the input signal; a signal splitting part which splits the amplified input signal; and a switching part which selects either a first mode which provides the input signal to the signal amplifying part to split the input signal, or a second mode which provides the input signal to a specific one of the output ports.

Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: A switch circuit comprising a plural of switch elements and a control circuit operative to simultaneously shut off all of the switch elements. When forming a switch device by the combination of plural switch circuits, no other additional switches connected in series in the subsequent stage is required for shutting off unintentional signals from other input terminals.

Abstract: Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address lines needed for unique addressing in a deterministic, non-randomly fabricated multiplexer or demultiplexer are used. The number of address lines in excess of the minimal number of address lines needed for unique addressing in a deterministic multiplexer or demultiplexer are referred to as supplemental address lines.

Abstract: The invention discloses a semiconductor switching circuit suitable for a Single Pole n Throw (SPnT) switching circuit having: a common terminal; first through third terminals, ground and control terminals, through FETS, shunt FETs, wherein when a first electric potential is supplied only to a Jth control terminal, and a second lower electric potential is supplied to the other control terminals, the common and Jth terminals are electrically connected and the first through third terminals are electrically disconnected.

Abstract: A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-of-phase driving signal is provided by an inverter coupled to the input. The in-phase and out-of-phase driving signals each drive an input of the cross-coupled latch. The in-phase driving signal from the always-on transmission gate starts to bring the cross-coupled latch into conduction, and when the out-of-phase driving signal arrives, the simultaneous driving of the cross-coupled latch causes a rapid and symmetric transition of both outputs of the cross-coupled latch.

Abstract: An input/output buffer is operative in an analog mode and a digital mode. The buffer includes a pad, a digital signal line which includes a transmission gate connected to the pad, an analog signal line connected to the pad, an analog/digital mode controller which sets an output level of the digital signal line in the analog mode, and a transmission gate controller which controls the transmission gate when a signal voltage of the pad exceeds a reference voltage.

Abstract: A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

Abstract: In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts the pre-driver lines to the large p-channel transistors of the pair of outputs, while the other transmission gate shorts the pre-driver lines to the large n-channel transistors of the pair of outputs. Pre-driver lines to the pull-up transistors within a bank driven by the same enable can be hardwired together, as can the pre-driver lines to the pull-down transistors. Shorting switches can short banks together to reduce output skew.

Abstract: Disclosed are systems and methods which provide a common bypass node with respect to multiple circuits of an integrated circuit. According to a preferred embodiment, a circuit for filtering bias noise introduced by components of the integrated circuit may be coupled to this common bypass node and bypass bias filtering may be provided with respect to each of the multiple circuits. According to a preferred embodiment, the common bypass node is associated with an external lead or pin of the integrated circuit to thereby facilitate the efficient use of integrated substrate area as well as the efficient use of external interfaces thereof. Additionally, the common bypass node of the preferred embodiment may be utilized in providing cooperative operation of the multiple circuits coupled thereto.

Abstract: In at least one embodiment, a circuit for a multi-channel tester having a central resource, a plurality of outputs, and a switching matrix coupling the central resource to the plurality of outputs via a plurality of selectable channels. Each of the selectable channels having PIN diodes coupled in a half-bridge configuration. A first, a second, and a third biasing source for forward biasing the PIN diodes. The first and second biasing sources are coupled to a central resource coupled end and an output coupled end of the half-bridge, respectively. The third biasing source is coupled to a common node. The first and second biasing sources are constructed to provide substantially balanced outputs and such that the sum of the outputs of the first and second biasing sources are substantially balanced with respect to the output of the third bias source. In some embodiments, a the plurality of selectable channels comprises the same first biasing source.

Abstract: A configurable multiplexing circuit and arrangement suited for phase locked loop applications. The multiplexing circuit includes an EX-OR element, a multiplexer element and a summer element. Each element is configured for receiving a particular type of detection signal output, as an input for one of multiple selectable multiplexing operations. The multiplexing circuit further includes a selection signal input, coupled to the EX-OR element, the multiplexer element and the summer element, for receiving a selection signal that enables one or more of the EX-OR element, the multiplexer element, and the summer element. Non-enabled elements are powered down to eliminate jitter and performance penalties.

Abstract: A system for testing an integrated circuit. The system includes a plurality of simultaneous switching output (SSO) cells with each of the plurality of simultaneous SSO cells including an output driver providing an output signal to a respective signal pin coupled to the integrated circuit, a toggle circuit toggling its output; a multiplexer selecting a signal for communication to the output driver to control output provided to the respective signal pin, an input signal line communicating an SSO enable signal to the multiplexer, wherein the multiplexer selects the toggled output for communication to the output driver when the SSO enable signal is asserted; and a signal pin that is coupled to each respective input signal line of the plurality of SSO cells.

Abstract: A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate.

Abstract: An oversampling circuit and method is proposed, which is used for converting an input serial data stream into a parallel data format. The proposed oversampling circuit comprises an array of transmission gates arranged into N cascaded stages of main sampling circuits, each stage of main sampling circuit being composed of M parallel layers of sub-sampling circuits, where N, M are each an integer number; each transmission gate has an input end, an output end, and a control port; and the respective control ports of all the transmission gates are connected to a predefined sequence of sampling pulses.

Abstract: A clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal. This clock generation circuit comprises a voltage-controlled oscillator (14) that generates an output signal having a frequency that varies in response to a control voltage; a phase comparator (11) that compares the phase of the input clock signal and the phase of the output signal of the voltage-controlled oscillator, to detect the phase difference therebetween; control voltage generation circuits (12, 13) that generate a control voltage corresponding to that phase difference; and a variable delay circuit (15) that generates multi-phase output clock signals by delaying the input clock signal in accordance with the control voltage.

Abstract: The semiconductor integrated switching circuit S1 employed in a dual-band mobile phone comprises the first through fourth field effect transistor 1, 2, 3, 4 by which electrical connection between either of the first through fourth input/output terminal 22 through 25 and the common input-output terminal 21 are controlled, the fifth field effect transistor 5 which becomes conducting with the second field effect transistor 2, and the series resonance circuit 51 having a resonance frequency equals to a frequency of higher harmonic of the signal passing through the second field effect transistor 2. The fifth field effect transistor 5 and the series resonance circuit 51 are connected in series and attached between the common input-output terminal 21 and the ground so as to divert the higher harmonic of the signal without giving passing loss to the signal.

Abstract: The semiconductor integrated switching circuit S1 employed in a dual-band mobile phone comprises the first through fourth field effect transistor 1, 2, 3, 4 by which electrical connection between either of the first through fourth input/output terminal 22 through 25 and the common input-output terminal 21 are controlled, the fifth field effect transistor 5 which becomes conducting with the second field effect transistor 2, and the series resonance circuit 51 having a resonance frequency equals to a frequency of higher harmonic of the signal passing through the second field effect transistor 2. The fifth field effect transistor 5 and the series resonance circuit 51 are connected in series and attached between the common input-output terminal 21 and the ground so as to divert the higher harmonic of the signal without giving passing loss to the signal.

Abstract: The circuit to be used either to create a simultaneously switching outputs (SSO) event or to create a simultaneously switching inputs (SSI) event. The circuit uses a toggle register to generate a toggling signal and a signal line to operate logic to select the toggling signal as output from the circuit for the SSO event. The signal line is connected to an external pin. The circuit uses another signal line, also connected to an external pin, to disable or tristate the output driver that drives the I/O pin. This permits the circuit to receive input for the SSI event. Two chips, each having a plurality of such circuits, can be arranged so that one chip generates the SSO event and sends it to the second chip, which is configured to receive the SSI event. The circuit also has a pair of registers in a cascade arrangement to provide precise control of the output signal. The circuit has an additional register to disable the output driver and permit the circuit to receive input for a scan event.

Abstract: A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.

Abstract: A novel method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations to allow minimal test time of electronic circuit components is presented. Shoot-through scan problems introduced by loading mismatches on the TAP master and slave clock signal lines are solved by scanning an appropriate value into a programmable register, which increases the delay from master clock signal TCKM off to slave clock signal TCKS on and from slave clock signal TCKS off to master clock signal TCKM on.

Abstract: The inventive circuit allows the circuit to be used either to create a simultaneously switching outputs (SSO) event or to create a simultaneously switching inputs (SSI) event. The circuit uses a toggle register to generate a toggling signal and a signal line to operate logic to select the toggling signal as output from the circuit for the SSO event. The signal line is connected to an external pin. The circuit uses another signal line, also connected to an external pin, to disable or tristate the output driver that drives the I/O pin. This permits the circuit to receive input for the SSI event. Two chips, each having a plurality of such circuits, can be arranged so that one chip generates the SSO event and sends it to the second chip, which is configured to receive the SSI event. The circuit also has a pair of registers in a cascade arrangement to provide precise control of the output signal.

Abstract: In accordance with the present invention a mode select circuit includes a bias circuit and a voltage level encoder. The mode select circuit further includes a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The bias circuit is coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the mode select terminal is not coupled to any of the configuration elements. The voltage level encoder is coupled to the mode select terminal for providing one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.

Abstract: A signal distributing circuit of the invention includes a first element which outputs a first signal and a second signal which is opposite to that of the first signal. The circuit is provided with a first signal line on which the first signal is transmitted and a second signal line on which the second signal is transmitted. A plurality of second elements each of which is connected to the first signal line in a first order and connected to the second signal line in a second order, wherein the second order is opposite to that of the first order. A method for connecting a plurality of loads to first and second signal lines, which are allocated to a regular signal and a signal opposite to that of the regular signal, respectively, of the invention includes connecting the loads to the first signal lines in a first order; and connecting the loads to the second signal lines in an order opposite to that of the first order.

Abstract: An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.

Abstract: A differential signal generator accepts a single-ended signal on an input node and produces a differential signal on differential output nodes. The differential output nodes include a true output node and a complementary output node. In one embodiment, the differential signal generator includes a memory element coupled between the differential output nodes, a first switch that conditionally couples one of the differential output nodes to a reference node, and a second switch that conditionally couples the other differential output node to the same reference node. The memory element includes a latch having cross-coupled inverters. The cross-coupled inverters are each skewed to respond more quickly to one edge of an input signal. When the switches conditionally couple one of the differential output nodes to a ground node, the inverters are skewed to respond more quickly to falling edge input signals.

Abstract: A dual-purpose transmission circuit capable of receiving two or more signals or voltages, or a signal and a voltage, using one input pad, and an input method using the circuit. The dual-purpose transmission circuit includes an internal signal line for transmitting a signal to the inside of the semiconductor device, an internal voltage line for transmitting a voltage to the inside of the semiconductor device, a first transmission portion for connecting the internal signal line to the outside of the semiconductor device in response to a control signal, in a signal input mode, and a second transmission portion for connecting the internal voltage line to the outside of the semiconductor device in response to the control signal, in a voltage input mode.

Abstract: A method for selectively enabling one of X agents in a system so as to allow the selected agent to be active in a shared communication system. The method comprises the steps of assigning each agent to a unique subset M of a plurality of N select lines, M being greater than 1 and less than N, and translating an identification number so as to assert M of the plurality of N select lines. The asserted M select lines uniquely select a designated agent. For one embodiment, all of the X agents may be selected by enabling all N select lines. For another embodiment, more than one but not all of the agents may be selected.

Abstract: A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.

Abstract: A method (701-717) and apparatus for providing a driver system requiring a reduced number of amplifier circuits. Load driving circuitry (205) is configured to include a single loop amplifier (401) for sequentially receiving multiplexed signals representative of the parameter values and effecting the output of such signals to corresponding loads. Sample-and-hold circuitry is coupled between the output of the loop amplifier (401) and load circuitry within the driver circuits (409, 429, 435) in an arrangement such that only one loop amplifier (401) is required in a multiplexed multi-input system.

Abstract: To provide a bi-directional interface circuit which can reduce the simultaneous switching noise and the power consumption even at transitions of the signal direction, a bi-directional interface circuit of the invention comprises: an encoder (10) for generating an output bit sequence in synchronous with a clock cycle of the bus lines, said output bit sequence being obtained by coding an original signal and a redundant bit so that signal alteration rate of the output bit sequence to a preceding bit sequence thereof is less than a half; a decoder (20) for decoding the input bit sequence into an original bit sequence; and bypass lines (3) for bypassing the input bit sequence to the encoder for enabling the encoder to refer to the input bit sequence as the preceding bit sequence when the LSI chip begins to transfer the original signal.

Abstract: Switches are provided on the input and output side of an amplification stage in a signal switching circuit provided in a signal transmission line, and another signal is provided so that a signal can be transmitted directly. Further, a switching circuit is formed from FET elements, which are controlled to be switched on/off by control signals to assure a high isolation.

Abstract: A method is herein provided for placing drivers and repeaters along the interconnect so as to optimize interconnection propagation delay with respect to area and time constraints. The method provided optimizes the propagation delay and simplifies the propagation delay determination by first using drivers to divide an interconnect into forkless branches, then linearizing the delay of each branch by placing repeaters along the length of the branches.

Abstract: An inventive integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.