Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

Abstract: Two electronic modules are connected to share and to independently read the sensed value from a single environmental sensor element, by communicating between each other when a particular module is reading the sensor output signal. The sensor output signal is a function of the value of the reference voltage being applied by the reading module and the characteristics of the environment being sensed. A module provides a toggle signal when it completes its reading of the sensor so that the other (non-reading) module will know when it may apply its reference voltage to the sensor and complete its reading of the sensor. The modules alternate the reading of the sensor in order to eliminate the need for a plurality of corresponding sensors.

Abstract: The semiconductor integrated circuit of this invention includes: a first converter for converting a plurality of input data signals into a composite serial data signal and outputting the composite serial data signal; a second converter for receiving the composite serial data signal via a data signal wiring and converting the composite serial data signal into a plurality of output data signals; and a clock signal supply section for supplying a clock signal for synchronizing an operation of the first converter and an operation of the second converter, wherein the clock signal is input into the first converter and the second converter via a clock signal wiring, the data signal wiring imparts a time delay to the composite serial data signal input into the second converter, and the clock signal wiring imparts a time delay to the clock signal input into the second converter.

Abstract: A selector circuit with symmetry is disclosed. It steers input transition events to one of two outputs according to the value of a data input signal. The selector circuit includes a first flip-flop and a second flip-flop. Depending on the state of a data input, one of the two flip-flops is enabled and the other is disabled. The disabled flip-flop will be in a tristate mode. The enabled flip-flop continues storing its data, and may load the disabled flip-flop with this data. The selector circuit further includes pass gates to couple the outputs of the flip-flops based on the state of the event input.

Abstract: An apparatus controls the operation mode of a time division switching device selected from two incorporated in an electronic switching system for reliability thereof. Mode information representing previous operation modes of the two time switching devices is received and processed to issue a first and a second mode control signals. Thereafter, status of each component in the selected switching device and a power from a power supply in the unselected switching device are analyzed to produce each component status information and power status information. Next, an initial duplexing control signal is obtained based on each component status information, the first and the second mode control signals, and the power status information.

Abstract: A multiplexer includes an n-th stage as a final output stage (n=integer, 2.ltoreq.n); j stages (j=integer, 1.ltoreq.j.ltoreq.n-1), the n-th stage including a D flip-flop having a clock input terminal for receiving a first clock signal, a data input terminal for receiving serial data, and a data output terminal, the D flip-flop synchronizing the clock signal with the serial data; and a j-th stage including m.sup.n-j-1 (m=integer, 2.ltoreq.m) multiplexer blocks, each multiplexer block including D flip-flops and having data input terminals for receiving m parallel data inputs and a clock input terminal for receiving a second clock signal produced by frequency division of the first clock signal, and converting the parallel data into serial data in response to the second clock signal. The multiplexer further includes a variable delay circuit connected to the data input terminal of each multiplexer block in one of the second to the n-th stages for delaying the data input by a variable delay time.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: A power driving circuit of a thin film transistor liquid crystal display includes Darlington circuits for generating voltages corresponding to the gate driving voltages required in the displays. Analog switching circuits control the application of voltages used to form the Von and Voff driving waveforms, which have driving voltage levels generated from the Darlington circuits. The phasing of the driving waveforms is controlled by a phasing signal which is received by the analog switching circuits. The power driving circuit of the present invention consumes less power than conventional driving circuits.

Abstract: A clock driver circuit comprises a first driver including first and second inverters cascaded between an input terminal and a first output terminal for outputting a non-inverted signal delayed from the clock signal applied to the input terminal by a delay amount corresponding to two stages of inverters. The clock driver circuit also comprises and a second driver including third, fourth and fifth inverters cascaded between the input terminal and a second output terminal and a sixth inverter connected between the input terminal and the second output terminal. With this arrangement, a first signal delayed from the clock signal applied to the input terminal by a first delay amount corresponding to the third, fourth and fifth inverters, is synthesized by a wired-OR at the second output terminal with a second signal delayed from the clock signal applied to the input terminal by a second delay amount corresponding to the sixth inverter.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: A switch for controlling the throughput of a signal between a pair of input channels and a pair of output channels is provided which receives an input signal from each of the pair of input channels. The switch transmits an output signal to each of the pair of output channels. Four line channels are provided within the switch. Each of the four line channels connects one of the pair of input channels and one of the pair of output channels. Four line channel switches are also provided, one line channel switch provided on each of the line channels. Each of the four line channel switches is controlled by a signal to open or close the four line channels.

Abstract: A high-speed burst digital time multiplexed data system has N parallel input data paths that are multiplexed onto a serial data path for transmission from a transmitter to a receiver. Serial transmission takes place in a short burst upon command at the transmitter. Data from the serial data path is demultiplexed back into N parallel data paths at the receiver. The entire process is accomplished asynchronously without the aid of a clock or framing signal. In the preferred embodiment, a train of N sampling pulses is generated by two tapped delay lines, one at the transmitter and one at the receiver. The length of each sequential sampling pulse is determined by the tap spacing of the delay line, and the duration of the entire burst process is equal to the total delay of the delay line. A new burst may be initiated at any time after the completion of the previous burst. Thus bursts may follow each other immediately or be arbitrarily spaced to occur whenever data transmission is required.

Abstract: An apparatus for enabling an IC pin to function in a dual mode, which apparatus includes a first switch for coupling the IC pin to an input terminal when the IC pin operates in an input mode, and a charging circuit for sourcing current to the IC pin during a charging cycle of a timer mode. The inventive apparatus further includes a discharging circuit for sinking current from the IC pin during a discharging cycle of the timer mode. In one embodiment, the inventive apparatus further includes a comparator for generating an activation signal, the activation signal being activated when a potential at the IC pin equals or exceeds a predefined voltage in the timer mode. In another embodiment, the comparator is disabled during the input mode.

Abstract: A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.

Abstract: In a method for simultaneous transmission of two heterochronous binary signals in the form of a single binary signal on a common physical medium, the second binary signal is timed by a bit clock whose period is greater than the minimal duration allowed for a bit of the first signal. For constituting the single binary signal transmitted there is provision for inserting between transitions of the first binary input signal a brief binary level inverting pulse for each bit of the second input signal which corresponds to the same one of the two possible binary levels of the second signal. Each temporary polarity inversion pulse due to the second signal is placed outside a guard area on either side of transitions of the first signal.

Abstract: A method and an arrangement minimizes skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an input and an output. Each driver circuit has a delay of .delta..sub.1, .delta..sub.2, .delta..sub.3, .delta..sub.4 . . . .delta..sub.N. Of these buffer units, N-1 buffer units are reserved while the inputs of the remaining buffer units P-(N-1) are connected mutually in parallel. The reserved buffer units are used as follows. A signal deriving from a signal source is applied to an input of a first buffer unit in each of the N-number of driver circuits, where the signal is subjected to a delay. The one-time delayed signal from a driver circuit is then delayed once, and only once, in the reserved buffer units of each of the remaining driver circuits. This procedure is repeated for each of the once-delayed signals on the outputs of the first buffer unit in each of the remaining N-1 driver circuits.

Abstract: A storage element is provided in a circuit arrangement for latching one bit. A first MOS transistor (T1) is provided which, when a first control signal (S1) is present, switches an input signal corresponding to the bit to the input of the storage element. The storage element is provided with circuit elements by which an output signal at the output of the storage element is brought to a predetermined potential in dependence on the level of the input signal. The circuit arrangement is particularly suitable for constructing an address latch for DRAMs, particularly of the 16-M generation.

Abstract: A distributed clock generation scheme is provided for a microprocessor that reduces electromagnetic interference and power consumption. Rather than using a single, large internal clock generator circuit that meets the drive requirements of the remaining circuitry upon the microprocessor die, a plurality of smaller clock generator circuits are distributed across the die, each generating clock signals to drive a separate portion of the microprocessor circuitry. Each of the distributed clock generator circuits may be load matched with respect to the others to minimize the skew between clock signals, and each receives a synchronized timing signal provided from a master timing distribution circuit. As a result of the distributed clock generation scheme, the amount of current and the rate at which current is sourced or sunk at a given location on the semiconductor die is reduced, thereby reducing electromagnetic interference and increasing the signal to noise ratio.