Abstract: A voltage sensor device includes an oscillator unit, the oscillator unit having a tunable bulk acoustic wave (BAW) resonator device and an oscillator core. The voltage sensor device also includes a frequency analyzer configured to obtain frequency measurements for the oscillator unit and to determine a voltage sense value based on a comparison of at least some of the obtained frequency measurements. The voltage sensor device also includes an output interface configured to store or output voltage sense values determined by the frequency analyzer.

Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided.

Abstract: A dual modulation network is disclosed. The dual modulation network includes a primary network hub (PNH) having a PNH Long range transceiver and a PNH microcontroller. The PNH microcontroller has communication firmware for long range spread spectrum (SS) and narrowband frequency shift keying (FSK) signal communication via the PNH Long range transceiver, and includes a PNH clock signal. The dual modulation network also includes a peripheral device (PD). The PD includes an actuation mechanism, a PD Long range transceiver, and a PD microcontroller. The PD microcontroller has actuation firmware, communication firmware for communication via the PD Long range transceiver, and location firmware, and includes a clock signal. The location firmware instructs the PD long range transceiver to transmit a location signal encoded with a PD transmit time stamp notifying a receiving device of the time the PD transmitted the location signal.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A device compensating for a loss in sensitivity of a sensor, such as a trackpad. The device may be standalone, integrated with the trackpad itself, or within the associated integrated circuit designed to measure relative electrode capacitances. The embodiment generally employs a current source to negatively compensate for the current available to charge at least one capacitor (or other storage device) in the trackpad.

Abstract: An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal.

Abstract: A method of signal identification, including: receiving a signal; utilizing a clock generated by a ring oscillator to sample the signal continuously to generate a plurality of sampled signals; counting each sampled signal length corresponding to successive sampled signals each having an identical value; and identifying a content of the signal according to a plurality of sampled signal lengths. A signal identification apparatus, including: a receiving circuit, arranged for receiving a signal; a ring oscillator, arranged for generating a clock; a sampling circuit, arranged for sampling the signal continuously to generate a plurality of sampled signal; a counter, arranged for counting each sampled signal length corresponding to successive sampled signals each having an identical value; and a determining unit, arranged for identifying a content of the signal according to a plurality of sampled signal lengths.

Abstract: In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section.

Abstract: In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A wake-up circuit, comprising: a control signal generation circuit comprising: a pulse generator configured to receive a digital signal and generate a pulse sequence signal with a frequency thereof; a first comparison circuit and a second comparison circuit both coupled to the pulse generator and configured to receive the pulse sequence signal; the first comparison circuit is configured to compare the frequency of the pulse sequence signal with a first threshold frequency and generate a first control signal; the second comparison circuit is configured to compare the frequency of the pulse sequence signal with a second threshold frequency and generate a second control signal; the frequency detector further comprises: an indication generation circuit configured to generate a wake-up indication if the frequency of the pulse sequence signal falls within a frequency range defined by the first and second threshold frequencies.

Abstract: A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut—1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut—2). The selected frequency source is compared to fpdOut—1 and fpdOut—2 signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A window sampling system and method are provided for comparing a signal with an unknown frequency to a reference clock. A pattern modulator accepts a compClk signal and supplies a test window with a period equal to n compClk periods, where n is an integer greater than 1. A pattern detector accepts the test window and a reference clock, and contrasts the test window with the reference clock. In response to failing to fit n reference clock periods inside the test window, the pattern detector supplies a frequency pattern detector output signal (fpdOut) indicating that the frequency of the compClk is greater than the reference clock frequency.

Abstract: A frequency characteristic measuring apparatus measures a device under test in which the frequency of an input signal and the frequency of an output signal differ from each other, simplifying the configuration of a tracking generator and peripheral circuits associated with the tracking generator, and simultaneously measuring the characteristics of the input signal and the output signal of the device under test. A spectrum analyzer has mixers, local oscillators and IF sections as first and second measuring units for measuring frequency characteristics of two input signals by performing frequency sweep in correspondence with a first or second frequency range, a mixer and an oscillator as a tracking generator section which operates by being linked to the frequency sweep operation in the first measuring unit, and a section which generates a trigger signal designating measurement start timing.

Abstract: A control indication assembly. A first control mounted on a surface of a computer is coupled to a first sensor, to a first sensing circuit to send an electrical signal to the first control when a user-touch occurs to the first sensor, and to a first indicator to indicate an occurrence of said user-touch. A second control mounted on a surface of a display which is coupled to the computer is coupled to a second sensor, to a second sensing circuit to send an electrical signal to said second control when said user-touch occurs to the display, and to a second indicator to indicate an occurrence of the user-touch. The first and second control are configured such that the first and second indicator are synchronized to exhibit identical behaviors when the user-touch occurs to either the first control or the second control.

Abstract: A method and an apparatus to detect over clocking of a processor are illustrated. The over clocking detector may detect as to whether the system clock of a microprocessor is over clocked and then generate an over clocking indicator. The over clocking indicator may be stored and accessed at a later time. The over clocking indicator may be retrieved through a test access port.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

Abstract: A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Abstract: In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: A semiconductor device includes a control unit for outputting an oscillation enable signal in synchronization with transitions of an input clock and buffering the input clock to output a comparison clock corresponding to an activation timing of the oscillation enable signal. A reference frequency generating unit outputs a reference clock having a predetermined frequency based on the oscillation enable signal. First and second counting units count clocking numbers of the reference clock and the comparison clock respectively until a preset count value. A comparing unit compares the clocking number of the reference clock with that of the comparison clock to generate a comparison signal.

Abstract: High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal.

Abstract: Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory device is automatically set based at least in part on the measured frequency of the external clock signal. The automatically set CAS latency value is then used to generate the internal clock signal from the external clock signal. In these methods, the delay of a delay lock loop of the semiconductor memory device may be based at least in part on the automatically set CAS latency value. The internal clock signal may be generated from the external clock signal using the delay lock loop. Circuits and methods for measuring the frequency of the external clock signal are also provided.

Abstract: A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

Abstract: Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.

Abstract: An object of the present invention is to provide a phase comparing circuit capable of outputting a signal in accordance with phase difference with a high degree of accuracy, even if the phase difference is small. The phase comparing circuit according to the present invention has a feed forward circuit connected between a frequency phase comparator and a charge pump. The feed forward circuit has a capacitor connected between each Q output terminal of flip-flops in the frequency phase comparator and the current path of the charge pump circuit. The capacitor couples capacitively the Q output terminals of the D flip-flops with the current path of the charge pump circuit, in order to quickly provide the Q output voltages of the D flip-flops to the charge pump circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a device input signal. The apparatus may be configured to perform a predefined function in response to the device input signal during normal operation. The second circuit may be configured to determine when the device input signal is invalid according to a predetermined parameter. The second circuit may be configured to generate a function control signal in response to the predetermined parameter. The function control signal may be configured to direct the apparatus to perform a second predetermined function. The second predetermined function may be different than the first predetermined function.

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Abstract: A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first condition characterized as a “dead zone” when their frequency difference is within a predetermined frequency range; (b) a second condition when the frequency of the first signal is greater than that of the second signal by the predetermined range; and (c) a third condition when the frequency of the second signal is greater than that of the first by the predetermined range. Frequency detectors embodying the invention are suitable for use in frequency tuning systems.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: There is provided buffer circuitry that can include a data output circuit for connecting a first power supply to its output terminal when a data applied thereto is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level, a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency, and a driving capability changing circuit for, only if the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the reference frequency, connecting a second power supply to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level.

Abstract: A sensor for detecting a physical parameter is capable of detecting an error state in which normal physical parameter detection is not possible even though the output voltage is within a normal output voltage range is disclosed. Errors such as a normal reference frequency signal not being output from an oscillation circuit for some reason, or the frequency of the reference frequency signal output from the oscillation circuit not being within a particular frequency range, can occur. The physical parameter sensor of the invention comprises a self-testing circuit for detecting such error states, and outputting a signal indicating such error detection.

Abstract: An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the external clock signal. Based upon this comparison, the appropriate frequency for the internal clock signal that controls the bus interface unit is determined. A clock generation circuit, such as a phase-locked loop, generates the appropriate frequency for the internal clock signal based upon the comparison of the reference clock signal and external clock signal.

Abstract: A frequency detecting circuit is provided that includes a level shift detecting unit for generating pulse signals of a certain pulse width at each level shifting of input clock signals and a level detecting unit. The level detecting unit includes a charging unit and a discharging unit. The discharging unit is activated by the pulse signals of the level shift detecting unit to discharge the charges of the charging unit. An inverter having a logic threshold voltage receives electrical signals in accordance with the charged level of the charging unit to output a signal indicative of the frequency of the input clock signals.

Abstract: A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal.

Abstract: A circuit is designed with a reference circuit (200) for generating a reference signal. The reference signal determines a reference period. A delay circuit (208, 212, 216) responsive to the reference signal produces a delay signal. A control circuit (248, 254, 258, 260, 262) responsive to the delay signal produces a control signal. The delay circuit emulates the speed of an integrated circuit for the reference period. Control signals from the control circuit compensate the integrated circuit performance for measured circuit speed variations.