Abstract: A semiconductor device (e.g., a zero-delay buffer) is provided which is capable of reducing current or power consumption without the use of a dedicated pin. The device may include a frequency detector that receives a detector input signal corresponding to or derived from a device input signal. The device input signal performs a first function during normal operation of the device. The detector determines whether the frequency of the detector input signal is less than a predetermined minimum, and if so, generates a power down signal configured to direct the device to reduce current or power consumption in at least one of its component circuits. The frequency detector may include a "one-shot" circuit responsive to the detector input signal for generating a frequency indicator signal, and a "power down" signal output circuit responsive to the frequency indicator signal for generating the power down signal.

Abstract: A method for improving the precision of a signal generator utilizing counters. The difference between an external standard signal frequency and an internal standard frequency is measured by digital counters. The signal of this internal standard frequency signal source is counted by a first counter and the frequency of an external standard frequency signal source is counted by a second counter. A calculating and control part determines the accurate frequency of internal standard frequency signal source from count values of both counters. The measurement frequency signal source generates a signal with the desired frequency. The circuit is digitally implemented.

Abstract: A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted value, large magnitude of frequency departure of repeated frequency of the reference clock from a frequency that should be is judged. Also, through comparison of given number of lower bits of the counted value and externally set detecting value, departure of the repeated frequency of the reference clock from the frequency that should be, is judged. When the counted value reaches a predetermined value, free running condition of the counter is judged to stop counting operation. When judgement is made that the repeated frequency of the reference clock is departed from the frequency that should be, the working reference clock is replaced with a back-up reference clock in response to an alarm.

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.

Abstract: A frequency difference detection apparatus includes a first PLL, a second PLL, a first phase difference detection unit, a second phase difference detection unit, a phase difference processing unit, and a frequency difference detection unit. The first PLL detects a phase difference between an input clock and an output clock in response to the input clock and performs control to gradually suppress the detected phase difference to zero. The second PLL detects a phase difference between the input clock and an output clock in response to the input clock and performs control to suppress the detected phase difference to zero at a speed higher than that of the first PLL. The first phase difference detection unit detects a phase difference between the input clock and the output clock from the first PLL. The second phase difference detection unit detects a phase difference between the input clock and the output clock from the second PLL.

Abstract: A common mode controlled signal multiplier includes a pair of interconnected differential amplifiers, each of which receives a common mode signal and an input signal and generates one phase of a differential output signal. In one of the differential amplifiers, the common mode signal is applied to the input terminal of each transistor, while the input signal is applied differentially to the input terminals of the transistors. In the other differential amplifier, an inverse phase of the common mode signal is applied to the input terminal of each transistor, while the input signal is applied differentially to the input terminals of the transistors. The differential amplifiers together generate the differential output signal, with such differential output signal having output frequencies including a sum of and a difference between the frequencies of the common mode signal and the input signal.

Abstract: An IC chip operation inhibitor to prevent operation of an IC chip in a system having a clock rate that exceeds a predetermined reference clock rate for the chip. The inhibitor has a frequency detecting device that generates at least one reference frequency. It compares the system clock with the reference frequency and prevents the chip from operating if the system clock frequency is greater than the reference frequency. The invention includes an external actuating device coupled to the frequency detecting device for generating a compare enable signal to actuate the comparing function of the frequency detecting device, and for generating a frequency select signal for selecting one of the built-in reference frequencies to be compared with the system oscillating frequency. The external actuating device may be turned off in order not to actuate the comparing function of the frequency detecting device when it is sure that the system oscillating frequency will not be higher than the reference frequency.

Abstract: A frequency multiplier circuit generates an supplemental high-frequency timing signal from a single, low-frequency current-controlled oscillator (CCO). The current-controlled oscillator (CCO) generates a controlled discharge current and a controlled bias current which are controlled in parallel to substantially eliminate inaccuracies in a characteristic frequency-current curve of the current-controlled oscillator. The frequency multiplier circuit generates a high-frequency timing signal using the digitally-controlled CCO and avoids the usage of a phase-locked loop (PLL) technique. Specifically, a frequency multiplier includes a current-controlled oscillator having a plurality of input lines connected to receive a digital current select signal and having an output terminal connected to carry a timing signal at a current-controlled oscillator frequency f.sub.CCO set in accordance with the current select signal.

Abstract: A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.

Abstract: A free running relaxation oscillator is disposed on a semiconductor integrated circuit die for generating a frequency representative of the natural frequency of the die. The natural frequency of the die changes for different operating temperatures and voltages. An optimal speed may be determined at which the die will reliably operate by measuring the natural frequency. The die may be effectively graded and matched with a similar die by correlating the natural frequency of the die with the temperature and voltage values at which the natural frequency was measured for each die. A plurality of integrated circuit dice may be connected into a digital system, and the natural frequencies of each die may be monitored so as to optimize the system operating speed, reduce system power consumption without degrading performance, and/or increase the operating speed of a slower die by changing the temperature and/or operating voltage thereof.

Abstract: A frequency monitor and error detector circuit that processes an input ac signal to be monitored, comparing the input ac signal with an internally generated reference center frequency, and outputting a "Go/No-Go" signal indicating whether the monitored ac signal frequency is within a pre-selected tolerance band or is out of tolerance. The reference frequency is provided by a highly accurate crystal oscillator. An adjustable delay circuit is provided, capable of being adjusted to produce a frequency tolerance band of from +/-0.05% to 0.1% of the center frequency. The device has three output signals which may be logic high or logic low, and are used for activating illuminated indicators or as frequency signal inputs to other equipment. The device is small in size, accurate and reliable over a wide range of frequencies.

Abstract: In a device for encoding a pulse phase difference or controlling an oscillation frequency based on delayed signals sequentially output by a delay circuit, the encoding of a pulse phase difference or the oscillation control can be simultaneously performed using a single delay device. There is provided a frequency converter including a ring oscillator consisting of inverting circuits interconnected in the form of a ring, a pulse phase difference encoding circuit for encoding the cycle of a reference signal into a binary digital value based on a pulse output by the ring oscillator, an arithmetic circuit for multiplying or dividing the binary digital value by a predetermined value to generate control data and a digitally controlled oscillation circuit for generating a pulse signal in a cycle in accordance with the control data based on the pulse output by the ring oscillator, the ring oscillator being shared by the encoding circuit and oscillation circuit.

Abstract: A harmonic filter for active or adaptive noise attenuation control systems for obtaining the complex amplitude of a single harmonic component from a signal which contains one or more harmonic components.

Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307)is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

Abstract: A method and apparatus for a "self-calibration timing circuit" is utilized to dynamically compensate for inherent performance differences between individual semiconductor dice, and for a wide range of different operating temperature and voltage parameters. The present invention accomplishes this by utilizing circuits which are deposed on the semiconductor die. These circuits consist of a relaxation oscillator running at the natural frequency of the silicon die, a gated counter counting the number of cycles of the relaxation oscillator frequency during a reference clock period to produce a ratio thereof, and a decision circuit that utilizes this ratio to optimize a system clock frequency for best system operation.