Abstract: Systems, methods, techniques and apparatuses of power switch control are disclosed. One exemplary embodiment is a power switch comprising a thyristor-based branch including a thyristor device; a FET-based branch coupled in parallel with the thyristor-based branch and including a FET device; and a controller. The controller is structured to turn on the FET device, turn on the thyristor device after turning on the FET device based on a thyristor voltage threshold, and update the thyristor voltage threshold based on a voltage measurement corresponding to the thyristor-based branch measured while the thyristor device is turned on.

Abstract: A synchronous rectifier (SR) controller includes a controller having an input adapted to be coupled to a drain of an SR transistor, and an output for providing a drive signal in response thereto, a gate driver having an input coupled to the output of the controller, and an output adapted to be coupled to a gate of the SR transistor for providing a gate signal thereto, a first transistor having a drain coupled to the gate terminal, a gate, and a source coupled to ground, and a protection circuit having an input coupled to the drain terminal, and an output coupled to the gate of the first transistor. The protection circuit is responsive to a voltage on the drain terminal exceeding a first voltage to provide a voltage on the gate of the first transistor greater than a turn-on voltage and less than an overvoltage of the first transistor.

Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.

Abstract: A solid state switch may include a plurality of inputs, such as to receive a control signal to cause the solid state relay to selectively deliver power from an AC power source to an electrical load (e.g., a heater, a pump, a lighting source, a motor, etc.). The solid state switch may include at metal-oxide-semiconductor field-effect transistors (MOSFETs) connected in a series opposition arrangement, where a gate of each of the MOSFETs may be electrically connected to a corresponding one of the plurality of inputs. A signal output from the MOSFETs may provide a triggering signal at a gate input of each of a corresponding semiconductor switching device to close the solid state relay to enable power delivery from the AC power source to the electrical load.

Abstract: A dimmable LED illumination system includes a LED lamp, a switch, and a driver. The LED lamp receives electric signals to emit light; the switch is connected to a power source, and generates a pulse signal by being turned off and then on again in a predetermined time; the driver connects the switch to the LED lamp to convert electric power of the power source into the electric signals which are supplied to the LED lamp when the switch is turned on. In addition, the driver saves a setting luminance, a default illumination mode, and a luminance adjustment mode. When the driver receives the pulse signal, one of the two modes is selected to light the LED lamp.

Abstract: A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer.

Abstract: A motor includes a rotor, a sensor unit, an offset unit, a rectification unit and a modulating unit. The sensor unit outputs a first signal in accordance with a magnetic field variation of the rotor. The offset unit is coupled to the sensor unit, and outputs a second signal in accordance with the first signal. The rectification unit is coupled to the offset unit, and outputs a third signal in accordance with the second signal. The modulating unit is coupled to the rectification unit, and outputs a control signal in accordance with a result by comparing the third signal with a periodic signal. The modulating unit controls a reverse rotation of the rotor smoothly in accordance with the control signal. A control method of the motor is also disclosed.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vp) and a latch circuit comprising a p-channel transistor and an n-channel transistor (208-214). A semiconductor controlled rectifier (206) in the circuit includes at least one terminal of the p-channel transistor. A fuse (200) is coupled between the voltage supply terminal and the semiconductor controlled rectifier. The fuse is programmed in response to the semiconductor controlled rectifier.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: The active rectifier circuit and related method of operation disclosed herein is self-powered and improves the efficiency and reliability of photovoltaic solar power systems by replacing the conventional bypass and blocking rectifiers used in such systems. The circuit includes a power MOSFET used as a switch between the anode and cathode terminals, and control circuitry that turns on the MOSFET when the anode voltage is greater than the cathode voltage. The method of operation utilizes resonance to produce a large periodic voltage waveform from the small anode-to-cathode dc voltage drop, and then converts the period voltage waveform to a dc voltage to drive the gate of the power MOSFET.

Abstract: A resonant tank circuit has an output port configured to be coupled to a load comprising a current-controlled semiconductor device, such as a diode, thyristor, transistor or the like. A voltage generator circuit is configured to intermittently apply voltages to an input port of the resonant tank circuit in successive intervals having a duration equal to or greater than a resonant period of the resonant tank circuit. Such an arrangement may be used, for example, to drive a static switch.

Abstract: A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vp) and a latch circuit comprising a p-channel transistor and an n-channel transistor (208-214). A semiconductor controlled rectifier (206) in the circuit includes at least one terminal of the p-channel transistor. A fuse (200) is coupled between the voltage supply terminal and the semiconductor controlled rectifier. The fuse is programmed in response to the semiconductor controlled rectifier.

Abstract: A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: A switching array includes a plurality of switching elements electrically coupled to each other, each switching element being configured to be switched between conducting and non-conducting states. The switching array also includes at least one parasitic minimizing circuitry electrically coupled to the plurality of switching elements and configured to provide near zero electrical voltage and current across and through each of the plurality of switching elements during switching of the plurality of switching elements between the conducting and non-conducting states.

Abstract: The present invention discloses a smart driver used in flyback converters adopting a transconductance amplifier to turn on a synchronous rectifier FET, and a comparator to quickly turn off the synchronous rectifier FET.

Abstract: A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors.

Abstract: In a conventional switch circuit capable of bidirectional conductivity, there is the problem that latch-up occurs in a parasitic thyristor included in a transistor having a switching function. Therefore it is an object of the present invention to provide a switch circuit capable of bidirectional conductivity while suppressing the occurrence of latch-up due to a parasitic thyristor. The present invention provides a switch circuit that includes diodes connected in parallel with each of a MOS transistor having the switching function and parasitic diodes present at the source and the drain of the MOS transistor.

Abstract: A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.

Abstract: A method and apparatus for controlling a device by detecting a silicon controlled rectifier (SCR) thereof, as well as a method and apparatus of automatic transfer switch controller thereof are disclosed. In one embodiment, the apparatus includes an input configured to receive input power, an output configured to provide said input power to a load a switch unit electrically coupled between said input and said output, the switch unit having at least one silicon controlled rectifier (SCR), a control unit electrically coupled to the switch unit for detecting the SCR of said switch unit and configured to provide a driving signal, and a device, which is driven by said control unit, wherein the driving signal is determined by the control unit after detecting a voltage value between the gate electrode and the cathode electrode of said SCR.

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

Abstract: A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement that protects the device against malfunction and harm during operation. According to an example embodiment of the present invention, a semiconductor device includes a protection circuit that is adapted to discharge excess current and/or voltage in response to the voltage level at an input pad and to the operating condition of the device. The circuit protection circuit is configured to a first configuration during a power-up mode and to a second configuration during a power-down mode. When the voltage at the input pad reaches a selected threshold, the input voltage is discharged.

Abstract: An integrated ringing access switch circuit for telecommunications switching applications that provides improved dV/dt sensitivity at low operating power by using a pilot controlled rectifier, such as an SCR, that conducts at low ringing signal currents and operates to steer a bias current for causing a relatively larger controlled rectifier in parallel therewith to become conductive during higher load current operation. Also included is circuitry for preventing inadvertent turn-on of the SCRs in response to transient signals.

Abstract: A gate driving circuit for power semiconductor switch including a DC voltage source whose positive output terminal is connected to a cathode of a power semiconductor switch, a series circuit of a reactor and a turn-on switching element connected across the positive output terminal of the DC voltage source and a gate of the power semiconductor switch, a turn-off switching element connected across the gate of the power semiconductor switch and a negative output terminal of the DC voltage source, a freewheel diode connected across the negative output terminal of the DC voltage source and a junction point between the turn-on switching element and the reactor, and a control circuit for controlling the turn-on and turn-off switching elements such that the power semiconductor switch is kept non-conductive by making the first and second switching elements in off-state and in on-state, respectively, upon turning-on the power semiconductor switch, after storing energy in said reactor by changing the first switching e

Abstract: In an FET device having a pair of input terminals, a pair of output terminals, a plurality of FETs and driving circuits, the driving circuit has such a circuit structure that source electrodes of the FETs are electrically connected to each other. Each of gate electrodes of the FETs is independently connected to a photo-diode array. The gate electrodes of the FETs are not electrically short-circuited to each other. The FETs are tuned on and off in response to a single control signal.

Abstract: An MOS-controlled, lateral SCR device including a semiconductor substrate of a first doping type; a first well region formed in the substrate and being of a second doping type which is different from the first doping type; a second well region formed in the substrate, being of the second doping type, and being spaced apart from the first well region so as to define an intermediate region separating the first and second well regions from each other; a first region formed within the first well region and extending into the intermediate region between the first and second well regions, the first region being of the second doping type; a second region formed within the second well region and extending into the intermediate region between the first and second well regions, the second region being of the second doping type; and a control gate bridging over the intermediate region between the first and second regions.

Abstract: A circuit for discharging of a photovoltaic power source has a first and a second terminal and the circuit comprises a discharge circuit which is connected between the first and second terminal of the power source which comprises a controllable current source which is controlled by a band gap reference.

Abstract: A driver circuit delays the turning on of a MOS transistor by utilizing the time-wise pattern of the circuit input signal rather than generating a delay within the circuit itself. A threshold type of circuit element is arranged so that no current flows toward or from, depending on the type of the MOS transistor, the control terminal before the voltage at the circuit input exceeds a predetermined value. This is achieved, for example, by coupling a Zener diode serially to the control terminal. Where the input signal is of a kind which increases with a degree of uniformity, the time required to exceed that threshold will correspond to the desired delay. Thus, the driver circuit can match the dynamic range of the input signal automatically.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: A resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit is presented for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit or integrated circuit chip. The suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit.

Abstract: A power driver circuit for turning a semiconductor switching device on and off in response to receipt of a control signal includes a trigger circuit that turns on a latching switch at a speed that is independent of the rate of change of the control signal. The trigger circuit is responsive to the control signal to apply a current from the semiconductor switching device to the latching switch. A high speed SCR may be used as the latching switch and may be triggered by a small trigger current from the gate of the semiconductor switching device fed to both the anode and cathode gates of the SCR. High speed diodes may also be used to increase the speed of the circuit. The power driver circuit improves the efficiency of the semiconductor switching device by decreasing the time the switching device spends in transition its two steady states.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A fast turn-on electrical switch circuit includes a silicon controlled rectifier ("SCR") connected substantially in parallel with a MOS controlled thyristor ("MCT"). When the switch is turned on, the MCT turns on almost immediately and carries the circuit load during the spreading time of the SCR. The SCR subsequently carries the circuit load when it is turned fully on because it has a smaller forward drop, due in part to its larger area and/or higher carrier lifetime. The MCT and SCR may be gated simultaneously from the same or separate sources or the SCR may be gated with a portion of the current from the MCT. The switch may be integrated into a single semiconductor device with alternating MCT regions and SCR regions.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.