Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first nitride-based transistor, and a second nitride-based transistor. The first nitride-based transistor applies the 2DEG region as a channel thereof and comprising a first drain electrode that makes contact with the second nitride-based semiconductor layer to form a first Schottky diode with the second nitride-based semiconductor layer. The second nitride-based transistor applies the 2DEG region as a channel thereof and includes a second drain electrode that makes contact with the second nitride-based semiconductor layer to form a second Schottky diode with the second nitride-based semiconductor layer, such that the first Schottky diode and the second Schottky diode are connected to the same node.

Abstract: A system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range.

Abstract: Aspects of an electrical safety device that provides detection of miswiring of line and load connection pairs are presented. In an example, the device includes a differential current detector through which are routed a live current path and a neutral current path coupling the line and load connection pairs. The device also includes a selectable conducting path that, when selected, circumvents the differential current detector while coupling one of a line live connection to a load live connection or a line neutral connection to a load neutral connection of the connection pairs. The device further includes a control circuit that determines, via the differential current detector, while the conducting path is selected, a differential current defined by a difference in currents on the live and neutral current paths, and interrupts at least one of the live and neutral current paths in response to the differential current not exceeding a threshold value.

Abstract: A circuit interrupting device having a dual-coil solenoid for delivering an increased magnetic field to the solenoid plunger when a fault is detected and it is desired to place the device into a tripped condition. Independent switching devices control the flow of current through the respective coils of the solenoid and a third switching device controls the operation of the two coil driving switch devices. A detection circuit detects faults and controls the third switching device to activate the coil driving switching devices when a fault is detected. A programmable device runs a self-test program to determine whether the device is operating properly and faults can be detected. The programmable device can also independently control the operation of the two coil driving switching devices.

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range.

Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

Abstract: According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the control electrode is electrically separated from a source electrode, a drain electrode, and a gate electrode of the power device. The control voltage is separately applied to the control electrode. The method may include applying a negative control voltage to the control electrode prior to applying a gate voltage to the gate electrode.

Abstract: A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output.

Abstract: In an electronic device with a switching element, a control circuit controls the voltage at the control terminal of the switching element and drives the switching element, by controlling an ON-drive switching element and an OFF-drive switching element based on an inputted drive signal to the control circuit. The control circuit is configured to turn OFF a switching element using a switching circuit other than the OFF-drive switching element after an elapse of a predetermined period of time from a timing at which the drive signal switches from an ON instruction thereof to an OFF instruction thereof, the ON instruction giving an instruction to turn ON the switching element, the OFF instruction giving an instruction to turn OFF the switching element.

Abstract: A four quadrant bidirectional switch. In one embodiment, the four quadrant bidirectional switch comprises a first switch, a second switch, and a third switch, wherein (i) the first and second switches are normally-off switches, (ii) the third switch is a dual-gate, bidirectional, normally-on switch, and (iii) the first, the second, and the third switches are coupled to one another in a bi-cascode configuration.

Abstract: A winding switching apparatus includes a winding switching device and a drive circuit. The winding switching device is configured to switch a plurality of windings of an AC motor. The drive circuit is configured to control the winding switching device. The winding switching device includes a winding switch, a diode bridge, and a capacitor. The diode bridge includes a positive-side DC output terminal, a negative-side DC output terminal, and AC input terminals. The AC input terminals corresponds to respective phases of the AC motor. The positive-side and negative-side DC output terminals are respectively connected to positive-side and negative-side DC buses provided in an inverter. The AC input terminals are respectively connected to winding-switching terminals corresponding to the respective phases of the AC motor. The AC input terminals are respectively connected to phase terminals provided in the winding switch.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: The present invention relates to a driving circuit of switch device. The present invention employs transformer isolated driving. The number of said transformers is two. The primary sides of the two transformers are connected to two driving modulators, respectively. The input terminal of a high frequency carrier signal and the input terminal of a driving signal are connected to the input terminal of a first driving modulator. The input terminal of a driving signal being connected with an inverter together with the input terminal of the high frequency carrier signal are connected to the input terminal of a second driving modulator. The first secondary side of the first transformer is connected to a power supply circuit which may provide a necessary voltage for turning on the switch device during a high level period of the driving signal.

Abstract: In one embodiment, a charge pump controller is configured with transistors having at least two different selectable on-resistance values may be used to charge a pump capacitor.

Abstract: In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.

Abstract: A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q101 and Q102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102, a P-type MOS transistor Q103 and N-type MOS transistor Q105 having drains connected to the gate of Q101, a P-type MOS transistor Q104 and N-type MOS transistor Q106 having drains connected to the gate of Q102, and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q103 and Q104 connected to the sources of Q101 and Q102. Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.

Abstract: A semiconductor device with switch electrode and gate electrode and a method for switching a semiconductor device. One embodiment provides a semiconductor substrate with an emitter region, a drift region, a body region and a source region. The drift region is formed between the emitter and the body region while the body region is formed between the drift and the source region. A first trench structure extends from the source region at least partially into the drift region. The first trench structure includes a gate electrode arranged next to the body region and a switch electrode arranged in portions next to the drift region, wherein the switch and gate electrodes are electrically insulated from each other in the trench structure. A first gate driver is electrically connected to the gate electrode while a second gate driver is electrically connected to the switch gate.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

Abstract: A switch provided between a first terminal and a second terminal with a varying cross terminal voltage. The switch contains two transistors, with the source terminal of the first transistor being coupled to the first terminal and a drain terminal of the second transistor being coupled to the second terminal. The gate terminal of the first transistor is coupled to the first terminal, the gate terminal of the second transistor is coupled to the second terminal, and the drain terminal of the first transistor is coupled to the source terminal of the second transistor. Due to such a topology, the cross-terminal voltage across the first and second terminals can be substantially higher than the voltage of the control signal indicating whether the switch is to be in on or off state.

Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.

Abstract: A switching circuit is disclosed. The switching circuit is provided with first and second signal terminals, a control terminal, first and second resisters, and a field-effect transistor having a drain, a source, a gate and a back-gate. One end of the first resister is connected with the control terminal. The field-effect transistor is connected between the first and second signal terminals. The gate of the field-effect transistor is connected with the other end of the first resister. The back-gate of the field-effect transistor is connected with one end of the second resister. One of the source and drain of the first field-effect transistor is connected with the other end of the second resister.

Abstract: A multi-gate field effect transistor power switch is used to selectively couple a circuit to a supply voltage. In various embodiments, both n and p-type multi-gate field effect transistor power switches may be used to couple sub-circuits of varying granularity to different voltage supplies.

Abstract: Disclosed is a method of controlling a High Electron Mobility Transistor (HEMT) through a cascode circuit, the cascode circuit including first and second switches, a capacitor connected to a source of the first switch, a source of the HEMT being connected to the drain of the first switch, and a controller for controlling the first and second switches. The method is achieved by defining state A, where the first switch is controlled to be OFF resulting in the HEMT being OFF and the second switch is controlled to be ON allowing the capacitor to be charged and stabilizing the drain voltage of the HEMT at around the HEMT gate threshold voltage. The method further defines state B, where the first switch is controlled to be ON resulting in the HEMT being ON and the second switch is controlled to be OFF almost all the time, thereby preserving the charge stored in the capacitor.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.

Abstract: Two FET transistors provide an electrical circuit characterized by a stable capacitance across a wide range of input voltages and temperture fluctuations. Additionally, the transistors provide a capacitive compensation circuit which stabilizes the output voltage of a band-gap reference circuit. The compensation circuit encompasses the electrical connecting of a PFET capacitor across the terminals of an NFET capacitor (preferably a low threshold voltage NFET), wherein the gate of the of the NFET capacitor is directly connected to an input lead, the substrate is grounded, and the source and drain are directly connected to a common output lead. The PFET is also directly connected to the the input lead and the output lead, however, instead of the substrate being grounded, the substrate of the PFET is electrically connected to the common output lead.

Abstract: A solid-state switching element that works with at least one semiconductor region or a pair of antiserially arranged semiconductor regions having characteristic curves similar to those of FETs. An internal body diode in inverse operation is also provided. In addition to having a drain and a gate, each of the semiconductor regions has two source electrodes, with several cells combined with the electrodes in cell design. One source serves as a load current electrode, called a load source, and the other source is available as a gate electrode, called a control source. The effective semiconductor region of the load source is larger than the effective semiconductor region of the control source.

Abstract: A semiconductor circuit which realizes a read-only memory cell having zero stand-by power consumption and capable of non-volatile storage of multiple-valued or analog data. This semiconductor device is comprises of at least a single-channel or p-channel MOS transistor in a source-follower circuit configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A power integrated circuit is pin-compatible with a three-terminal power MOSFET and contains integrated circuits to turn off the device in the event of an overcurrent or an over-temperature condition. Control power voltage V.sub.cc is applied through a first MOSFET connected between the gate pin and the gate electrode of the power device. A second control MOSFET is connected across the power device gate and source electrodes. The first control MOSFET is turned off and the second control MOSFET is turned on in response to a fault condition. The turn off of the first MOSFET limits the current sinked by the gate pin. A novel boot strap circuit is disclosed which permits the use of all N channel MOSFETs with an N channel power device, and a novel trimmable temperature shutdown circuit is provided. An integrated bipolar transistor is also integrated into the chip to prevent conduction of the P well/N epi diode formed in the device substrate.