Abstract: A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

Abstract: A high frequency detection circuit detects information about a first high frequency power in a high frequency power source device supplying the first high frequency power having a first frequency and a second high frequency power having a second frequency lower than the first frequency to a load. A third high frequency signal that is a mixed signal of a first high frequency signal having the first frequency and a second high frequency signal having the second frequency is detected by a directional coupler. The third high frequency signal is converted to a fourth high frequency signal having a third frequency between the first and second frequencies using a heterodyne system. A progressive wave power of the first frequency is detected based on the fourth high frequency signal.

Abstract: An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

Abstract: The invention relates to signal conversion devices to be used for the receiving radio devices. The attained technical result is the detection and conversion of signals in an electrical two-terminal device, a data loss level being minimal.

Abstract: The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.

Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.

Abstract: A high frequency detection circuit in accordance with the present invention detects information about a first high frequency power in a high frequency power source device supplying the first high frequency power having a first frequency (t) and a second high frequency power having a second frequency (f1) lower than the first frequency (f) to a load (7). A third high frequency signal (V1) that is a mixed signal of a first high frequency signal having the first frequency (f) and a second high frequency signal having the second frequency (f1) is detected by a directional coupler (12). The third high frequency signal (V1) is converted to a fourth high frequency signal (V1′) having a third frequency (&Dgr;f) between the first and second frequencies (f, f1) using a heterodyne system. A progressive wave power (Pf) of the first frequency (f) is detected based on the fourth high frequency signal (V1′).

Abstract: A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.

Abstract: A clock interruption detection circuit comprises a frequency divider circuit for outputting a plurality of frequency divided clocks by dividing an input clock with different division values, an AND circuit for ANDing the input clock and the plurality of frequency divided clocks, an inverter for inverting one of the frequency divided clocks with the largest division value, another AND circuit for ANDing the input clock, the rest of the frequency divided clocks and the output of the inverter, a first and a second switch with a control terminal supplied with the output of each of the AND circuits for controlling the on/off of a discharge path of a first and a second capacitor, a first and a second waveform-shaping buffer circuit supplied with a terminal voltage of the first and the second capacitor, and a selection circuit for selecting one of the outputs of the first and second waveform-shaping buffer circuits in accordance with a selection control signal obtained by delaying the output of the inverter by a pre

Abstract: What is disclosed is a system and method of generating a random frequency. First a fundamental noise signal from a fundamental noise source is detected. Then the fundamental noise signal is amplified. The amplified fundamental noise signal is then mixed with an oscillator signal. For one embodiment, the system is carried out in a single integrated circuit.

Abstract: The present invention provides a method and/or circuit for achieving a near 50 percent duty cycle divide-by-odd-integer output of an input reference clock.

Abstract: A clock monitoring circuit is disclosed for detecting that the period of a clock signal has become shorter than a predetermined time interval. The clock monitoring monitoring circuit comprises a first and second flip-flop circuits that are D-type flip-flops, a delay circuit, and a gate circuit. The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time interval by the delay circuit and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay circuit is set to be equal to the previously described predetermined period. The gate circuit receives the output signals of the first and second flip-flop circuits, and provides a signal whose logic level when the period of the received clock signal is the predetermined period differs from that when it is shorter than the predetermined period.

Abstract: A three state phase frequency lock detector (14) is provided which monitors the UP and DOWN phase pulses generated by a three state phase frequency detector (PFD). The lock detector (14) asserts the lock detect signal when the rising edges of the UP and DOWN phase pulses are phase aligned and un-asserts the lock detect signal for all other relative phases of the UP and DOWN phase pulses. Lock detector (14) is capable of reporting the lock detect signal for each cycle of the UP and DOWN pulses.

Abstract: A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a phase detector for detecting the phase difference between the sampling clock signal and the synchronous signal to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal to generate a correction signal, a micro-controller for generating the delay data and for increasing or decreasing the frequency divisional value of the sampling clock generator to adjust the frequency of the sampling clock signal in response to the correction signal, and an analog to digital converter for converting an analog video signal into corresponding digital video signal in response to the sampling clock signal.

Abstract: Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts the number of pulses of the clock CLK1A based on the clock CLK2B and outputs an error signal ERR1. The clock comparator (16) counts the number of pulses of the clock CLK2B based on the clock CLK1B and outputs an error signal ERR2. An abnormal clock is detected by examining states of the error signals ERR1 and ERR2.

Abstract: An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.

Abstract: The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high frequency filter is in operation. If operating, a status register is set which a microcontroller can poll to determine if an attack has been attempted. A microcode programmer can then control what sequence of events occur once the register has been set. Alternatively, detection of operation of the high frequency filter could automatically trigger a reset or interrupt of the microcontroller.

Abstract: By applying a modification considering a frequency difference to a phase error signal, phase lock is established in a short period of time even when there is a frequency difference. A jump detector detects a discontinuous jump of the phase error signal which occurs when there is a frequency difference, and a state transition is caused in a state storage device in accordance with the resulting detection signal. A holding device corrects the phase error signal in accordance with the state stored in the state storage device and outputs the thus corrected phase error signal as a frequency-phase error signal.

Abstract: An inverse modulator 21, a Fourier transform circuit 22 and a power converter 23 are provided for obtaining a power-frequency spectrum of the carrier wave of a received signal, which is subjected to the influence of fading in the transmission line. A peak detector obtains a peak power level from the power-frequency spectrum and also obtains a peak power level frequency corresponding to the peak power level. A first and a second lower power level frequency detector 25 and 26 receive the power-frequency spectrum, the peak power level and the peak power level frequency. The first lower power level frequency detector detects a frequency which is higher than the peak power level frequency and corresponds to a power level lower than the peak power level by 120 dB, as a first lower power level frequency.

Abstract: The present invention relates to the automatic frequency control circuit and the method of automatic frequency control. The automatic frequency control circuit for processing frequency control of a received signal frequency based on an incoming received signal comprises a first control circuit for processing frequency control based on a precision counter by using the incoming received signal and a second control circuit for processing frequency control based on a coarse counter by using the incoming received signal, wherein the first control circuit and the second control circuit are configured to be used interchangeably in response to the incoming received signal. By employing the circuit which directly counts the received signal and the circuit which counts the regenerative carrier signal in combination, the follow up range of the automatic frequency control circuit is thus expanded.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Abstract: An over frequency detection circuit which is based on the concept of a critical path in a design to protect an IC chip from running at a rate which will produce unpredictable results. The over frequency detection circuit will compare the output of a critical path generation circuit with that of a known path generation circuit. The known path generation circuit must have a delay which is guaranteed to be much shorter than the delay of the critical path generation circuit. If the output of the critical path generation circuit is not the same as the output of the known path generation circuit, then the critical path generation circuit has begun to fail and the IC chip should be disabled.

Abstract: A frequency detecting circuit is provided that includes a level shift detecting unit for generating pulse signals of a certain pulse width at each level shifting of input clock signals and a level detecting unit. The level detecting unit includes a charging unit and a discharging unit. The discharging unit is activated by the pulse signals of the level shift detecting unit to discharge the charges of the charging unit. An inverter having a logic threshold voltage receives electrical signals in accordance with the charged level of the charging unit to output a signal indicative of the frequency of the input clock signals.

Abstract: A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: For testing a frequency divider, oscillations are produced and wave-shaped into a series of dock pulses. The dock pulses are supplied to a frequency divider under test. A window pulse of duration equal to one cycle of the output pulses of the frequency divider is used to sample the clock pulses. The sampled clock pulses are counted and compared with a reference value. Depending on the number of the sampled clock pulses relative to the reference value, an output voltage at one of two discrete values is produced to indicate the result of the test.

Abstract: In a bandpass filter, a first cyclical analogue signal V3 at a center frequency divided by integer N in divide 44 and the divided signal supplied to a digital filter 48 as its system clock; a second cyclical analogue signal at a frequency, to be measured, differing by a small amount from the center frequency, is delayed by N cycles by a dynamic store 54; a substractor 56 subtracts the second signal from the delayed second signal and supplies any difference to the digital filter 48; the output of the digital filter is related to the frequency of the second signal, but the center frequency is suppressed. The filter may be used in an interrogation for an electronic detection system in which an interrogation signal is modified in frequency by a small amount, characteristic of a device to be detected.

Abstract: By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The carrier recovery circuit is constituted such that a phase synchronous circuit constituted by a PLL is controlled by a signal obtained by removing a sign component from an input carrier wave.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.

Abstract: A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.

Abstract: A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted.

Abstract: A frequency detector in a phase locked loop which generates a clock signal for reproducing a signal from a optical disc. 3 T information corresponding to an upper limit of the frequency of the Eight-to-Fourteen Modulation signal is compared with the oscillation clock of the VCO divided by three to reduce the oscillation frequency of the VCO. Additionally, 11 T information corresponding to a lower limit of the frequency of the Eight-to-Fourteen Modulation signal is compared with the oscillation clock of the VCO divided by eleven to increase the oscillation frequency of the VCO thereby providing a VCO which oscillates at a frequency corresponding to the frequency of the Eight-to-Fourteen Modulation signal.

Abstract: This invention provides a frequency estimating circuit in which estimating a frequency offset distributed outside the observation range based on the frequency of a received pilot signal degenerated into the observation range. The frequency estimating circuit comprises a time-axis to frequency-axis converter circuit for converting an input data stream constructed of a sampled quantized received pilot signal into a signal on a frequency axis to determine a power spectrum, and an MAX search circuit for searching for the maximum value of the power spectrum to determine the frequency f.sub.1 corresponding to the maximum value of the power spectrum, and a frequency computing circuit for computing candidates of a frequency offset distributed outside the observation range baaed on the frequency f.sub.1 and for outputting them as frequency information f.sub.EST.

Abstract: A driver for a power transistor (a MOSFET or IGBT) uses a transformer to isolate the power supply from the control signal, but uses very low power components on the isolated side to allow use of a physically small transformer. The control signal is one of two frequencies, and the isolated side of the driver includes a circuit for detecting which of the two frequencies is present. One frequency is preferably twice as much as the other. The output of the frequency detection circuit switches between low and high states depending on the frequency present, and the output of this circuit is connected to the input of a transistor driver circuit which charges the gate of the power transistor.

Abstract: The invention relates to a device for identifying a predetermined sequence of signals arriving on a modem, the sequence having a frequency spectrum of two determined frequencies, the device including a notch filter, associated with a first magnitude calculator having an output sent on a first input of a comparator, a second input of the comparator receiving the output of a second magnitude calculator, the input of which directly receives the signals received by the modem.

Abstract: A phase detection circuit detects a phase relationship between a first clock signal, characterized by transitions of a given polarity (e.g., rising edges) at a first frequency, and a second clock signal, characterized by transitions of the given polarity at a second frequency that is an integer multiple of the first frequency. Transition indication circuitry generates a transition indication signal responsive to transitions, of the given polarity, of the second clock signal. The transition indication signal includes a transition indication (e.g., a pulse) corresponding to each n.sup.th transition, of the given polarity, of the second clock signal and at a phase that is selectable relative to the first clock signal in response to a transition indication control signal. Sampling circuitry (e.g., one or more latches) samples the transition indication signal responsive to each transition, of the given polarity, of the first clock signal to generate a transition indication sample.

Abstract: A telephone answering device (TAD) includes a remote access mode which is operative responsive to dual tone multi-frequency (DTMF) signals. At least three bandpass filters each receive an input signal from a telephone line interface provided in the TAD. A software controlled sampling section receives outputs from all the bandpass filters for sampling outputs from the bandpass filters, the sampling section including a multiplexer which receives the outputs from all of the bandpass filters, and a peak hold circuit coupled to an output of the multiplexer. An analog-to-digital converter receives an output from the peak hold circuit, and a digital controller receives the output of the analog-to-digital converter for controlling operations of the TAD in a remote access mode responsive to the detected DTMF signals. First and second ones of the bandpass filters have respective center frequencies corresponding to frequencies of respective DTMF signals and a third bandpass filter has a different center frequency.

Abstract: A voltage converting circuit of the charge pump step-up type includes a first circuit means for charging each of first and second capacitors with the voltage of a voltage source at a first timing. A second circuit operates to serially connect the charged first capacitor between a positive electrode of the voltage source and a positive voltage output terminal at a second timing so that a positive voltage which is a double of the voltage source voltage, is supplied from positive voltage output terminal. A third circuit operates to the charged first and second capacitors in series between a ground terminal and a negative voltage output terminal at a third timing so that a negative voltage which is a double of the voltage source voltage, is supplied from the negative voltage output terminal.

Abstract: The present invention relates to a low frequency discriminator circuit comprised if apparatus for providing a rectangular wave input signal, apparatus for integrating the input signal, apparatus for detecting whether the integrated input signal falls between upper and lower thresholds respectively, and apparatus for providing an output signal indicating when the integrated input signal falls between the thresholds, whereby the frequency of the input signal may be determined to be between higher and lower limits.

Abstract: A method for optically powering and controlling a hydraulic actuator in which the electrohydraulic servo valve is powered and controlled by a solar cell, with incident light at optimum level, but frequency-modulated at low amplitude, allowing optimum impedance matching to the servo valve solenoids. The signal is F.M. detected using a discriminator, which outputs are applied to the bases of two transistors in series with the electrohydraulic servo valve solenoids. The nearly constant output impedance of the solar cell or a follow-up amplifier allows optimum performance of the discriminator. The unique feature is the operation of the solar cell at a light level which is optimum for efficiency of the system.

Abstract: This detector provides a computationally simple digital low power detector of symbol rate, also called baud rate. It uses an approximate Hilbert transform function to create approximate in-phase and quadrature signals. An approximate envelope detector (feature extractor) processes these signals to produce a signal with a strong frequency component at the symbol rate. This signal is then filtered, accumulated, and threshold detected. The approximate in-phase and quadrature signals are formed by a linear sequence of six delay elements, the output of the third delay element being the in-phase signal. A first summer receives the output of the second delay element at a minus input and the output of the fourth delay element at a plus input. A second summer receives the signal input at a minus input and the output of the sixth delay element at a plus input, and drives a right two bit shifter.

Abstract: A frequency monitor and error detector circuit that processes an input ac signal to be monitored, comparing the input ac signal with an internally generated reference center frequency, and outputting a "Go/No-Go" signal indicating whether the monitored ac signal frequency is within a pre-selected tolerance band or is out of tolerance. The reference frequency is provided by a highly accurate crystal oscillator. An adjustable delay circuit is provided, capable of being adjusted to produce a frequency tolerance band of from +/-0.05% to 0.1% of the center frequency. The device has three output signals which may be logic high or logic low, and are used for activating illuminated indicators or as frequency signal inputs to other equipment. The device is small in size, accurate and reliable over a wide range of frequencies.

Abstract: A clock control circuit is provided to control the frequency of a microprocessor clock signal and includes a clock management unit which controls the frequency of a timing signal applied to a clock generator and distribution unit, which correspondingly supplies an internal clock signal to a CPU core of the microprocessor. A thermal sensor is integrated with the semiconductor die which forms the microprocessor circuit. An output signal from the thermal sensor is provided to a primary temperature indicator unit and to an auxiliary temperature indicator unit. The primary temperature indicator unit is configured to assert a primary indicator signal when the temperature of the semiconductor die has increased above a first threshold level referred to as the primary threshold level, and the auxiliary temperature indicator unit is configured to assert an auxiliary indicator signal when the temperature of the semiconductor die exceeds yet a second threshold level referred to as the auxiliary threshold level.

Abstract: A frequency demodulation circuit having an improved detection sensitivity is provided by forming an all-pass equalizer in a Quadrature-type demodulator capable of allowing a band covering at least a carrier frequency deviation to pass therethrough. The equalizer comprises a band-pass filter for detecting the frequency deviation of an inputted FM carrier signal, a gain-doubling amplifier and a substractor for performing subtraction between the signal inputted to the band-pass filter and the output of the amplifier. The operation of the circuit is such that a FM carrier signal is supplied to the band-pass filter through a phase shifter and to a phase comparator and the output of the substractor and the FM carrier signal are compared to each other by the phase comparator to thereby obtain a FM demodulated signal.

Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307)is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

Abstract: The state machine with hysteresis provided in the invention includes a current state circuit and a next state control circuit. The current state circuit, in response to a clock signal and a control signal, generates a current state signal and a frequency detection signal. The current state signal has a plurality of bits. The next state control circuit, in response to the current state signal and the input signal, generates the control signal. A hysteresis is observed with regard to the relation of the frequency detection signal with respect to the frequency of the input signal.

Abstract: Two wide dynamic range detection circuits are disclosed, which are capable of detecting low-level desired signals in the presence of nearby strong interfering signals. Each circuit includes an attenuator scheme for attenuating the interfering signal while passing the desired signal. The first attenuator scheme uses a YIG filter in combination with an automatic gate arrangement. The second attenuator scheme uses a two-channel arrangement. The first channel uses a chirp-Z processor to derive a pulse-type transform signal in response to the strong interference signal. The second channel includes a YIG filter followed by a programmable notch filter which is controlled by the interference-signal pulse from the first channel. Following the programmable notch filter in the second channel is a chirp-Z processor followed by a gate arrangement wherein the gates are switched "OFF" under control of the interference-signal pulse from the first channel.

Abstract: A frequency discriminator which generates an output signal characteristically representative of a predetermined frequency spectrum of an input signal, but insensitive to variations in the amplitude and spectral width thereof is disclosed. The frequency discriminator is adaptable for use in a radar receiver clutter tracking loop to improve the filtering of clutter signals from the radar returns by maintaining a measured centroid frequency of the clutter signal spectrum substantially at a desired frequency with a loop response which is invariant to both amplitude and spectral width of the clutter signals. More specifically, the frequency discriminator when included in a clutter tracking loop of a radar receiver discriminates from the clutter spectrum a plurality of frequency signals in accordance with a preselected sequence and computes the amplitudes thereof to generate a corresponding sequence of amplitude signals.

Abstract: A ringing tone signal detecting circuit detects a ringing tone signal from a received signal of the echo canceler type which is supplied from a subscriber line through a hybrid circuit. The ringing tone signal detecting circuit has a sampler for sampling the received signal at a predetermined sampling frequency, a comparator for comparing an output signal from the sampler with a predetermined threshold value and producing a binary digital signal, a plurality of first through nth delay circuits for delaying the binary digital signal from the comparator for 1 through n sampling times, respectively, and a frequency detector for detecting a ringing tone signal from the binary digital signal from the comparator and output signals from the first through nth delay circuits. The circuit has particular use in detecting the ringing tone signals in the 2B1Q signaling code scheme.