Abstract: A test circuit for testing a monitoring circuit includes: a ramp generator configured to generate a ramp signal in response to an activated first control signal; a counter configured to count pulses of a clock signal in response to the activated first control signal; at least one register configured to store an output value of the counter based on a change in at least one output signal generated by the monitoring circuit in response to the ramp signal in a test mode; and a controller configured to generate the first control signal and verify the monitoring circuit based on a ratio of a value stored in the at least one register to a duration during which the first control signal is activated.

Abstract: The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

Abstract: An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, a control terminal that is electrically coupled to the circuit device, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit and sets a potential of the control terminal to an abnormality detection voltage when an abnormal state is detected by the abnormality detection circuit.

Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.

Abstract: The present invention discloses a pulse frequency measurement device and method and a control system, the device including: a hardware counter configured to perform a counting operation on an input pulse sequence to output a counting result; and a processing unit configured to obtain number of pulses from the counting result outputted by the hardware counter and measure a first time period during which the obtained number of pulses occupy, in which the processing unit includes a frequency calculation module configured to calculate a frequency of the input pulse sequence based on the obtained number of pulses and the first time period. According to the invention, it is possible to achieve adaptive pulse frequency measurement and multi-channel sampling for multiple input pulse sequences with a relatively low cost while ensuring the accuracy of the measurement result.

Abstract: A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a variation and transfers the output data to the external data line based on the sensing result.

Abstract: A data lock detection system may include a receiver configured to receive a data signal, a phase detector configured to output a phase detection output signal representative of the data signal with respect to a clock signal, and a lock detector configured to receive the phase detection output signal. The lock detector is configured to determine a presence of a frequency difference between the data signal and the clock signal and output a lock determination output signal that indicates if the data signal is locked or unlocked with the clock signal.

Abstract: Disclosed is a apparatus and method for detecting a cut-off frequency of a pulse signal, the apparatus including an input processor configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor configured to reset the counter at every predetermined (set) period, and a detector configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

Abstract: A calibrated crystal warm-up method that can include determining the number of clock cycles of a crystal clock reference signal from a crystal oscillator occur during a single clock cycle of a low-power oscillator. Further, the determination can occur when the crystal oscillator is warmed up. The method can also include comparing a number of clock cycles of the crystal clock reference signal with a previously determined number of clock cycles of the crystal clock reference signal to indicate whether the crystal oscillator is warmed up. Further, the method can include counting the number of clock cycles of a low-power clock reference signal have occurred up until the time it has been determined that the crystal oscillator has been warmed up.

Abstract: A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration.

Abstract: A circuit, set forth by way of example and not limitation, includes a signal detector operative to detect two types of signals, where the two types of signals include a higher-frequency signal and a lower-frequency signal. The signal detector is operative to detect that a received input signal is one of the two types of signals. An output driver is operative to receive the input signal and to adjust conditioning performed on the input signal to create an output signal for transmission over a communication channel, where the adjustment is based on the detection by the signal detector.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).

Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

Abstract: A lock detector and a clock generator including the same are disclosed. A lock detector includes a counter unit which counts a non-matching section of a first signal and a second signal to provide a count value, the first signal and the second signal being comparison result signals obtained by comparing a phase of a reference signal with a phase of a comparison signal, and a lock detection unit which outputs a lock detection signal based on a result of comparing the count value with the reference value. Accordingly, a lock state of the phase-locked loop can be detected rapidly and exactly.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.

Abstract: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

Abstract: The invention includes a method for transmitting and detecting high speed Ultra Wideband pulses across a wireless interface. The transmitter includes a serializer and pulse generator. The receiver comprises a fixed delay line, multiplier, local serializer (with a sequence matching the transmitter), digital delay lines, low noise amplifier and logic fan-out buffer along with an array of D flip-flop pairs. Each flip-flop pair is enabled, at fixed time increments, to detect signals at a precise time; the timing is controlled by the pseudo-random sequence generated by the local serializer. A local tunable oscillator is controlled by detecting the phase change of the incoming signal and applying compensation to maintain the phase alignment and clock synchronization of the receiver to the clock reference of the transmitter. The invention uses a pair of pulses with a fixed delay and then relies on mixing the two to provide better noise immunity.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: Methods and apparatuses for reducing noise in frequency to digital converters (FDCs). An FDC apparatus includes a first FDC, a second FDC and a combiner. The first and second FDCs are configured to independently sample an input signal according to a sample clock to generate first and second digital signals, each representing the instantaneous frequency of the input signal. The combiner is configured to form a resultant digital signal from the first and second digital signals. The first and second FDCs are designed and combined in the noise-canceling FDC apparatus so that the first and second signals they generate have correlated noise profiles in a frequency range of interest. When combined by the combiner to form the resultant digital signal, the resultant digital signal has a signal power to noise power ratio greater than the signal power to noise power ratios characterizing the first and second digital signals of the individual first and second FDCs.

Abstract: A computer-implemented method, device, and program product for detecting a phase shift between an I data clock and a Q data clock in processing an I data signal or a Q data signal used in quadrature modulation or quadrature demodulation. The method includes: receiving an input of the I data clock and the Q data clock; performing exclusive-ORing (XORing) on the I data clock and the Q data clock; latching a result of the performance of XORing on a phase sampling clock which is asynchronous with the I data clock and the Q data clock; incrementing a first number; incrementing a second number; comparing the incremented first number and the incremented second number and determining, based on a phase determination criterion, a phase shift between the I data clock and the Q data clock; and detecting a phase shift between the I data clock and the Q data clock.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. The counting circuit outputs a digital count signal and an evaluation circuit is coupled to generate a decision signal in response to the digital count signal after an end of the second time interval. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Abstract: A stop of a detection object clock is detected by inverting a signal level of an output signal of a level output unit at a count completion time at a counter unit operated by a detection clock and of which count value is changeable, and by determining whether or not a signal level change passes through a clock detection unit operated by the detection object clock by comparing signal levels of an output signal of a level output unit and an output signal of a clock detection unit.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: A time-differential analog comparator is disclosed. An example apparatus according to aspects of the present invention includes a source of a variable frequency signal having a frequency responsive to an analog input. A counting circuit is coupled to count cycles of the variable frequency signal. The counting circuit is coupled to count in a first direction for a first time interval and is coupled to count in a second direction opposite to the first direction for a second time interval that occurs after an end of the first time interval. An evaluation circuit is coupled to the counting circuit. The evaluation circuit is responsive to the count of the cycles of the variable frequency signal after an end of the second time interval.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

Abstract: A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.

Abstract: A method and a device are described for testing a frequency-modulated clock generator, the device including a cycle counting unit for counting clock cycles of a clock signal of the clock generator in multiple consecutive measuring periods, which are defined, in particular, by a measuring signal having a measuring frequency, and for outputting cycle count values, and including a comparator device for receiving and comparing the cycle count values with each other and for outputting at least one output signal as a function of the comparison. In particular, ascertained maximum and minimum values may be compared with each other.

Abstract: A system for decoding frequency modulated signals includes a glue logic module, a key matrix, and a driver coupled to the key matrix. The glue logic module provides a pre-scaled frequency signal, while the key matrix receives the pre-scaled frequency signal. The driver decodes the pre-scaled frequency signal to generate at least one event update corresponding to a frequency of the pre-scaled frequency signal.

Abstract: Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Abstract: The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.

Abstract: A frequency level detecting method includes counting pulses of a spread-spectrum clock, the spread-spectrum clock having a frequency that is modulated within a frequency range from a minimum frequency to a maximum frequency in a constant modulation period of time, the frequency range being divided into a plurality of sub-ranges each corresponding to one of a plurality of frequency levels; determining at least one to-be-counted value range corresponding to one of the plurality of sub-ranges; judging whether or not the counted pulses fall within one of the at least one to-be-counted value range; and generating a level detection signal if the counted pulses fall within the one of the at least one to-be-counted value range, the level detection signal indicating that a frequency of the spread-spectrum clock falls within one of the plurality of frequency levels that corresponds to one of the plurality of sub-ranges corresponding to the one of the at least one to-be-counted value range.

Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.

Abstract: A clock-detecting circuit, containing at least a microprocessor, a clock circuit, and a zero-cross detecting circuit. The clock circuit is connected to the microprocessor. The input end of the zero-cross detecting circuit is connected to the utility power AC input. The output end of the zero-cross detecting circuit is connected to the input end of the microprocessor. The zero-cross detecting circuit operates to detect zero crossing points of the utility power AC input. The microprocessor operates to count the number of oscillation periods of the clock circuit in a time interval between two adjacent zero crossing points of the utility power AC input and to detect clock precision of the microprocessor according to the counted number. The circuit according to the invention features simple structure and low production cost, and is reliable and easy to be implemented.

Abstract: A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step.

Abstract: A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A frequency and/or phase locked loop architecture that eliminates the loop filter generally required in conventional phase locked loops, and which may be implemented in digital logic, for example, as a field programmable gate array. In one example, a frequency/phase locked loop includes both a frequency comparison component and a phase comparison component to allow locking of an output clock signal to both the frequency and phase of a reference signal.