Abstract: Examples relate to an overvoltage protection circuit for a device interface adapted to convey at least electrical energy. The overvoltage protection circuit includes a first and a second terminal and a normally-on transistor. The normally-on transistor is electrically coupled to the first and second terminal. The overvoltage protection circuit further includes a control circuit configured to switch off the normally-on transistor as a function of at least one of a voltage at the first terminal and a voltage at the second terminal. Further examples relate to a device including an interface and an overvoltage protection circuit. The first terminal of the overvoltage protection circuit is electrically coupled to the interface.

Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.

Abstract: Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

Abstract: In one general aspect, a level-shifting circuit includes a first supply terminal configured to receive a first supply voltage, and a second supply terminal configured to receive a second supply voltage different from the first supply voltage. The level-shifting circuit includes a shifting circuit having electrical connections to an input terminal and an output terminal and configured to, in response to a first voltage at a first node, produce a second voltage at a second node. The shifting circuit is used to shift a first voltage level to a second voltage level. The level-shifting circuit includes a clamping circuit having an electrical connection to the first node where the clamping circuit is configured to limit current at the first node from flowing to a ground.

Abstract: A gate driver circuit includes a first power supply rail providing a first fixed supply voltage; a second power supply rail providing a second fixed supply voltage; a transistor including a gate terminal having a gate voltage; and a gate driver integrated circuit (IC) supplied with the first fixed supply voltage and the second fixed supply voltage, the gate driver IC including an output terminal configured to provide a gate drive voltage at the output terminal in order to drive the transistor between switching states. The gate driver IC includes a first voltage converter configured to modulate an amplitude of the first fixed supply voltage to generate a first modulated supply voltage; and a first switch configured to selectively couple the first fixed supply voltage and the first modulated supply voltage to the output terminal of the gate driver IC in order to regulate the gate drive voltage.

Abstract: A multi-loop voltage regulator with load tracking compensation includes a first closed-loop feedback network configured to receive a supply voltage from a power supply and drive an output voltage that is smaller than the supply voltage to a load. The multi-loop voltage regulator includes a second closed-loop feedback network connected to the first closed-loop feedback network and configured to regulate the output voltage between a first supply voltage rail and a second supply voltage rail for a given load current, in which the second closed-loop feedback network produces a gain that is greater than that of the first closed-loop feedback network. The multi-loop voltage regulator also includes a load tracking compensation circuit configured to detect a load current, and to increase the gain of the second closed-loop feedback network based on a dominant pole in the second closed-loop feedback network being a function of the detected load current.

Abstract: The present disclosure relates to semiconductors and low dropout regulator (LDO) circuits. A LDO circuit may include first and second adjustment pipes and first and second error amplifiers. When an output voltage outputted by the output end of the LDO circuit is smaller than a reference voltage, the first error amplifier controls the first adjustment pipe to be turned on, and the second error amplifier controls the second adjustment pipe to be turned off. Alternative, when the output voltage is greater than the reference voltage, the first error amplifier controls the first adjustment pipe to be turned off, and the second error amplifier controls the second adjustment pipe to be turned on.

Abstract: Certain aspects of the present disclosure generally relate a dual feedback loop regulator. For example, the regulator may include a first amplifier having an output coupled to an output node of the regulator, the output node further coupled to a first feedback path and a second feedback path of the regulator. A first input of a second amplifier may be coupled to the first feedback path and a second input of the second amplifier may be coupled to a reference path. The regulator may also include a transconductance stage having a first transistor and a first current source, the first transistor and the current source coupled to the first feedback path and the second feedback path, and a transimpedance stage coupled to the transconductance stage and an input of the first amplifier.

Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages, and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide band-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

Abstract: A temperature sensor circuit whose output voltage has high precision is provided. The temperature sensor circuit includes a Darlington circuit having bipolar transistors, a constant current circuit, and a current control circuit. Emitter currents of the bipolar transistors are made equal to one another by the constant current circuit. Base currents corresponding to the emitter currents of the respective bipolar transistors are sunk by the current control circuit.

Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.

Abstract: An electrostatic discharge protection circuit includes a metal-oxide semiconductor transistor having a first terminal connected to an input end, and a gate connected to a supply voltage; a first bipolar junction transistor having a first terminal connected to the input end, and a base connected to a second terminal of the metal-oxide semiconductor transistor; a second bipolar junction transistor having a first terminal connected to the input end, a second terminal connected to the supply voltage, and a base connected to the second terminal of the first bipolar junction transistor; a first resistive device having a first end connected to the second terminal of the metal-oxide semiconductor transistor, and a second end connected to the supply voltage; and a second resistive device having a first end connected to the second terminal of the first bipolar junction transistor, and a second end connected to the supply voltage.

Abstract: Semiconductor devices and methods are disclosed wherein a switching element or a current path is coupled to a substrate, and wherein a further element is coupled to said substrate and a control input of said switching element or said current path. Accordingly, in at least one embodiment, a semiconductor device comprises a substrate and a switching element with a control input coupled to the substrate. The semiconductor device includes a compensation element having a control input and an output. The control input of the compensation element is coupled to the substrate and the output of the compensation element is coupled to the control input of the switching element.

Abstract: An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.

Abstract: When a current mirror circuit is composed of transistors that inevitably form a parasitic photodiode between an epitaxial layer and a substrate layer because of structure of an integrated circuit, a photocurrent increases in proportional to an area of the epitaxial layer. Thus, the area of the epitaxial layer is adjusted in accordance with a current ratio of the current mirror, so as to allow the photocurrent to affect equally on both input and output sides of the current mirror circuit, i.e., so as to cancel the photocurrent. With this, in a current mirror circuit provided in an integrated circuit, it is possible to eliminate the influence of the photocurrent, without considerably increasing an element area or taking special measures to shield light.

Abstract: A device for controlling a voltage-controlled switch, including two circuits respectively for setting to the high level and for setting to the low level a control terminal of the voltage-controlled switch, one at least of the circuits including a power transistor capable of connecting the control terminal to a high, respectively low voltage, a bipolar control transistor having its emitter, respectively its collector, connected to the control terminal of the power transistor, the base of the control transistor being likely to receive a control current and a first diode connected between a first predetermined voltage smaller than the high voltage, and the base of the control transistor.

Abstract: A method for reducing charge injection from a field effect transistor switch in a circuit being controlled by a timing signal having an operation cycle with at least a first phase and a second phase. A charge density is changed in at least one layer in a channel in the switch when the timing signal begins its operational cycle and is in the first phase. A depth of the layer is significantly reduced while the timing signal is still in the first phase before a transition of the timing signal from the first phase to the second phase. The timing signal is transitioned from the first phase to the second phase while the layer is significantly reduced.

Abstract: A light emitting element driver composed of two transistors, one ground resistor, one inductance and a single capacitor is arranged to drive an LED with a supplied voltage as low as about 0.92 V. The transistors include an NPN transistor and a PNP transistor, the base of the PNP transistor being connected to the ground resistor and the base of the NPN transistor being connected to the collector of the PNP transistor, with the capacitor being connected between the base of the PNP transistor and the node connecting the collector of the NPN transistor to the inductance and to the LED.

Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.

Abstract: A circuit configuration is provided for stabilizing an operating point of a first transistor having a base, a collector and an emitter connected to a first power supply. A second transistor has a base, a collector coupled to the base of the first transistor and an emitter coupled to the collector of the first transistor. A first resistor is connected to a second electrical energy supply and is also connected to both the collector of the first transistor and the emitter of the second transistor. A current limiting element is connected to the base of the second transistor and the first power supply. A third transistor has a base, an emitter connected to the second power supply and a collector connected to the base of the second transistor. A second resistor is connected to a reference potential and to the base of the third transistor. A third resistor is connected to the base and the collector of the third transistor.

Abstract: Disclosed is a front end circuit involving a transimpedance amplifier that drives a resistor, thereby lowering the input impedance of the circuit by dividing the feedback resistance by the gain of the amplifier. In the front end circuit of the present invention, a first transistor is coupled in series with a resistor, where the received signal is input to a base or gate of the first transistor and the amplified received signal is recovered from a collector or drain of the first transistor such that the first transistor and resistor provide the gain of the front end circuit. A second transistor has an emitter or source coupled to the base or gate of the first transistor. A base or gate of the second transistor is coupled to the collector or drain of the first transistor and a collector or drain of the second transistor is coupled to a power supply rail. The second transistor thus provides the feedback path for the transimpedance amplifier thereby reducing the input impedance of the circuit.

Abstract: A monolithically integrated output stage includes an arrangement for detecting the load current through a power switching transistor and/or an arrangement for detecting the output voltage at a power switching transistor and/or an arrangement for detecting the chip temperature. A switching logic of the monolithically integrated output stage includes at least one output transistor for switching the output transistor on reaching at least one predetermined load current threshold and/or output voltage threshold and/or temperature threshold, where the output transistor supplies a high signal at at least one logic output. The emitter of the output transistor is coupled to the logic output, and a switching device is provided to block the output transistor at a negative collector voltage of the power switching transistor.

Abstract: An inverting hysteretic transistor switch having an input terminal, an output terminal and a ground terminal includes, in some embodiments, a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hyteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

Abstract: A semiconductor device is provided which includes a first unipolar transistor provided in a front stage of the device, second unipolar transistor provided in the front stage, and a bipolar transistor provided in a rear stage of the device. In this semiconductor device, drain and the source of the first unipolar transistor are connected to collector and the base of the bipolar transistor, respectively, and drain and the source of the second unipolar transistor are connected to emitter and base of the bipolar transistor, respectively.

Abstract: An electronic inductor circuit comprises a pair of cascoded Darlington bipolar or MOSFET transistors, configured such that the impedance presented by the collector (drain) of the top transistor of the electronic inductor is increased, relative to the other resistive components in the electronic inductor circuit and DAA. The impedance is increased to a magnitude such that small fluctuations in the collector (drain) impedance do not vary the over-all electronic inductor circuit impedance. Therefore, as heat generated by the circuit causes the impedance of the transistor in the electronic inductor to change, the impedance change does not adversely affect over-all modem circuit performance.

Abstract: An output circuit including an input inverting buffer circuit, and an output transistor circuit controlling a voltage of an output terminal by a current flowing therein. A control terminal of the output transistor is coupled to an output of the buffer circuit and to a current divider. The current divider is controlled by a voltage level of the output terminal and diverts current flowing from the output of the buffer circuit to the output transistor. The output circuit reduces overcurrent that flows at a rise of a voltage level of an output terminal, and thereby prevents a ground voltage level from floating up and noise from occurring.

Abstract: An integratable circuit configuration for stabilizing an operating point of a transistor by negative feedback includes first, second, third and fourth terminals. The fourth terminal is connected to a fixed ground potential, and the first and fourth terminals have a supply voltage source connected therebetween. A first transistor to be stabilized by negative feedback has a collector connected to the second terminal, an emitter connected to the fourth terminal, and a base connected to the third terminal. A second transistor has an emitter connected to the second terminal, a collector connected to the third terminal, and a base. A first resistor is connected between the first terminal and the second terminal. A second resistor is connected between the base of the second transistor and the fourth terminal. A series circuit has at least one first diode and one second diode and is connected between the first terminal and the base of the second transistor.

Abstract: To solve a problem that, as the number of signal sources for outputting peak values decreases, a peak output voltage decreases, and to improve detecting precision, there are provided a plurality of first buffer units ?Q.sub.11 .multidot.Q.sub.21 .multidot.M.sub.31 to Q.sub.13 .multidot.Q.sub.23 .multidot.M.sub.33 !, which are emitter-follower circuits, to each of which a signal is input, a plurality of second buffer units ?Q.sub.31 to Q.sub.33 ! which are respectively connected to the first buffer units and an output unit for outputting the detected peak signal.

Abstract: A write driver, having a pair of head pins for connection to a write head, includes two push-pull buffer circuits connected respectively between first and second pull-up resistors and the control nodes of first and second upper drive transistors. The buffer circuits selectively charge and discharge the inherent capacitances of the upper drive transistors, thereby accelerating their turn on and turn off without diminishing head swing. Moreover, connecting the buffer circuits between the pull-up resistors and the upper transistors effectively isolates, or buffers, the pull-up resistors from the self-inductance voltages of the write head, reducing glitching in the write-head output signal.

Abstract: An inverter circuit, suitably implemented in the feedback loop of a series pass regulator, limits the maximum drive current through an output drive transistor connected to control the regulator's pass transistor. A first current source i1 biases an inverting amplifier that includes a transistor and an output resistor R, which inverts an input signal received from an emitter follower and feeds the inverted signal to an output drive transistor which has its collector connected to the base of the pass transistor. A second current source i2 is connected to allow the inverter's input signal to follow the emitter follower negative. When the follower is cut-off, i2 flows through the output resistor and increases the voltage of the signal fed to the output drive transistor by i2.times.R. The increased voltage establishes a maximum drive current based on i1, i2 and R, which is independent of the betas of the individual transistors.

Abstract: In order to stabilize the idle current and the bandwidth of a Darlington-coupled output stage, the output stage is adapted, within an interval of currents, to continuously increase its current amplification with increasing input current from a first amplification value to a second amplification value.

Abstract: A method and apparatus for implementing DC mode selection in a data access arrangement (DAA). The present invention overcomes the geographic constraints of the prior art by providing a plurality of selectable DC modes. Each of the selectable DC modes may be designed to meet the DC mask specifications of a desired country or region. The apparatus of the present invention may then be utilized in any of the desired countries or regions by selecting the appropriate DC mode. To accommodate several possible DC mask parameters, embodiments of the present invention include selection between a plurality of DC mode voltage levels, selection between current limiting and non-current limiting DC modes, and selection between a plurality of current limit values. Control elements, such as opto-couplers controlled by a microcontroller, are used to perform the selection by enabling and disabling circuit elements or connections. One embodiment provides for temperature compensation of DC current limiting.

Abstract: A bipolar driver circuit includes a primary driver transistor and an independently controlled pre-driver transistor having an emitter connected to the base of the primary driver transistor and a collector connected to the collector of the primary driver transistor. In one embodiment, the collector of the primary driver transistor is connected to the output terminal of the driver circuit for sinking current from a load and, in another embodiment, the emitter of the primary driver transistor is connected to the output terminal of the driver circuit for sourcing current to a load. A first current source is connected to the base of the primary driver transistor and a second current source is connected to the base of the pre-driver transistor. The current sources are commonly controllable by an input signal. Also provided is an inverse conduction prevention circuit for preventing the pre-driver transistor from diverting base current from the primary driver transistor in the sink driver embodiment.

Abstract: An output circuit has a bipolar transistor circuit of a 1st and a 2nd bipolar transistor connected in Darlington configuration. The base of the 1st transistor is supplied with an input signal. The collector of the 2nd transistor is connected to a power supply through a 1st diode. And, a signal is outputted from the emitter of the 2nd transistor. The output circuit also includes a 1st PMOS transistor. The source of the 1st PMOS transistor is connected to the base of the 2nd transistor, its drain being grounded, and its the backgate being connected to the power supply through the 1st diode. The output circuit may further includes a 2nd PMOS transistor having a source and a backgate both connected to the power supply, a drain connected to the base of the 2nd transistor through a second diode, and a gate supplied with an inverting signal of the input signal.

Abstract: A power driving circuit of a thin film transistor liquid crystal display includes Darlington circuits for generating voltages corresponding to the gate driving voltages required in the displays. Analog switching circuits control the application of voltages used to form the Von and Voff driving waveforms, which have driving voltage levels generated from the Darlington circuits. The phasing of the driving waveforms is controlled by a phasing signal which is received by the analog switching circuits. The power driving circuit of the present invention consumes less power than conventional driving circuits.

Abstract: A low drop-out voltage regulator is compensated by providing a compensation capacitor across an output terminal of the regulator and an output lead of an input stage which compares a reference voltage and a voltage derived from a regulated output signal at the output terminal. The output from the input stage is inverted without gain before being provided to an output stage. This inversion allows Miller compensation with the compensation capacitor.

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract: A control circuit for an insulated-gate semiconductor device (IGBT) 1 has a drive circuit 2, which is a series circuit constructed of an npn transistor 3 and a pnp transistor 4, and controls the switching operation of the IGBT 1 in response to an on/off signal 9S from a switching signal source 9. The control circuit includes a switching speed control means 10, a gate potential stabilizing npn transistor 20, and a stable operation extending means 30. The switching speed control means 10 gives predetermined slops to the rise and fall of the on/off signal 9S. The gate potential stabilizing npn transistor 20 is Darlington-connected to the pnp transistor 4 of the drive circuit 2 and has the emitter thereof connected to the source of the IGBT 1. The stable operation extending means 30 generates an on signal to the base of the gate potential stabilizing npn transistor 20 upon sensing a drop in the gate potential of the IGBT 1 to a threshold voltage thereof or less.

Abstract: A power switching circuit includes a power switching NPN transistor (1) having its collector electrode coupled to a reference potential terminal (17) and its emitter electrode coupled to an output terminal (7). A driver circuit (5) is provided having an input coupled to a supply terminal (6) and a driving current output coupled to the base electrode of the power transistor (1). A PNP transistor(4) has its emitter electrode coupled to the output terminal(7), its base electrode coupled to a reference voltage terminal (9) for receiving, in operation, a voltage which is positive relative to the reference potential and its collector electrode coupled to the base electrode of an NPN transistor (2). The NPN transistor (2) has its collector electrode coupled to the collector electrode of the power transistor (1) and its emitter electrode coupled to the base electrode of the power transistor (1).

Abstract: A high voltage switch in which an extended SCR is built in an insulated polysilicon layer for providing a single structure high voltage switch. The high voltage SCR is built by building unit SCRs comprising a cathode, a gate, an anode and a voltage sustaining area. The unit SCRs are built as horizontal linear devices. The unit SCRs can then be combined to form a large SCR by building each unit SCR so that the anode of one SCR is at least partially contiguous with the cathode of the next unit SCR.

Abstract: A low voltage indicator circuit including a self-biased driver circuit. A voltage at the output terminal is used to create a bias voltage to operate the driver when less than a threshold voltage is present on at least one voltage supply line. A transistor for supplying base drive current to the driver has a base coupled to the at least one voltage supply line in one embodiment and to the bias circuit in other embodiments. The transistor in the one embodiment provides base drive current to the driver when voltage on the at least one voltage supply line is less than the voltage on the output terminal by at least a predetermined amount. In other embodiments, the bias circuit may include a FET or resistor coupled between the output terminal and the base of a bias circuit transistor. The bias circuit transistor has a terminal connected to a bias resistor for providing current through the bias resistor when the bias circuit transistor is turned on.

Abstract: In order to drive an MOS field-effect transistor as a voltage interrupter in a DC/DC converter operating on the chopper principle, a suitable circuit arrangement has an input transistor (T1) for current control on the input side with a low voltage change, a downstream phase reversing transistor (T2) and a complementary stage formed from a first and a second further transistor (T3, T4) whose collectors are interconnected. An auxiliary voltage is applied which is raised to the input voltage to be regulated. The complementary stage switches without any overlap by means of different current switching thresholds for the first further transistor (T3) and the phase reversing transistor (T2) which drives the second further transistor (T4). In addition, it switches with a switch-on delay, so that the switched-on duration of an upstream switched-mode regulator chip can be increased to 100%. The internal current consumption of the circuit arrangement is in this case low.

Abstract: An amplifier which performs the function of switching on and off its output signal includes an inverted Darlington circuit made up of an input transistor and an output transistor, a first switching circuit connected across the base and the emitter of the output transistor, and a second switching circuit connected between the emitter of the input transistor and the collector of the output transistor. Amplifier also includes means for opening the first switching circuit and closing the second switching circuit to send out an output signal, and for closing the first switching circuit and opening the second switching circuit to stop the output signal. The input and output transistors may be fabricated using vipolar or MOSFET technology because current of a small magnitude flows through the switching circuits, the switching circuits can be formed from elements that are small in size and which have small parasitic capacitance.

Abstract: A preamplifier for use with currents developed by a photodetecting diode is disclosed wherein the currents are coupled to the base of an NPN transistor connected as a common emitter stage and a feedback resistor is connected by way of a buffer amplifier to the base to provide a standard transimpedance configuration. A control loop monitors the signal level by integrating the output of the buffer amplifier, and upon the detection of large signals the control loop causes a MOSFET in parallel with the feedback resistor to decrease the transimpedance and thereby increase the signal handling capability of the preamplifier. The control loop is also connected to a second MOSFET in parallel with the collector load resistor of said NPN transistor to decrease the effective collector load impedance for large signal levels.

Abstract: A bi-mode circuit for driving an output load selectively couples the output load to a supply voltage source or to a low discharge voltage source such as ground using switches which are controlled by an input buffer in response to an input signal. A high input signal closes a first switch to provide a biasing current to first and second current amplifiers to turn on a first output transistor which couples the output load to the low reference voltage to discharge the output load. Conversely, a low input signal closes a second switch to provide the biasing current to a third current amplifier to turn on a second output transistor which couples the output load to the supply voltage source. When the input signal becomes high, rapid pulldown of a capacitive output load is achieved using a high internal pre-drive current provided by the first and second current amplifiers, in a first mode of operation.

Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on.

Abstract: The circuit for converting unipolar input to bipolar output includes a differential amplifier, first and second feedback resistors; and a peak detector. The negative output of the differential amplifier is fed back to the positive input of the differential amplifier through the first feedback resistor, and the positive output of the differential amplifier is fed back to the negative input of the differential amplifier through the peak detector and the second feedback resistor. A pole of lowest frequency among feedback amplifier circuits forming the circuit for converting unipolar input to bipolar output is to be determined with cut-off frequency of an amplification stage of the differential amplifier.