Abstract: An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

Abstract: According to one embodiment, a memory device includes a first nonvolatile memory die, a second nonvolatile memory die, a controller, and a first temperature sensor and a second temperature sensor incorporated respectively in the first nonvolatile memory die and the second nonvolatile memory die. The controller reads temperatures measured by the first and second temperature sensors, from the first and second nonvolatile memory dies. When at least one of the temperatures read from the first and second nonvolatile memory dies is equal to or higher than a threshold temperature, the controller reduces a frequency of issue of commands to the first and second nonvolatile memory dies or a seed of access to the first and second nonvolatile memory dies.

Abstract: An in-vehicle temperature detection circuit includes a temperature detecting unit including a plurality of individual detecting units, each having a first resistor and a temperature detecting element connected in series between a first conductive path to which a predetermined source voltage is applied and a reference conductive path. A plurality of bipolar transistors are connected to a corresponding individual detecting units. A second conductive path is electrically connected to each of emitters of the bipolar transistors. In each bipolar transistor, a base is electrically connected to a third conductive path between the first resistor and the temperature detecting element of the individual detecting unit corresponding to the bipolar transistor. A voltage reflecting the lowest voltage among the voltages applied to the third conductive paths in the plurality of individual detecting units is applied to the second conductive path.

Abstract: A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction.

Abstract: An acceleration detection device includes a first acceleration acquisition unit configured to acquire a first acceleration from a mechanical acceleration sensor a second acceleration acquisition unit configured to acquire a second acceleration from a non-mechanical acceleration sensor and a correction value calculation unit configured to calculate a correction value for correcting the first acceleration using the second acceleration.

Abstract: Provided are a gain compensation device and a bias circuit device. A compensation bias current is generated by the gain compensation device to compensate the gain deviation of power amplifier and improve stability of power amplifier. Through high-temperature compensation unit and low-temperature compensation unit in different gears, gain of power amplifier is compensated along with temperature changes, thereby improving feasibility of the gain compensation device. It takes small space, and the circuit only includes the circuits corresponding to high-temperature compensation unit and low-temperature compensation unit, so the circuit is relatively simple and beneficial to miniaturization.

Abstract: A virtual, augmented, or mixed reality display system includes a display configured to display virtual, augmented, or mixed reality image data, the display including one or more optical components which introduce optical distortions or aberrations to the image data. The system also includes a display controller configured to provide the image data to the display. The display controller includes memory for storing optical distortion correction information, and one or more processing elements to at least partially correct the image data for the optical distortions or aberrations using the optical distortion correction information.

Abstract: A temperature sensor and a method of controlling the temperature sensor are provided. The temperature sensor includes a voltage generator suitable for generating a temperature voltage that has a voltage level determined according to a temperature and a reference voltage that has a constant voltage level independent of a change in temperature, a code generator suitable for generating an initial code based on the temperature voltage and the reference voltage, and a code calibrator suitable for generating a calibrated code based on the initial code and a calibration factor.

Abstract: An electronic device includes a structured metallization layer including a plurality of contact pads that are electrically isolated from one another, and a metal clip connected in a current shunt measurement arrangement with a semiconductor device, wherein the metal clip includes first, second and third landing pads, a first bridge span connected between the first and second landing pads, and second bridge span connected between the second and third landing pads, wherein the first, second third landing pads are respectively thermally conductively attached to first, second and third contact pads from the structured metallization layer, and wherein the second mounting pad is electrically floating.

Abstract: Circuits, systems, and methods to switch modes based on temperature and to provide reference voltages are discussed herein. For example, a bandgap reference circuit may include one or more impedance elements and one or more switches coupled to the one or more impedance elements. The one or more switches may be controllable based on a temperature signal. The bandgap reference circuit may be configured to provide a bandgap reference voltage that is associated with less than a particular amount of voltage variation.

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

Abstract: A system current sensor module can accurately sense or measure system current flowing through a sense current resistor by shunting current through a gain-setting resistor and using an amplifier to measure a resulting voltage, with an output transistor controlled by the amplifier controlling current through the gain setting resistor in a manner that tends to keep the amplifier inputs at the same voltage. The resistors can be thermally coupled to maintain similar temperatures when a system current is flowing. The thermal coupling can include conducting heat from a first resistor layer carrying the current sense resistor to a thermal cage layer located beyond a second resistor layer carrying the gain-setting resistor. This preserves accuracy, including during aging.

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

Abstract: A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.

Abstract: A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction.

Abstract: In an embodiment a semiconductor device includes a first diode and a second diode of specified sizing or biasing ratio, a negative voltage supply, a first resistor for a proportional to absolute temperature (PTAT) voltage drop, wherein the first diode is connected between the negative supply voltage and the first resistor, an array of dynamically matched current sources employing a dynamic element matching controller, wherein the first resistor is connected between the first diode and a first input of the array, and wherein the second diode is connected between the negative supply voltage and a second input of the array and a successive approximation register (SAR) feedback loop configured to drive a voltage difference to zero, wherein the voltage difference occurs between a first node present between the first resistor and the first input of the array and a second node present between the second diode and the second input of the array.

Abstract: An integrated circuit includes: a resistor terminal adapted to be coupled to a first end of a first resistor; a ground terminal adapted to be coupled to a second end of the first resistor; a second resistor in series with the first resistor and having a first end and a second end, the second end coupled to the resistor terminal; a first capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor terminal is coupled to: the first end of the second resistor via a first switch; and the ground terminal via a second switch; a second capacitor having a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal is coupled to: the first end of the second resistor via a third switch; the resistor terminal via a fourth switch; and the ground terminal via a fifth switch.

Abstract: A compact solid state relay (7) is provided. Solid state devices (74, 75), such as Triacs or Thyristors are used to implement the relay functionality. The device is at least partially enclosed in a housing that has pins for mounting on an electronics board. A number of “U” shaped jumpers (72) or other jumpers or wires are provided in the housing to act as heat sinks. A sub-miniature fan (70) is positioned to create an air flow over the heat sinks and dissipate heat from the device.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: A temperature sensor configured to generate an output signal corresponding to a sensed and/or measured temperature includes: a diode including a cathode coupled to a ground node; a first capacitor including a first end coupled to the ground node; a switch circuit configured to connect a second end of the first capacitor to a positive voltage node or an anode of the diode according to a control signal; switch control circuitry configured to generate the control signal based on a reference voltage with a voltage of the anode; and an output signal generator configured to generate the output signal corresponding to the sensed temperature based on a frequency of the control signal.

Abstract: An on-chip temperature sensor for generating a digital output signal representing a temperature value includes: a proportional to absolute temperature (PTAT) buffer for alternately generating a first voltage signal representing a first temperature of the PTAT buffer and a second voltage signal representing a second temperature of the PTAT buffer; an analog to digital (A/D) converter, coupled to the PTAT buffer, for converting the first voltage signal to a first digital voltage signal and for converting the second voltage signal to a second digital voltage signal; and a digital output generating block, for receiving the first digital voltage signal and the second digital voltage signal, and comparing a difference between the first digital voltage signal and the second digital voltage signal with a digital voltage reference signal to generate the digital output signal.

Abstract: A system includes a controller for a DC to AC inverter including a processor configured to execute instructions to perform operations including: generating a first pulse for a first phase of a center-aligned PWM signal to alternately activate a first phase switch of a first switch group of the inverter for a first duration and a first phase switch of a second switch group of the inverter for a second duration within a period of the PWM signal; and generating a second pulse for a second phase of the PWM signal to alternately activate a second phase switch of the first switch group of the inverter for a third duration and a second phase switch of the second switch group of the inverter for a fourth duration within the period of the PWM signal, wherein the second duration is different from the third duration during a stall condition.

Abstract: A power supply semiconductor integrated circuit includes an output transistor, a control circuit, a first-fault detection circuit, a second-fault detection circuit, a delay circuit, and a latch circuit. The output transistor is connected between a voltage-input terminal to which a DC voltage is input and a voltage-output terminal. The control circuit controls the output transistor. The first-fault detection circuit detects a first fault. The second-fault detection circuit detects a second fault different from the first fault. The delay circuit delays an output of the first-fault detection circuit and an output of the second-fault detection circuit. The latch circuit captures and holds an output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a discharge switch for discharging the delay capacitor; and a voltage comparator circuit that compares a charge voltage across the delay capacitor and a predetermined voltage.

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

Abstract: A semiconductor device is provided, including a plurality of memory chips and a temperature detection module. The temperature detection module includes: a plurality of temperature detection units, in which the plurality of temperature detection units are disposed on at least part of the memory chips to detect the temperatures of at least part of the memory chips; and a processing unit, in which the plurality of temperature detection units share the processing unit with each other, and the processing unit is configured to process a signal of at least one of the temperature detection units.

Abstract: A bandgap circuit is disclosed. The bandgap circuit includes a current source configured to generate, using a bias voltage, a first current and a second current, a first bipolar device configured to sink the first current, and a second bipolar device configured to sink the second current via a bias resistor. The bandgap circuit further includes an amplifier circuit configured to generate the bias voltage using a first voltage drop across the first bipolar device and a second voltage drop across the series combination of the bias resistor and the second bipolar device. A compensation circuit is also included, where the compensation circuit is configured to adjust, based on a value of the bias resistor, a base current of the second bipolar device.

Abstract: A low-power CMOS reference voltage generating with enhanced power supply rejection ratio (PSRR) and fast start-up time is disclosed. The reference voltage generating is generated by the stacked diode-connected MOS transistors (SDMT) architecture to reduce the dependence on process, voltage and temperature. The self-biased and capacitor coupled architecture can shorten the start-up time without increasing power consumption and improve the bandwidth of the power supply rejection ratio. This design is implemented using a CMOS process, which can achieve stabilization time of 0.2 ms. Under the same power consumption, this design is 274 times better than a design without a start-up time enhancement. The power supply rejection ratio measured at 100 Hz is ?73.5 dB. In the temperature range of ?40 to 130° C., the average temperature coefficient is 62 ppm/° C.

Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.

Abstract: A system current sensor module can accurately sense or measure system current flowing through a sense current resistor by shunting current through a gain-setting resistor and using an amplifier to measure a resulting voltage, with an output transistor controlled by the amplifier controlling current through the gain setting resistor in a manner that tends to keep the amplifier inputs at the same voltage. The resistors can be thermally coupled to maintain similar temperatures when a system current is flowing. The thermal coupling can include conducting heat from a first resistor layer carrying the current sense resistor to a thermal cage layer located beyond a second resistor layer carrying the gain-setting resistor. This preserves accuracy, including during aging.

Abstract: A lighting apparatus includes a driver, a metal plate, a light source module and a conductor unit. The driver receives an alternating current power source and converts the alternating current power source to a driving current. The metal plate is electrically connected to a ground. The light source module has a substrate and multiple LED modules. The multiple LED modules are mounted on the substrate. The substrate is disposed upon the metal plate. The conductor unit has a first end connected to the substrate of the light source module and a second end connected to the metal plate for removing a parasitic capacitance between the substrate of the light source and the metal plate for preventing a noise occurred when the LED module is turned on and the metal plate is connected to the ground.

Abstract: With regard to an instrument wherein a plurality of phase operations are carried out, the type of failure or the phase in which the failure has occurred is determined and, in accordance with the result of the determination, an alarm signal is generated. Provided that the failure details and the phase in which the failure has occurred can be determined from the generated alarm signal, it is possible, using a configuration wherein an alarm signal having a pulse number corresponding to the phase in which a failure has occurred is generated, or a configuration wherein an alarm signal having a pulse width corresponding to the phase in which a failure has occurred is generated, to determine the type of failure that has occurred and the phase in which the failure has occurred from the pulse number and pulse width.

Abstract: A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction.

Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.

Abstract: Embodiments of the present invention relate to a method for controlling temperature of a terminal, including: receiving, by the terminal, an instruction for triggering execution of a first task; obtaining, by the terminal, a current temperature of the terminal; and controlling, by the terminal, an execution manner of the first task based on the current temperature, to control temperature of the terminal. When the terminal obtains the current temperature of the terminal, the terminal may control, based on the current temperature of the terminal, the first task to be executed in different manners, so as to control temperature of the terminal and ensure that the mobile phone is in a safe state.

Abstract: A power-on reset circuit includes a complementary-to-absolute-temperature circuit that outputs one control voltage, and a proportional-to-absolute-temperature (PTAT) circuit that outputs a PTAT current. The power-on reset circuit further includes various resistors that are coupled in series, and generate another control voltage based on the PTAT current that is outputted by the PTAT circuit. Further, the power-on reset circuit includes a comparator that compares the two control voltages to generate a power-on reset signal. The power-on reset signal is activated when a supply voltage is greater than or equal to a trip voltage, and deactivated when the supply voltage is less than the trip voltage. A functional circuit is configured to execute a reset operation associated therewith when the power-on reset signal transitions from a deactivated state to an activated state.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: Systems, methods and devices are described related to remote temperature sensing. In one embodiment, fractional currents are used to bias a remote temperature diode. Such fractional currents may be selected to simplify at least some temperature calculations performed using digital logic.

Abstract: A temperature measuring device includes first and second semiconductor elements each of which has a p-n junction, a transistor group including a plurality of transistors of which respective sources are connected to a power source and of which respective gates are connected to each other, the plurality of transistors constituting a current source, the transistor group being configured to output a first current and a second current having a different magnitude from the first current to the first and second semiconductor elements, respectively, and a selector configured to select at least one first transistor and a plurality of second transistors different from the first transistor, from among the plurality of transistors.

Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Abstract: An object of the present invention is to stop the driving of a semiconductor element swiftly at a time of abnormality while sharing an output terminal between temperature information and an error signal in an IPM. In the intelligent power module of the present invention, each drive circuit includes an output control circuit configured to select the error signal while the error signal generation circuit outputs the error signal, to select the temperature signal while the error signal generation circuit does not output the error signal, and to output a selected signal as an alarm signal. The temperature signal generation circuit is configured to change the voltage value of the temperature signal in accordance with the element temperature of the specific semiconductor element within a voltage range different from the voltage value of the error signal.

Abstract: A temperature detection device includes: first and second temperature sensors that output temperature signals that are signals corresponding to measured temperatures; a signal conversion circuit that respectively converts the temperature signals, which are output from the first and second temperature sensors, into pulse signals having duty ratios or frequencies corresponding thereto; a multiplexer that selectively outputs one of a plurality of the pulse signals converted by the signal conversion circuit; and an offset unit that offsets the temperature signal, which is output from the first temperature sensor of the first and second temperature sensors, to the signal conversion circuit.

Abstract: A Proportional-To-Absolute-Temperature (PTAT) current source is used for high-resolution temperature measurement. The PTAT current source is coupled to a capacitor for a fixed amount of time so as to charge the capacitor to a voltage which is proportional to the current applied to the capacitor, and thus proportional to the temperature. The voltage on the capacitor is measured, and a temperature is calculated or determined from the measured voltage.

Abstract: Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

Abstract: A sensor circuit includes a bandgap reference circuit (BGREF) that produces two outputs, a temperature dependent output and a reference voltage, which does not change with temperature. The temperature dependent output includes a PTAT (proportional to absolute temperature, rising with increased temperature) portion and a CTAT (complementary to absolute temperature, falling with increased temperature) portion. Circuitry is provided that calculates the reference voltage by adding the PTAT portion and a divided version of the CTAT portion in which the CTAT portion has been divided by a divisor.

Abstract: The circuit device includes a current generation circuit and a current-voltage conversion circuit. The current generation circuit generates a temperature compensation current based on a temperature detection voltage from the temperature sensor and temperature compensation data. The current-voltage conversion circuit converts the temperature compensation current into the temperature compensation voltage. The current generation circuit performs a fine adjustment of the temperature compensation current based on lower bits of the temperature compensation data, and performs a coarse adjustment of the temperature compensation current based on higher bits of the temperature compensation data.

Abstract: A method of operating a semiconductor device can include providing a multi-bit count value to a temperature sensing circuit; and generating an output having a detect logic level from the temperature sensing circuit based on an internal temperature of the semiconductor device and the count value. In some embodiments, a semiconductor device can be a dynamic random access memory (DRAM) device.

Abstract: A temperature sensor and a method of sensing a temperature are provided. The temperature sensor generates a temperature clock signal based on a control signal to adjust a nonlinearity of the temperature clock signal, and outputs a count signal by counting clocks of the temperature clock signal corresponding to a counting interval of a reference clock signal.

Abstract: The invention proposes a method for the flame signal detection by means of an ionization electrode (15) protruding into a combustion zone of a burner, comprising the steps: detecting a first signal, which is dependent on an ionization current flowing off the ionization electrode (15), generating a second signal which has a predetermined periodic course, generating a third signal by adding the first signal and the second signal, comparing the third signal with a first threshold value and generating a fourth signal on the basis of the comparison of the third signal with the first threshold value, comparing the third signal with a second threshold value different from the first threshold value and generating a fourth signal on the basis of the comparison of the third signal with the second threshold value, and determining an operating variable of the burner on the basis of at least one of the fourth signal and the fifth signal.

Abstract: A differential voltage measurement device includes a first capacitor, a second capacitor of which the capacity is smaller than that of the first capacitor, a differential amplification unit which outputs a voltage according to a differential voltage between a voltage held in the first capacitor and a voltage held in the second capacitor, and a control unit which guides a first voltage to the first capacitor and guides a second voltage to the second capacitor in a state where the first capacitor holds the first voltage.