Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

Abstract: Various embodiments of the present technology comprise a method and apparatus for a continuous time linear equalizer (CTLE). In various embodiments, the CTLE comprises a cross-coupled transistor pair that operates as a negative impedance converter. The CTLE produces a transfer function that provides high gain peaking at a high frequency without increasing the size of the die area and/or the power supply level.

Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.

Abstract: A current monitoring circuit includes: an output terminal configured to be coupled to a controller; an inverter having an output coupled to the output terminal; a first transconductance amplifier having first and second inputs configured to be coupled across a sense resistive element, and an output coupled to an input of the inverter; and a current generator having a second transconductance amplifier configured to generate a reference current at an output of the current generator based on a reference voltage, the output of the current generator being coupled to the input of the inverter, where the output of the inverter is configured to be in a first state when a load current flowing through the sense resistive element is higher than a predetermined threshold, and in a second state when the load current is lower than the predetermined threshold, and where the predetermined threshold is based on the reference current.

Abstract: A test system accesses a test script. The test script is to test an application at a target screen resolution. The test system tests the application using the test script, and a current screen resolution of the test system is different from the target screen resolution. In the test, the test system initializes a system web browser to run the application, and in the test, the test system overwrites a size parameter of the system web browser to cause a content window of the system web browser to display application content at the target screen resolution instead of the current screen resolution.

Abstract: The present disclosure provides a comparator, an integrated circuit, and a method.

Abstract: Systems and methods according to one or more embodiments are provided for correcting a current measurement through a speaker in an audio system. In one example, a system for driving a speaker includes an output stage configured to drive a current through the speaker. The system further includes a first and second current sensor coupled to the output stage and configured to measure a positive current including a first measurement error and a negative current including a second measurement error through the speaker, respectively. The system further includes a processing block coupled to the first and second current sensors to receive the measured positive and negative current signals and configured to add a positive offset value to an input of each first and second current sensors, determine the first and second measurement errors, and correct a measured current using the positive and negative currents and the determined first and second measurement errors.

Abstract: Shoot-through condition in a component containing an amplifier with a push-pull output stage is managed. A first current in a first transistor of the output stage is mirrored to generate a first mirrored current. A second current in a second transistor of the output stage is mirrored to generate a second mirrored current. A sum of the first mirrored current and said second mirrored current is generated. When a magnitude of the sum exceeds a first pre-determined threshold, a respective control voltage of the first transistor and the second transistor is adjusted to reduce the first current and the second current at least until the sum falls below a second pre-determined threshold. In an embodiment, the first pre-determined threshold equals the second pre-determined threshold. In an embodiment, the component is a class-L power amplifier.

Abstract: A comparator circuit has a sense amplifier with a differential pair, a voltage excursion limiter, and a switch. The differential pair receives two analog input signals. Its differential outputs operate at a common mode voltage approximately half the supply voltage. The voltage limiter is coupled with one of the differential pair outputs. A capacitor may store comparison results. The switch energizes the differential pair and the voltage excursion limiter during a first phase of a clock, and de-energizes them during a second phase of the clock. During this phase, the comparator may provide the stored comparison result to an amplifier with positive feedback.

Abstract: A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.

Abstract: A circuit includes a first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store a first and a second logic values, respectively. The current sense amplifier is configured to couple the first reference cell to a first node of the current sense amplifier, and couple the second reference cell to a second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell.

Abstract: A resistive memory device includes a resistive memory cell whose resistance value varies based on a logic value of data stored therein, a current amplification block suitable for amplifying a current flowing through the resistive memory cell by N times, where N is a natural number greater than 1, and a sensing block suitable for sensing the data based on the amplified current.

Abstract: A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Abstract: A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and the first resistive memory cell to provide a clamping bias to the first resistive memory cell, a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

Abstract: A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

Abstract: An electronic device can be configured to support a port that connects to a plug or jack such that the face of the port is substantially equal to or greater in size than at least one dimension of the electronic device. The electronic device can then continue to support connections to peripheral devices and other devices having plugs and jacks of various sizes, and the electronic device is not necessarily limited to a certain depth or thickness. This can be achieved by electronic devices that incorporate adaptive or extensible ports that are retracted in one state and extended in a second state to support the plugs or jacks such that the face of the port substantially meets or exceeds at least one dimension of the electronic device. Alternatively, or in addition, other embodiments can incorporate resilient materials for certain portions of the port.

Abstract: Memory apparatuses and methods for low power current mode sense amplification are disclosed. An example memory apparatus may include a current mode sense amplifier and a current circuit. The current mode sense amplifier may be configured to provide an output current. The current circuit may comprise a bias generator that is configured to generate a bias signal as well as a current control circuit coupled to both the current mode sense amplifier and the bias generator. The current control circuit may be configured to receive both the output current and the bias signal and control the output current based, at least in part, on the bias signal.

Abstract: An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto. The output voltage is generated in response to the control signals. A speed of the comparing is increased in response to the mode signals indicating that the output voltage is being increased. The speed is reduced in response to the mode signals indicating that the output voltage is being reduced. For increasing the speed, a path is enabled to conduct current. While the path is enabled, at least one switched voltage is connected to vary an amount of the current conducted through the path. The switched voltage is at least one of the reference voltage and the output voltage. For reducing the speed, the path is disabled against conducting current. While the path is disabled, the switched voltage is disconnected from varying the amount.

Abstract: A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier in a first mode, and couple a cell of the cell segment to the first node of the current sense amplifier, and couple the first and second reference cells to the second node of the current sense amplifier in a second mode.

Abstract: In various embodiments a transmitter circuit may include a first circuit configured to transmit data in a first data transmission mode, a second circuit configured to transmit data in a second data transmission mode and a switching circuit configured to control the first circuit and the second circuit to transmit data in the first data transmission mode or in the second data transmission mode. Further, a corresponding method for operating the transmitter circuit is provided.

Abstract: In various embodiments a transmitter circuit may include a first circuit configured to transmit data in a first data transmission mode, a second circuit configured to transmit data in a second data transmission mode and a switching circuit configured to control the first circuit and the second circuit to transmit data in the first data transmission mode or in the second data transmission mode. Further, a corresponding method for operating the transmitter circuit is provided.

Abstract: A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.

Abstract: A battery switching charger includes a PWM signal generator, a switching circuit, an inductor, a resistor and an analog-to-digital converter. The PWM signal generator is utilized for generating a PWM signal. The switching circuit includes cascoded transistors controlled by the PWM signal for generating an output voltage. The inductor is utilized for receiving the output voltage. The resistor is coupled between the inductor and a charge terminal of the battery switching charger, where the charge terminal is connected to a battery when the battery is being charged by the battery switching charger. The analog-to-digital converter is coupled to the PWM signal generator and the resistor, and is utilized for receiving voltages of two terminals of the resistor to generate control data to the PWM signal generator. In addition, the PWM signal generator adjusts a duty cycle of the PWM signal according to the control data.

Abstract: An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.

Abstract: Provided is a sensor circuit which can amplify a sensor signal at high speed and with a high amplification factor without increasing the current consumption. The sensor circuit includes a primary amplifier for amplifying in advance a differential output signal which is a current signal of a sensor element, a secondary amplifier for amplifying the amplified differential output signal, a constant voltage generating circuit for maintaining a sensor element driving current to be constant, and a feedback circuit for feeding back a feedback signal to adjust an amplification factor. Most of the currents which pass through the primary amplifier are bias currents of the sensor element.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Abstract: A method and device for signal detection is disclosed. At least one detection period is predefined for detecting a signal of a signal source, a differential signal of a pair of signal sources, or a dual-differential signal of three signal sources during at least one clock cycle.

Abstract: Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.

Abstract: Provided is a sensor circuit which can amplify a sensor signal at high speed and with a high amplification factor without increasing the current consumption. The sensor circuit includes a primary amplifier for amplifying in advance a differential output signal which is a current signal of a sensor element, a secondary amplifier for amplifying the amplified differential output signal, a constant voltage generating circuit for maintaining a sensor element driving current to be constant, and a feedback circuit for feeding back a feedback signal to adjust an amplification factor. Most of the currents which pass through the primary amplifier are bias currents of the sensor element.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: The semiconductor device includes: a first transistor controlled by a control signal; a sense voltage generating circuit for sensing current flowing through the first transistor, mirroring current flowing through a reference current circuit, and summing the currents to generate voltage based on the summed currents; a reference voltage circuit for mirroring current flowing through the reference current circuit and generating reference voltage; an amplifier for comparing the voltage generated by the sense voltage generating circuit and the reference voltage; and a second transistor which has a gate connected to an output terminal of the amplifier and which can turn off the first transistor.

Abstract: A semiconductor device configured that its differential pair is made operable in both states of high speed with a high consumption current and low speed with a low consumption current. A differential circuit includes differential pair transistors and a tail current source for supplying a tail current that is switchable so that an amount of current flowing in the differential pair transistors may be switched between at least two sates of different levels. The differential pair transistors have a characteristic that, with a decrease of currents flowing in the differential pair transistors, a value of ?(?I/gm) decreases monotonously, where ? denotes a standard deviation, ?I denotes a difference of the amounts of current of the differential pair transistors, and gm denotes transconductance of the differential pair transistors.

Abstract: A comparator is disclosed. The comparator includes a mirror circuit that is electrically coupled to a first voltage source and a second voltage source. The first voltage source produces a first voltage and the second voltage source produces a second voltage. The comparator also includes a first positive metal oxide semiconductor (PMOS) transistor electrically coupled to the first voltage source and an output terminal. The first PMOS transistor is biased by the mirror circuit. The comparator also includes a first negative metal oxide semiconductor (NMOS) that is electrically coupled to a ground terminal and the output terminal. The first NMOS transistor is also biased by the mirror circuit. An electrical current flowing across the first NMOS transistor is mirrored from an electrical current flowing through the first PMOS transistor. A method to operate the comparator and a comparator system is also disclosed.

Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.

Abstract: The semiconductor device includes: a first transistor controlled by a control signal; a sense voltage generating circuit for sensing current flowing through the first transistor, mirroring current flowing through a reference current circuit, and summing the currents to generate voltage based on the summed currents; a reference voltage circuit for mirroring current flowing through the reference current circuit and generating reference voltage; an amplifier for comparing the voltage generated by the sense voltage generating circuit and the reference voltage; and a second transistor which has a gate connected to an output terminal of the amplifier and which can turn off the first transistor.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

Abstract: A sense amplifier includes a sense input node, a current mirror circuit to mirror the current on the sense input node, and a result output node. A current source supplies an offset current. The sense amplifier increases the current on the sense input node by the offset current and reduces the offset current from the mirrored current at the result output node.

Abstract: A system to interface analog-to-digital converters to inputs with arbitrary common-modes includes a common-mode voltage amplifier circuit and a PGA circuit connected to the common-mode voltage amplifier circuit. The common-mode voltage amplifier and PGA circuits receive first and second analog input signals. The PGA circuit eliminates the arbitrary common-modes from the first and second analog input signals based on an output of the common-mode voltage amplifier circuit.

Abstract: A comparator includes: a pre-amplification module, configured to generate two amplified differential signal reference currents according to an input voltage and a reference voltage; and a differential signal obtaining module, configured to obtain a differential signal according to the two amplified differential signal reference currents. The pre-amplification module includes a differential unit, an offset unit, and an amplification unit, where the differential unit is configured to generate two direct current bias currents according to the input voltage and the reference voltage; the offset unit is configured to generate an offset current of the two direct current bias currents according to the input voltage and the reference voltage, so as to reduce magnitude of the two direct current bias currents and obtain two differential signal reference currents; the amplification unit is configured to receive the two differential signal reference currents, and amplify the two differential signal reference currents.

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

Abstract: A circuit includes a first resistor, a second resistor, a voltage follower and a current mirror. The first resistor converts a current flowing through the first resistor to a voltage drop between positive and negative sides of the first resistor. The second resistor is coupled to the negative side of the first resistor. The voltage follower is coupled to the positive side of the first resistor via a non-inverting terminal, and coupled to the negative side of the first resistor through the second resistor via an inverting terminal to cause a voltage at the inverting terminal to follow a voltage at the non-inverting terminal. The current mirror is coupled to the voltage follower to provide a sensing current proportional to the current flowing through the first resistor.

Abstract: A sense amplifier may be operable to form a current-mirror reference using a first PMOS transistor and a NMOS transistor. Currents at a first internal terminal and a second internal terminal may be generated based on the current-mirror reference. Voltage signals at the first internal terminal and the second internal terminal may be generated based on received differential input signals and the currents at the first internal terminal and the second internal terminal. The sense amplifier may limit voltage excursions of the voltage signals at the first internal terminal and/or of the second internal terminal using a pair of cross coupled PMOS transistors, respectively. Voltage signals at a third internal terminal and a fourth internal terminal may be generated based on voltage signals at the first internal terminal and the second internal terminal. An output signal may be generated based on the voltage signal at the fourth internal terminal.

Abstract: The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.

Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.