With Sensing Amplifier Patents (Class 327/51)
  • Patent number: 11988785
    Abstract: The present invention relates to photon counting. In particular, a photon-counting data acquisition module is provided. The photon-counting data acquisition module comprises a signal input unit and one or more data acquisition channels, each channel adapted for converting at least one train of pulses received from the signal input unit to a counter signal. Each data acquisition channel comprises a pulse maximum identifier and a discriminator/counter pair comprising a discriminator and a counter. The pulse maximum identifier is configured to identify a maximum of a pulse in the at least one received train of pulses. The discriminator is configured to be triggered, by a detection of a maximum of a pulse in the at least one received train of pulses, to compare the pulse with at least one signal threshold to generate the counter signal. Alternatively, the counter is configured to be enabled in response to a detection of a maximum of a pulse to generate the counter signal.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: May 21, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Roger Steadman Booker, Christoph Herrmann
  • Patent number: 11962331
    Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Patent number: 11923673
    Abstract: A semiconductor device includes: a switching device including a main portion and a current sensing portion for detecting a current value of the main portion; a control IC including a gate drive unit that drives the switching device; a sensing resistor connected between an emitter of the main portion and an emitter of the current sensing portion and formed inside the control IC; a comparator comparing a sense voltage applied to the sensing resistor with a reference voltage; and a shut-down circuit shutting down an energization of the switching device when the sense voltage exceeds the reference voltage, wherein the sense voltage is more than or equal to 1 V when the energization of the switching device is shut down.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: March 5, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keisuke Eguchi, Takamasa Miyazaki
  • Patent number: 11783889
    Abstract: A memory device according to the present technology includes a memory cell array configured to include planes having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merged buffers configured to generate a reference signal using the common reference voltage, and control logic configured to control an operation of the common reference voltage generator and the merged buffers so that page buffer control signals generated based on the reference signal are supplied to the page buffer.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Chan Hui Jeong
  • Patent number: 11774609
    Abstract: Disclosed herein is an apparatus suitable for detecting x-ray, comprising: an X-ray absorption layer configured to generate an electrical signal from an X-ray photon incident on the X-ray absorption layer; an electronics layer comprising an electronics system configured to process or interpret the electrical signal; and an interposer chip embedded in a board of an electrically insulating material; wherein the X-ray absorption layer is bonded to the electronics layer; wherein the electronics layer is bonded to the interposer chip.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: October 3, 2023
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 11761992
    Abstract: A current measurement circuit, for wireless charging systems, for instance, comprises a differential input configured to have applied an input voltage sensed across a shunt resistor traversed by a current to be measured, a voltage reversal switch arrangement selectively switchable to reverse the polarity of the input voltage as applied between a first and a second voltage sensing nodes as well as a first and a second current flow line between the voltage sensing nodes and ground. A difference resistor intermediate the two current flow lines is traversed by a current which is a function of the input voltage as applied to the first and second sensing nodes via the voltage reversal switch arrangement. First and second current sensing nodes at the two current flow lines are coupled to a differential current output via a current reversal switch arrangement selectively switchable to reverse the output current polarity.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 19, 2023
    Assignee: STMICROELECTRONICS S.R.L
    Inventors: Paolo Angelini, Roberto Pio Baorda, Francesco Borgioli
  • Patent number: 11757411
    Abstract: A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: September 12, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Satoshi Goto, Yusuke Tanaka
  • Patent number: 11756601
    Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 11728731
    Abstract: A Ton/2 generator retrofits a digital tracking algorithm to an analog Constant-On-Time (COT) Controller to enable fast sensing. The Ton/2 generation is cognizant of the delay between high-side switch (HSFET) on generation and the actual turn-on time of the HSFET so that there is no deviation of sampling point, and current is reported with high accuracy. The digital tracking algorithm automatically takes higher steps during load transients to enable faster tracking and scales the measured current (Ipeak/2) based on a discontinuous conduction mode (DCM) period for DCM current reporting.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Shobhit Tyagi, Saurabh Verma, Anup Deka
  • Patent number: 11676649
    Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Makoto Kitagawa
  • Patent number: 11670345
    Abstract: A sense amplifier includes first, second and third circuits. The third circuit includes; a first NMOS transistor connected between a first node connected with the first circuit and a third node, generates first internal data, and operates in response to second internal data, a second NMOS transistor connected between a second node connected with the first circuit and a fourth node, generates the second internal data, and operates in response to the first internal data, a first PMOS transistor connected between a first input node of receiving the input data and the third node and operates in response to a sensing signal, a second PMOS transistor connected between a second input node of receiving the inverted input data and the fourth node and operates in response to the sensing signal.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Hwan Kim
  • Patent number: 11581032
    Abstract: An apparatus including a temperature dependent circuit is configured to receive a temperature dependent power supply voltage, and further is configured to receive a first input signal and provide a temperature dependent output signal responsive to the input signal. A power control circuit including the temperature dependent circuit is configured to receive a second input signal, and further configured provide a first control voltage based on the first temperature dependent output signal and provide a second control voltage based on the second input signal. The second control voltage has a temperature dependency based on the temperature dependent power supply voltage. A sense amplifier coupled to a pair of digit lines is configured to receive the first and second control voltages and amplify a voltage difference between the digit lines of the pair.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Kenji Asaki
  • Patent number: 11532362
    Abstract: A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: December 20, 2022
    Assignee: Kioxia Corporation
    Inventor: Atsushi Kawasumi
  • Patent number: 11527283
    Abstract: A sense amplifier circuit includes a bitline node, a sense node, and a feedback circuit which is connected to the bitline node and to the sense node. The feedback circuit includes a cascode-connected pair of transistors configured to isolate the bitline node from an occurrence of a voltage variation on the sense node.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Alexander Fritsch, Holger Wetter
  • Patent number: 11513299
    Abstract: A photon detection device, configured to couple to a multicore optical fibre, the device comprising a plurality of detection regions, each detection region being arranged to align with just a single core of the multicore optical fibre when the device is coupled to the multicore optical fibre.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: November 29, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Andrew James Shields, Zakaria Moktadir
  • Patent number: 11448667
    Abstract: A bidirectional sensor circuit includes a sensing impedance with first and second terminals; a first operational amplifier which non-inverting input is connected to the first terminal and its inverting input is connected to the second terminal; a second operational amplifier with the non-inverting input connected to the second terminal and its inverting input is connected to the first terminal; a first diode with the anode connected to the inverting input of the first operational amplifier and whose cathode is connected to the output of the first operational amplifier; and a second diode with the anode connected to the output of the first operational amplifier and to the cathode of the first diode. The input of the circuit consists of the terminals of the sensing impedance, and the output is at the anode of the second diode and senses a load impedance connected to the first terminal of the sensing impedance.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 20, 2022
    Assignee: PANACEA QUANTUM LEAP TECHNOLOGY LLC
    Inventor: Francisco Javier Velasco Valcke
  • Patent number: 11450402
    Abstract: A sensing circuit is provided which generates a sensing result according to a reading voltage of a non-volatile memory. The sensing circuit includes four transistors and a switch group. A first transistor is coupled between an operating voltage and a first node. A second transistor is coupled between the first node and a second node. A third transistor is coupled between the second node and a reference ground voltage. A control terminal of the first transistor, a control terminal of the second transistor, and a control terminal of the third transistor all receive the reading voltage. A fourth transistor is coupled between the operating voltage and the first node. The switch group forms or disconnects a conduction path between a control terminal of the fourth transistor and the second node according to a control signal, so that the first node obtains the sensing result.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: September 20, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chien-Fa Lee, Yi-Chun Lin
  • Patent number: 11276469
    Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Der Chih
  • Patent number: 11170864
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suresh Balasubramanian, Stephen Wayne Spriggs, George B. Jamison
  • Patent number: 10930324
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Patent number: 10861567
    Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Rowley, Dustin J. Carter
  • Patent number: 10826536
    Abstract: A single-ended inter-chip data transmission system and a single-ended inter-chip data reception system are provided for processing data. A controlled Hamming weight parallel data encoder at a transmitter device accepts N data bits with an arbitrary Hamming weight as input and generates M data bits with a controlled Hamming weight as output, wherein M is greater than N. A transmission circuit provides a time-aligned transmission of the controlled Hamming weight encoded data across a single-ended data bus.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Troy James Beukema, Mounir Meghelli
  • Patent number: 10783955
    Abstract: A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10761221
    Abstract: A counting x-ray detector includes a converter element, a rewiring unit and an evaluation unit including pixel electrodes. In an embodiment, the converter element includes a first electrode on a surface facing away from the evaluation unit and a pixelated second electrode having a plurality of electrode elements on a surface facing toward the evaluation unit. The rewiring unit is on a surface of the converter element facing toward the evaluation unit. First contacts of electrically conductive connections between the electrode elements and the pixel electrodes are provided on a surface of the rewiring unit and include a first areal distribution; and second such contacts are provided on a surface of the rewiring unit, including a relatively smaller second areal distribution. An areal extent of the evaluation unit is relatively smaller than an areal extent of the converter element.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 1, 2020
    Assignee: SIEMENS HEALTHCARE GMBH
    Inventors: Thorsten Ergler, Harald Geyer, Christian Schroeter, Justus Tonn, Jan Wrege
  • Patent number: 10707852
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging apparatus, an electronic apparatus, and a method of controlling a comparator each of which enables power consumption to be reduced while a decision speed of the comparator is enhanced. A comparator, including: a differential input circuit operating at a first power source voltage, and outputting a signal when a voltage of an input signal is higher than a voltage of a reference signal; a positive feedback circuit operating at a second power source voltage lower than the first power source voltage, and speeding up a transition speed when a comparison result signal representing a result of comparison in voltage between the input signal and the reference signal is inverted; and a voltage converting circuit. The present disclosure can be applied to an ADC or the like arranged for each pixel of a solid-state imaging apparatus.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Masaki Sakakibara
  • Patent number: 10692547
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Patent number: 10685700
    Abstract: A PVT detection circuit including: first and second transistors of a first conduction type each having its control node coupled to a control line, the first and second transistors being configured such that the variations in their threshold voltages as a function of temperature and/or process are different from each other; and an amplifier coupled to a second main conducting node of each of the first and second transistors and configured to amplify a difference in the currents conducted by the first and second transistors in order to generate an output signal.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 16, 2020
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Pablo Royer, Adam Makosiej
  • Patent number: 10656184
    Abstract: A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 19, 2020
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Ying-Zong Juang, Hann-Huei Tsai, Po-Chang Wu, Yu-Chen Liu, Chih-Yuan Yeh
  • Patent number: 10627458
    Abstract: A sensor is provided having a magnetic field sensing element to generate a magnetic field signal, a switching circuit coupled to receive the magnetic field signal and generate a switching signal that changes a polarity of the magnetic field signal at a predetermined frequency, and a comparison device configured to receive the switching signal and generate an output signal that changes a level in response to the switching signal crossing a predetermined threshold. The switching circuit is disposed between the magnetic field sensing element and the comparison device and can provide the comparison device an input signal (i.e., the switching signal) that changes polarity at the predetermined frequency. The comparison device can sense characteristics, such as but not limited to crossing operate and release threshold levels, of both north and south polarity magnetic field signals using the switching signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 21, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventor: Pablo Javier Bolsinger
  • Patent number: 10594265
    Abstract: A semiconductor device may include an amplification circuit. The amplification circuit may be configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal. The amplification circuit may determine voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 10586592
    Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
  • Patent number: 10573355
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Patent number: 10529389
    Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Frederik Schippers
  • Patent number: 10431268
    Abstract: A semiconductor device receiving a differential data strobe signal and a method of operating the same are provided. The semiconductor device includes a differential signal phase detector receiving a differential signal including a first signal and a second signal, detecting a phase of the differential signal, and generating a mode control signal; and a receiver receiving the differential signal and a reference voltage and performing a processing operation using the differential signal in a differential mode or using the first signal and the reference voltage in a single mode according to the mode control signal. The semiconductor device may be a memory controller. Data transfer may be disabled in the single mode to prevent false data recognition due to noise.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Ho Choi, Seok-Kyun Ko, Sang-Hune Park
  • Patent number: 10395697
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Patent number: 10382017
    Abstract: Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew Berzins, Sumanth Suraneni
  • Patent number: 10361695
    Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Ankur Chauhan, Sudheer Prasad, Md. Abidur Rahman, Subrato Roy
  • Patent number: 10332571
    Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Hoyoung Song, Kwangchol Choe
  • Patent number: 10312894
    Abstract: According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 10269414
    Abstract: To sense an impedance state of one or more correlated electron switch elements, a bit-line may be precharged to a voltage level that is less than a precharge voltage level for a sense amplifier, and a bit-line may be discharged through one or more correlated electron switch elements. A bit-line may be buffered from a sense amplifier via an electronic switch device.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 23, 2019
    Assignee: ARM Ltd.
    Inventors: Piyush Agarwal, Shruti Aggarwal, Mudit Bhargava, Akshay Kumar
  • Patent number: 10250236
    Abstract: A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Sarma Vrudhula, Niranjan Kulkarni, Jinghua Yang
  • Patent number: 10210928
    Abstract: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Marco-Domenico Tiburzi, Giulio-Giuseppe Marotta
  • Patent number: 10163483
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Scott James Derner, Christopher John Kawamura, Charles L. Ingalls
  • Patent number: 10152613
    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 11, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Joyce Kwong, Clive Bittlestone, Manish Goel
  • Patent number: 10110208
    Abstract: According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide, an output signal.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 10103628
    Abstract: A circuit and a method for sensing a current flowing through a pass device of a voltage converter. The pass device is switchable between a conducting state and a non-conducting state. The circuit contains an output node for providing an indication of the current flowing through the pass device, a capacitive element, connected between the pass device and the output node. A first switching element is connected between the first terminal of the capacitive element and ground. A second switching element is connected between the second terminal of the capacitive element and ground. A control circuit controls the first and second switching elements to isolate the output node from the terminal of the pass device through the capacitive element while the pass device is in the non-conducting state.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: October 16, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Siarhei Meliukh
  • Patent number: 10090035
    Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan Kyung Kim
  • Patent number: 10074407
    Abstract: Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Richard C. Murphy
  • Patent number: 10031242
    Abstract: An apparatus for detecting radiation energy includes a first comparator coupled to a first voltage source applying a first threshold voltage to the first comparator. The apparatus includes a second comparator, a radiation detector, Analog-to-Digital Converter (ADC), and control circuitry. The second comparator is coupled to a second voltage source applying a second threshold voltage to the second comparator. The radiation detector is coupled to the first and second comparators. The ADC has a first input coupled to the detector, and is responsive to a second input for placing it in a low-power mode. The control circuitry is coupled to outputs of the comparators and the ADC, and the control circuitry temporarily switches the ADC from the low-power mode to a normal operating mode to perform a peak measurement of detected radiation energy, and determine the first and second threshold voltages based on the peak measurement.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 24, 2018
    Assignee: Oregon State University
    Inventors: Abdollah Tavakoli Farsoni, Eric Matthew Becker
  • Patent number: 10020966
    Abstract: An alternative type of vector signaling codes having increased pin-efficiency normal vector signaling codes is described. Receivers for these Permutation Modulation codes of Type II use comparators requiring at most one fixed reference voltage. The resulting systems can allow for a better immunity to ISI-noise than those using conventional multilevel signaling such as PAM-X. These codes are also particularly advantageous for storage and recovery of information in memory, as in a DRAM.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 10, 2018
    Assignee: KANDOU LABS, S.A.
    Inventor: Amin Shokrollahi