With Sensing Amplifier Patents (Class 327/51)
  • Patent number: 10395697
    Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mahdi Jamali, William A. Melton, Daniele Vimercati, Xinwei Guo, Yasuko Hattori
  • Patent number: 10382017
    Abstract: Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew Berzins, Sumanth Suraneni
  • Patent number: 10361695
    Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Ankur Chauhan, Sudheer Prasad, Md. Abidur Rahman, Subrato Roy
  • Patent number: 10332571
    Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Ho Cha, Chankyung Kim, Sungchul Park, Hoyoung Song, Kwangchol Choe
  • Patent number: 10312894
    Abstract: According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 10269414
    Abstract: To sense an impedance state of one or more correlated electron switch elements, a bit-line may be precharged to a voltage level that is less than a precharge voltage level for a sense amplifier, and a bit-line may be discharged through one or more correlated electron switch elements. A bit-line may be buffered from a sense amplifier via an electronic switch device.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 23, 2019
    Assignee: ARM Ltd.
    Inventors: Piyush Agarwal, Shruti Aggarwal, Mudit Bhargava, Akshay Kumar
  • Patent number: 10250236
    Abstract: A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Sarma Vrudhula, Niranjan Kulkarni, Jinghua Yang
  • Patent number: 10210928
    Abstract: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Marco-Domenico Tiburzi, Giulio-Giuseppe Marotta
  • Patent number: 10163483
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 25, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Scott James Derner, Christopher John Kawamura, Charles L. Ingalls
  • Patent number: 10152613
    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes after applying a voltage to a memory array: determining a first duration between the applying of the voltage and a first output of a first bit cell, the first output corresponding to a first value stored in the first bit cell, and determining a second duration between the applying of the voltage and a second output of a second bit cell, the second output corresponding to a second value stored in the second bit cell. The example method further includes determining a function based on a comparison of the first duration and the second duration, the function to establish an identification of a circuit that includes the memory array.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 11, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Joyce Kwong, Clive Bittlestone, Manish Goel
  • Patent number: 10110208
    Abstract: According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide, an output signal.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 10103628
    Abstract: A circuit and a method for sensing a current flowing through a pass device of a voltage converter. The pass device is switchable between a conducting state and a non-conducting state. The circuit contains an output node for providing an indication of the current flowing through the pass device, a capacitive element, connected between the pass device and the output node. A first switching element is connected between the first terminal of the capacitive element and ground. A second switching element is connected between the second terminal of the capacitive element and ground. A control circuit controls the first and second switching elements to isolate the output node from the terminal of the pass device through the capacitive element while the pass device is in the non-conducting state.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: October 16, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Siarhei Meliukh
  • Patent number: 10090035
    Abstract: A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan Kyung Kim
  • Patent number: 10074407
    Abstract: Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Richard C. Murphy
  • Patent number: 10031242
    Abstract: An apparatus for detecting radiation energy includes a first comparator coupled to a first voltage source applying a first threshold voltage to the first comparator. The apparatus includes a second comparator, a radiation detector, Analog-to-Digital Converter (ADC), and control circuitry. The second comparator is coupled to a second voltage source applying a second threshold voltage to the second comparator. The radiation detector is coupled to the first and second comparators. The ADC has a first input coupled to the detector, and is responsive to a second input for placing it in a low-power mode. The control circuitry is coupled to outputs of the comparators and the ADC, and the control circuitry temporarily switches the ADC from the low-power mode to a normal operating mode to perform a peak measurement of detected radiation energy, and determine the first and second threshold voltages based on the peak measurement.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 24, 2018
    Assignee: Oregon State University
    Inventors: Abdollah Tavakoli Farsoni, Eric Matthew Becker
  • Patent number: 10020966
    Abstract: An alternative type of vector signaling codes having increased pin-efficiency normal vector signaling codes is described. Receivers for these Permutation Modulation codes of Type II use comparators requiring at most one fixed reference voltage. The resulting systems can allow for a better immunity to ISI-noise than those using conventional multilevel signaling such as PAM-X. These codes are also particularly advantageous for storage and recovery of information in memory, as in a DRAM.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 10, 2018
    Assignee: KANDOU LABS, S.A.
    Inventor: Amin Shokrollahi
  • Patent number: 10014851
    Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: July 3, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Ankur Chauhan, Sudheer Prasad, Md. Abidur Rahman, Subrato Roy
  • Patent number: 9990962
    Abstract: A data sense amplifier may include: first and second external nodes, wherein a potential difference occurs between the first and second external nodes when a memory cell is selected; an amplification unit suitable for generating and amplifying a potential difference between first and second nodes in response to the potential difference between the first and second external nodes; and a switching unit suitable for electrically coupling the first and second external nodes to the first and second nodes, respectively, after a predetermined time elapses from when the memory cell is selected.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong-Keun Kim
  • Patent number: 9972373
    Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 15, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • Patent number: 9966131
    Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: May 8, 2018
    Assignee: Synopsys, Inc.
    Inventors: Dharmesh Kumar Sonkar, Niranjan Behera
  • Patent number: 9899069
    Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventor: Jianan Yang
  • Patent number: 9897632
    Abstract: A monitor circuit for monitoring a CUT (Circuit Under Test) is provided. The monitor circuit includes a power switch and a current meter. The power switch is coupled between a supply voltage and the CUT. The current meter is coupled in parallel with the power switch. The current meter is configured to detect a current through the CUT.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventor: Bo-Jr Huang
  • Patent number: 9812199
    Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 7, 2017
    Assignee: SK hynix Inc.
    Inventor: Dong-Keun Kim
  • Patent number: 9792979
    Abstract: Systems, apparatuses, and methods for tracking a retention voltage are disclosed. In one embodiment, a circuit is utilized for generating a standby voltage for a static random-access memory (SRAM) array. The circuit tracks the leakage current of the bitcells of the SRAM array as the leakage current varies over temperature. The circuit mirrors this leakage current and tracks the higher threshold voltage of a p-channel transistor or an n-channel transistor, with the p-channel and n-channel transistors matching the transistors in the bitcells of the SRAM array. The circuit includes a voltage regulator to supply power to the SRAM array at a supply voltage proportional to the higher threshold voltage tracked. Setting a supply voltage of the SRAM array based on threshold voltages and leakage current may reduce power consumption as compared to using a supply voltage based on a worst case operating conditions assumption for the SRAM array.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 17, 2017
    Assignee: Apple Inc.
    Inventor: Michael A. Dreesen
  • Patent number: 9788370
    Abstract: A light-emitting-diode-driving device includes a control circuit that is configured to perform constant current control with a DC-DC converter so that a value of a current detected by a current detection unit agrees with a prescribed reference current value to be supplied to a light source. The control circuit includes a reference-current-instruction unit, a threshold-voltage-setting unit, and a comparator circuit. The reference-current-instruction unit is configured to set the prescribed reference current value. The threshold-voltage-setting unit is configured to set a threshold voltage for determining a short circuit failure in the light source. The comparator circuit is configured to compare, with the threshold voltage, a value of a voltage that is detected by a voltage detection unit. The control circuit is configured to make the threshold-voltage-setting unit reduce the threshold voltage, when the reference-current-instruction unit reduces the prescribed reference current value.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: October 10, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoshiyuki Inada
  • Patent number: 9747991
    Abstract: Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 29, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9704572
    Abstract: A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 11, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Yingchang Chen, Anurag Nigam, Chang Siau
  • Patent number: 9666273
    Abstract: A sensing circuit senses a sensing voltage of a resistive memory cell and outputs a resultant value in response to the sensing voltage which is indicative for the actual cell state. A settling circuit includes a plurality of current mirrors for settling the sensing voltage to a certain target voltage representing one of M programmable cell states. A prebiasing circuit is provided for prebiasing a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage. A resistance circuit includes a plurality of resistors connected in series and coupled in parallel to the resistive memory cell. The resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit. The settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs switchable to define a linear range detection currents corresponding to the certain target voltages.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Milos Stanisavljevic
  • Patent number: 9667200
    Abstract: Peak detecting cascode for breakdown protection. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 30, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: David Steven Ripley
  • Patent number: 9659631
    Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Onegyun Na, Jongtae Kwak, Seong-Hoon Lee, Hoon Choi
  • Patent number: 9621145
    Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator is configured to operate as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating the relative values of the inputs.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 9583208
    Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Synopsys, Inc.
    Inventors: Sachin Taneja, Vaibhav Verma, Pritender Singh, Sanjeev Kumar Jain
  • Patent number: 9552851
    Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
  • Patent number: 9532427
    Abstract: This application relates to a lighting system comprising a plurality of light emitting diode, LED, circuits, and a power source for providing a drive voltage to the plurality of LED circuits. For each LED circuit, the lighting system comprises a first variable resistance element connected between the respective LED circuit and ground, and a first feedback circuit configured to control a voltage at a first node between the respective LED circuit and the respective first variable resistance element to a first voltage. The lighting system further comprises a current source and a second variable resistance element connected between the current source and ground, wherein each first variable resistance element is configured to attain a resistance value depending on a resistance value attained by the second variable resistance element.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 27, 2016
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Fulvio Schiappelli, Jiri Ledr, Alessandro Angeli, Andrea Acquas
  • Patent number: 9490760
    Abstract: The present invention provides a self-timed differential amplifier, including an amplifier unit, having a pair of read/write terminals, wherein data is read or written by a select line; a pair of precharge transistors, controlled by a control line; and a pair of cross-coupled transistors, controlled by a column select line. Moreover, a complementary differential amplifier is formed by the combination of the pair of precharge transistors and the pair of cross-coupled transistors. The pair of the precharge transistors and the pair of cross-coupled transistors are connected to the pair of read/write terminals of the amplifier unit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: November 8, 2016
    Assignee: CHINGIS TECHNOLOGY CORPORATION
    Inventors: Mingshiang Wang, Ping-Chao Ho
  • Patent number: 9478277
    Abstract: Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells. Selected memory cell connected to bitline (BLT) to develop signal voltage, and adjacent reference bitline (BLR) develops reference voltage at VDD/2. An asymmetrical sensing amplifier (ASA), which has alternative positive offset and negative offset, is used to sense signal voltage and reference voltage for both their difference and sameness. ASA control signals, A and B, switch at different timing points or at different voltage level or the combination of both to have offset voltage set at either positive or negative polarity. Two consecutive read out from one ASA or one single read out from two ASA can be implemented to read memory cells data to local IOs. Output from ASA will be used to restore voltage back to the accessed memory cells.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 25, 2016
    Inventor: Bo Liu
  • Patent number: 9443050
    Abstract: Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 13, 2016
    Assignee: Oregon State University
    Inventors: Jacob Postman, Patrick Yin Chiang
  • Patent number: 9437280
    Abstract: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 6, 2016
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Gary B. Bronner
  • Patent number: 9424943
    Abstract: The present invention provides a data reading device capable of preventing erroneous writing during an operation of reading data from a non-volatile memory element. The data reading device includes a dummy reading circuit provided with a non-volatile memory element, the writing voltage of which is lower than that of a non-volatile memory element of a data reading circuit, and a state detection circuit that detects a written state of the non-volatile memory element of the dummy reading circuit. Upon detection of erroneous writing to the non-volatile memory element of the dummy reading circuit during a data reading operation, the data reading operation is immediately terminated.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 23, 2016
    Assignees: SEIKO INSTRUMENTS INC., SII SEMICONDUCTOR CORPORATION
    Inventors: Kotaro Watanabe, Makoto Mitani
  • Patent number: 9406354
    Abstract: A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: August 2, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Taehui Na, Jisu Kim, Jung Pill Kim, Seung Hyuk Kang
  • Patent number: 9401185
    Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 26, 2016
    Assignee: SK hynix Inc.
    Inventors: Kyu Nam Lim, Woong Ju Jang
  • Patent number: 9384790
    Abstract: A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Manish Trivedi, Setti Shanmukheswara Rao, Ankur Goel
  • Patent number: 9356570
    Abstract: An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventor: Gerd Rombach
  • Patent number: 9310490
    Abstract: Among other things, one or more techniques and/or systems are described for counting detection events on a detector cell of a photon counting detector array. An electronics arrangement of the detector cell comprises a digital discriminator which is configured according to an impulse response of the detector cell or, more particularly, an impulse response of a radiation detection element of the detector cell (e.g., where the radiation detection element is configured to convert energy of the radiation photon into electrical charge). The digital discriminator is configured to analyze a digital representation of a voltage signal of the detector cell and to compare a result of the analysis to one or more metrics derived based upon the impulse response of the detector cell to identify voltage pulses of the voltage signal that are indicative of detection events.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 12, 2016
    Assignee: Analogic Corporation
    Inventors: Douglas Q. Abraham, Basak Ulker Karbeyaz
  • Patent number: 9299449
    Abstract: Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line while a voltage level of the sense node is greater than a voltage level of the data line, and inhibiting discharging of the data line to the sense node while the voltage level of the data line is greater than the voltage level of the sense node. Sense circuits include a path between an input node and a sense node facilitating current flow from the sense node to the input node when a voltage level of the sense node is greater than a voltage level of the input node and inhibiting current flow from the input node to the sense node when the voltage level of the sense node is less than the voltage level of the input node.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: March 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Andrea D'Alessandro, Violante Moschiano
  • Patent number: 9299397
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Grant
    Filed: September 14, 2014
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter L. Ter├žariol, Richard Titov Lara Saez, Afr├ónio Magno da Silva, Jr.
  • Patent number: 9291724
    Abstract: An imaging system (100) includes a direct conversion detector pixel (111) that detects radiation traversing an examination region and generates an electrical signal indicative thereof, wherein the signal includes a persistent current, which is produced by a direct conversion material of the pixel and which shifts a level of the signal. A persistent current estimator (116) estimates the persistent current and generates a compensation signal based on the estimate. A pre-amplifier (112) receives the signal and the compensation signal, wherein the compensation signal substantially cancels the persistent current, producing a persistent current compensated signal, and that amplifies the compensated signal, generating an amplified compensated signal. A shaper (114) generates a pulse indicative of energy of the radiation illuminating the direct conversion material based on the amplified compensated signal.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 22, 2016
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventor: Roland Proksa
  • Patent number: 9224437
    Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Abraham Mathews, Donald W. Plass, Kenneth J. Reyer
  • Patent number: 9177621
    Abstract: A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Yu, Ku-Feng Lin
  • Patent number: 9117547
    Abstract: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventor: John E. Barth, Jr.