With Diverse Type Transistor Devices Patents (Class 327/542)
  • Patent number: 10352993
    Abstract: A wafer burn-in test circuit may be provided. The wafer burn-in test circuit may include a timing correction unit configured to generate a plurality of timing-compensated input signals by synchronizing a plurality of pulse signals generated according to a plurality of input signals with an input signal among the plurality of input signals. The wafer burn-in test circuit may include a wafer burn-in signal decoding unit configured to generate a plurality of decoding signals by decoding the plurality of timing-compensated input signals and output the plurality of decoding signals as a plurality of wafer burn-in signals by latching the plurality of decoding signals.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventor: Young Jae Choi
  • Patent number: 9728231
    Abstract: A device includes a voltage regulator, an auxiliary signal generator, and a circuit cell. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to output an auxiliary signal. The circuit cell is configured to receive both of the write voltage and the auxiliary signal according to a first select signal and a second select signal.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Lee, Yi-Chun Shih
  • Patent number: 8866538
    Abstract: The present inventive concept is a hyuntak transistor that can prevent a thermal runaway phenomenon and a low heat high efficiency constant current circuit using an auxiliary transistor capable of a high amplification and a constant current. The circuit may be applied to drive a LED and a motor.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: October 21, 2014
    Assignees: Electronics and Telecommunications Research Institute, Dongwon Systems Corporation
    Inventors: Hyun-Tak Kim, Bongjun Kim, Sun Shin Kwag, Jun Sik Kim
  • Publication number: 20140254258
    Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 11, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Xinwei Guo, Mingdong Cui
  • Patent number: 8823444
    Abstract: A reference voltage generating circuit comprises a pair of variable resistors connected to a pair of bipolar transistors. A differential amplifier amplifies the band gap voltage difference between the bipolar transistors and outputs a reference voltage to an output terminal. An output stage resistor is connected to the output terminal and a resistance dividing circuit. The generating circuit includes temperature compensating circuits that receive tap voltages from resistance dividing circuit and a current proportional to the temperature, then output correction currents. The generating circuit additionally includes a current mirror circuit that outputs a mirror current depending on each correction current. The reference voltage generating circuit thus corrects the temperature dependence of the reference voltage.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Fujime, Masaaki Morikawa
  • Patent number: 8766672
    Abstract: An electronic switching device comprises a first bipolar junction transistor (BJT) (2a) adapted to control the flow of current between a pair of switching terminals; a charge recovery circuit coupled to the base of the first BJT (2a) and adapted to establish a supply voltage across a capacitor (5) by storing in the capacitor (5) charge carriers accumulated in the base of the first BJT (2a) during application of a base drive current, the quantity of accumulated charge carriers depending on the base drive current; and a controllable current source (4) adapted to control the base drive current, thereby controlling the supply voltage.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 1, 2014
    Assignee: NXP B.V.
    Inventor: Anton Cornelis Blom
  • Patent number: 8717092
    Abstract: An improved current mirror circuit. The current mirror circuit includes a current mirror base network, a current source transistor, and an error transistor. The current mirror base network includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to the current source transistor through a first impedance element. The second terminal is connected to the error transistor. The third terminal is connected to a first bias voltage source, and the first terminal is connected to a second bias voltage source.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Anadigics, Inc.
    Inventors: Rui Filipe Antunes Ribafeita, Michael Wayne Trippe
  • Patent number: 8638163
    Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jung Kim, U-in Chung, Jai-kwang Shin
  • Patent number: 8587368
    Abstract: A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ping Yao, Wen-Shen Chou
  • Publication number: 20130285738
    Abstract: A charging circuit includes a first current mirror including a first branch circuit, a second branch circuit and a third branch circuit for generating a first conduction current, a second conduction current and a third conduction current according to the input voltage, a second current mirror including a fourth branch circuit coupled to the first branch circuit and including a first channel width, and a fifth branch circuit coupled to the second branch circuit and including a second channel width, wherein a load circuit is coupled between the first current mirror and the second current mirror, and the first current mirror as well as the second current mirror correspondingly adjust values of the first conduction current, the second conduction current and the third conduction current according to the first channel width as well as the second channel width, so as to process a charging operation of the load circuit.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 31, 2013
    Applicant: Anpec Electronics Corporation
    Inventors: Chih-Ning Chen, Yen-Ming Chen
  • Patent number: 8402288
    Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: March 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Dan Kuzmin
  • Patent number: 8390491
    Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 5, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Tsutomu Wakimoto
  • Patent number: 8378658
    Abstract: A semiconductor device, circuit, and AC and DC load switch for maintaining a small input-output differential voltage and providing a defined response. The load switch can include a pass element coupled to an input terminal and an output terminal. The pass element can include a control terminal, with the control terminal controlling a response of the pass element. The load switch can include a first loop coupled to the control terminal configured to control a voltage drop between the input terminal and the output terminal while maintaining high impedance with the pass element. The load switch can include a second loop coupled to the control terminal configured to provide a defined filter response from the input terminal. The defined response can be a low pass response, high pass response, or a band pass response. The passband and/or stopband of the response can be programmed.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: February 19, 2013
    Assignee: Micrel, Inc.
    Inventor: David Schie
  • Publication number: 20130033322
    Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.
    Type: Application
    Filed: March 5, 2010
    Publication date: February 7, 2013
    Inventors: Bart Balm, Jeroen Bouwman, Léon C.M. van den Oever
  • Patent number: 8313034
    Abstract: The present invention provides a reference power supply circuit which does not require trimming and prevents occurrence of deadlock of a band gap reference circuit. An RFID tag chip related to the present invention has a reference power supply including a switch for switching between a band gap reference circuit and a Vth difference reference circuit. A reference potential in band gap reference of the band gap reference circuit and an output of the Vth difference reference circuit are compared by a comparator, and a transistor operating as a switch is controlled, thereby making the reference potential in band gap reference rise, hastening startup of the band gap reference circuit, and preventing occurrence of deadlock in the band gap reference circuit.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Okuda
  • Patent number: 8314650
    Abstract: Disclosed is a reference voltage generating circuit including a constant current circuit which comprises: a first resistive element and a bipolar transistor connected in series between a supply voltage terminal and a constant potential point; a first MOS transistor having a gate connected to a node connecting the first resistive element with the bipolar transistor; a second resistive element connected in series between a source of the first MOS transistor and the constant potential point; a second MOS transistor connected between a drain of the first MOS transistor and the supply voltage terminal; and a third MOS transistor forming a current mirror in conjunction with the second MOS transistor, wherein a constant current generated by the constant current circuit or a current proportional to the generated constant current is converted to a voltage as a reference voltage.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 20, 2012
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Takafumi Goto, Tomomitsu Ohara
  • Patent number: 8229379
    Abstract: Systems and methods are disclosed that use multiple DC-DC (direct-current-to-direct-current) regulators and configurable DC-DC regulators with respect to multi-band audio receivers in order to allow for the use of different DC-DC regulator switching clock signals for different audio broadcast bands. The systems and methods disclosed thereby help to alleviate interference problems typically caused by switching devices used in the DC-DC conversion process. The embodiments described are also applicable to switching power supplies run from alternating current (AC) power sources and to Class D amplifiers working with broadcast radios.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 24, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Ligang Zhang
  • Patent number: 8228052
    Abstract: A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 24, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Stefan Marinca
  • Patent number: 8212545
    Abstract: In order to realize a reference voltage circuit that operates with lower current consumption while maintaining an operation at lower voltage without causing deterioration of a power supply rejection ratio, provided is a reference voltage circuit in which a depletion transistor of an ED type reference voltage circuit is constituted of a plurality of depletion transistors connected in series, and in which a gate terminal of a cascode depletion transistor is connected to a connection point between the depletion transistors of the ED type reference voltage circuit.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Imura
  • Patent number: 8169256
    Abstract: A circuit includes an operational amplifier including a first input and a second input. A first resistor has a first end coupled to the first input. A first bipolar transistor includes a first emitter coupled to a second end of the first resistor, and a first base. A second bipolar transistor includes a second emitter coupled to the second input, and a second base. A third bipolar transistor includes a third emitter coupled to the first base, a first collector, and a third base connected to the first collector. A fourth bipolar transistor includes a fourth emitter coupled to the second base, a second collector, and a fourth base connected to the second collector. A second resistor is coupled to the first input, wherein the second resistor is parallel to the first resistor and the first bipolar transistor.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ping Yao, Wen-Shen Chou
  • Publication number: 20110304387
    Abstract: In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
    Type: Application
    Filed: March 14, 2011
    Publication date: December 15, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichi Hirashiki, Norio Hagiwara, Tsutomu Nakashima, Minoru Nagata
  • Patent number: 8065535
    Abstract: A semiconductor integrated circuit includes an external terminal input with an external power supply voltage, a plurality of field effect transistors connected between the external terminal and an internal power supply line and a control circuit input with potentials of spots where voltage drops from output points of the output transistors are substantially the same in the internal power supply line, and controlling the plurality of field effect transistors according to the potential being input.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shingo Nakashima
  • Patent number: 8049555
    Abstract: An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/drain path of a first transistor drives a sampling capacitor. The second terminal of the source/drain channel of each subsequent transistor is connected to a backgate of a previous transistor. The backgate of the last transistor is connected to a supply voltage level. The second terminals of the subsequent transistors may be connected to corresponding buffer capacitors. The backgate of the last transistor may be supplied with the input during sampling and the supply voltage level at other times.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Matthias Arnold, Bernhard Ruck, Aymen Landoulsi
  • Patent number: 7965125
    Abstract: A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 21, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Manabu Ishida
  • Patent number: 7750726
    Abstract: A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: July 6, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Masayuki Nakamura, Hitoshi Tanaka
  • Publication number: 20100164609
    Abstract: A reference voltage generating circuit includes a reference voltage generating unit generating a uniform reference voltage in response to a bias voltage, a bias voltage generating unit generating the bias voltage, and a start-up circuit, after activating the bias voltage generating unit by receiving a first supply voltage, canceling a change of the first supply voltage to maintain a separation from the bias voltage generating unit. The circuit adopts a start-up circuit having a voltage distributing unit, thereby preventing a quiescent point of a bias voltage generating unit from entering a zero state and prevents a reference voltage from rising in a power-up state that an analog supply voltage rises according to a change of an external design environment such as a power, a temperature, a process parameter and the like, thereby generating a reference voltage more stably. As a result, current consumption and power consumption are minimized.
    Type: Application
    Filed: December 16, 2009
    Publication date: July 1, 2010
    Inventor: Min-Jong Yoo
  • Publication number: 20100079200
    Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Qi Xiang, Albert Ratnakumar, Jeffrey Xiaoqi Tung, Weiqi Ding
  • Patent number: 7598801
    Abstract: A voltage regulator and a voltage regulating method thereof and a voltage generator using the voltage regulator are disclosed by the present invention. The voltage regulator of the present invention uses a first switching unit and a second switching unit to respectively provide an operational transconductance amplifier (OTA) with different closed-loop feedback paths during a first period and a second period. In this way, an auto-zeroing unit is able to exactly store an input offset voltage presented between the inverting input terminal and the non-inverting input terminal of the OTA.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: October 6, 2009
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Jen Yen, Chih-Yuan Hsieh
  • Publication number: 20090243713
    Abstract: A reference voltage circuit which is less dependent on semiconductor process variations compared to bandgap based reference voltage circuits. The circuit comprises a first amplifier having an inverting input, a non-inverting input and an output. A current biasing circuit provides first and second PTAT currents, and a CTAT current. The CTAT current is equal in value to the second PTAT at a first predetermined temperature and opposite in polarity. A first load element is coupled to the non-inverting input of the first amplifier and arranged for receiving the first PTAT current such that a PTAT voltage is developed across the first load element. A feedback load element is coupled between the inverting input and the output of the amplifier for receiving the summation of the CTAT current and the second PTAT current.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: Analog Devices, Inc.
    Inventor: Stefan Marinca
  • Publication number: 20090243708
    Abstract: A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The load MOS device is operably coupled to the second bipolar transistor such that a base-emitter difference (?Vbe) resulting from the collector current density difference between the first and second bipolar transistors is developed across the drain-source resistance ron, of the load MOS device. A cascoded MOS device of a second aspect ratio is operably coupled to the load MOS device and is driven by the amplifier to operate in the triode region.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: Analog Devices, Inc.
    Inventor: Stefan Marinca
  • Publication number: 20090160538
    Abstract: A bandgap reference circuit which is operable in low supply conditions is described. Such a circuit includes a second amplifier and a resistor at the output of a bandgap reference cell to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1 and Q2 with currents of different forms.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Analog Devices, Inc.
    Inventor: Stefan Marinca
  • Publication number: 20090160537
    Abstract: A bandgap voltage reference circuit with an inherent curvature correction which comprises an amplifier having an inverting terminal, a non-inverting terminal and an output terminal is described. A first and second bipolar transistor operable at different current densities are provided each of the transistors being coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier such that a ?Vbe is reflected across a first load element. A current biasing circuit is provided which includes a semiconductor device coupled to each of the first and second bipolar transistors and is configured for applying a non-linear bias current to the first and second bipolar transistors for biasing thereof.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Applicant: Analog Devices, Inc.
    Inventor: Stefan Marinca
  • Patent number: 7541862
    Abstract: A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: June 2, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Masayuki Nakamura, Hitoshi Tanaka
  • Patent number: 7535285
    Abstract: A reference circuit. Included are first and second reference circuit blocks, first and second controllable current sources connected to supply current through the first and second reference circuit blocks respectively, an amplifier having non-inverting and inverting inputs responsive to the voltages developed by the first and second reference circuit blocks respectively and having an output connected to control the currents provided by the first and second current sources, and an output stage having a reference output controlled by the output of the amplifier. The reference circuit further comprises start-up circuitry, including a latch having an output indicating its state and being responsive to a signal indicative of the output from the reference output to latch from a first state into a second state when that signal passes a first threshold, and a switch that is responsive to the output of the latch to supply a control signal.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: May 19, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Derek Colman
  • Patent number: 7482859
    Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: January 27, 2009
    Assignee: Vimicro Corporation
    Inventors: Zhao Wang, Qing Yu, David Xiao Dong Yang
  • Patent number: 7477095
    Abstract: A current mirror has an input bipolar device and an output bipolar device, a first MOSFET device to control a current in the input bipolar device, and a second MOSFET device to control a bias current to common base terminals of the input and output bipolar devices. An output stack may be coupled to the bipolar output device, and may include at least one output MOSFET device.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 13, 2009
    Assignee: Silicon Laboratories Inc.
    Inventor: Russell J. Apfel
  • Patent number: 7456679
    Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a VBE and a multiplied ?VBE, so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ?VBE loop. The ?VBE loop can be the portion of the circuit involved in generating the ?VBE voltage. Other embodiments are disclosed in this application.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: November 25, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John M. Pigott, Byron G. Bynum
  • Patent number: 7449941
    Abstract: A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: November 11, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Ali E. Zadeh, Ashirwad Bahukhandi
  • Patent number: 7423416
    Abstract: A voltage regulator includes first and second MOS transistors and a bipolar transistor. The first MOS transistor has a first conductivity type and has a drain coupled to a first power supply voltage terminal, a gate for receiving a first bias voltage, and a source. The second MOS transistor has a second conductivity type and has a source coupled to the first power supply voltage terminal, a drain coupled to the source of the first MOS transistor, and a gate for receiving a second bias voltage. The bipolar transistor has a collector coupled to the source of the first MOS transistor, a base for receiving a third bias voltage, and an emitter for providing an output voltage. The first MOS transistor and the second MOS transistor control a voltage level at the collector of the bipolar transistor in response to a varying power supply voltage provided to the first power supply voltage terminal.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: September 9, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bryan Quinones, William E. Edwards, Randall C. Gray
  • Publication number: 20080186083
    Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.
    Type: Application
    Filed: November 10, 2004
    Publication date: August 7, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Dan Kuzmin
  • Patent number: 7400188
    Abstract: A voltage providing circuit includes a protective circuit and a power supply circuit. The protective circuit includes a first transistor. A first control signal is input to a collector of the first transistor, a second control signal is input to a base of the first transistor, an emitter of the first transistor is grounded. The collector of the first transistor is connected to the power supply circuit. The second control signal and the first control signal jointly control the power supply circuit to be turned on or turned off. When the second control signal is at a low level, the first transistor is turned off and the power supply circuit is turned off. When the second control signal is at a high level, the first transistor is turned on and the power supply circuit is turned on. Thus, the providing circuit can prevent the electronic component from being damaged when a computer is restarted.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: July 15, 2008
    Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yong-Zhao Huang, Yun Li
  • Patent number: 7368975
    Abstract: A circuit is described that generates multiple voltages each having a common reference point. The circuit uses a feedback control loop to generate a center voltage, a first voltage generator, and a second voltage generator. The first voltage generator generates a first high voltage related to the center voltage plus a first offset voltage and a first low voltage related to the center voltage minus the first offset voltage, where the first offset voltage is determined by a first control input to the first voltage generator. The second voltage generator generates a second high voltage related to the center voltage plus a second offset voltage and a second low voltage related to the center voltage minus the second offset voltage, where the second offset voltage is determined by a second control input to the second voltage reference generator. An example is also presented where the multiple voltage generator circuit is advantageously employed in a deserializer data acquisition system.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: May 6, 2008
    Assignee: Agere Systems Inc.
    Inventor: Joseph Anidjar
  • Patent number: 7365589
    Abstract: A bandgap reference circuit, taking two or more power supplies as the input power supply for outputting a reference voltage, includes a first reference circuit, a second reference circuit, a power selection circuit and a switch circuit. The first and second reference circuits receive two respective power supplies for producing first and second voltages, respectively. As the power selection circuit takes the first power voltage level as the input voltage, the power selection circuit outputs a first control signal; while the power selection circuit takes the second power voltage level as the input voltage, the power selection circuit outputs a second control signal. The switch circuit is coupled to the power selection circuit, the first reference circuit and the second reference circuit. As the switch circuit receives the first control signal, it outputs the first voltage; while the switch circuit receives the second control signal, it outputs the second voltage.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: April 29, 2008
    Assignee: ITE Tech. Inc.
    Inventor: Yi-Chung Chou
  • Patent number: 7321255
    Abstract: A voltage generating circuit outputs a generated voltage corresponding to (a+b+c)-bit digital data from a plurality of generated voltages. The voltage generating circuit includes a first selector of each conductive type and 2a pieces of second selectors of each conductive type. Each first selector is constituted by the conductive type MOS transistor, and based on upper order a-bit of the digital data, outputs one of the generated voltages selected corresponding to low order (b+c)-bit of the digital data. Each second selector is constituted by the conductive type MOS transistor, and based on low order a-bit of the digital data, outputs one of the generated voltages to the first selector of the conductive type. One output and the other outputs of the first selectors of both conductive types are connected to one another.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 22, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Katsuhiko Maki
  • Patent number: 7262650
    Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 28, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Patent number: 7259614
    Abstract: An auto voltage sense circuit uses voltage controlled current sources to generate a desired reference voltage level that closely tracks the variations and changes of a first voltage level and a second voltage level. The auto voltage sensing circuit includes a first voltage controlled current source operable to receive the first voltage level to generate a reference current that is proportional to the first voltage level. The auto voltage sensing circuit also includes a second voltage controlled current source operable to receive the second voltage level and the reference voltage to generate an output current that is proportional to the difference between the second voltage level and the reference voltage. The reference voltage causes the output current to be approximately equal to the reference current so as to generate a reference voltage that is proportional to the difference between the second voltage level and the first voltage level.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: August 21, 2007
    Assignee: Integrated Device Technology, Inc.
    Inventors: William G. Baker, Timothy Gillespie
  • Patent number: 7248097
    Abstract: Voltage-activated and accurate current sink, and method of providing same. In one aspect, a circuit for accurately sinking current includes a zener diode coupled to a power source at the cathode of the zener diode, and first and second transistors, where the first transistor has its collector coupled to the power source and its base coupled to the cathode of the zener diode, and the second transistor has its base coupled to the anode of the zener diode and its emitter coupled to ground. A resistor is coupled between the emitter of the first transistor and the collector of the second transistor.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 24, 2007
    Assignee: Micrel, Inc.
    Inventor: Sean Montgomery
  • Patent number: 7224208
    Abstract: A voltage regulator has a reference voltage generator that outputs a reference voltage based on first and second electrical source voltages, an output circuit which generates a predetermined direct-current voltage based on the reference voltage and generates a comparison voltage lower than the predetermined direct-current voltage, and a differential amplifier coupled between the reference voltage generator and the output circuit. The differential amplifier provides a control voltage to the output circuit responsive to a difference between the reference and comparison voltages. The voltage regulator has a voltage adjustment circuit that adjusts the reference voltage responsive to a variation in the first electrical source voltage. The differential amplifier may include a constant-current circuit and an operation current generating circuit.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: May 29, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yuichi Matsushita
  • Patent number: RE39918
    Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: November 13, 2007
    Assignee: STMicroelectronics, Inc.
    Inventor: William Carl Slemmer
  • Patent number: RE40673
    Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: March 24, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Minoru Kanbara, Kazuhiro Sasaki, Katsuhiko Morosawa