Stabilized (e.g., Compensated, Regulated, Maintained, Etc.) Patents (Class 327/538)
  • Patent number: 11521659
    Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Sang-Hoon Lee
  • Patent number: 11502611
    Abstract: The switching circuit includes a first capacitor to which a pulse signal output from a control unit is input, a rectification circuit including at least a first diode and a second diode, the rectification circuit rectifying a voltage input from the first capacitor, and generating a first voltage, and a first switching element including a first terminal, a second terminal and a third terminal, the first voltage generated by the rectification circuit being applied between the first terminal and the second terminal.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: November 15, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Jun Hirabayashi
  • Patent number: 11495960
    Abstract: A semiconductor device includes, for example, an external terminal, an output element, a detecting element configured to detect occurrence of a negative voltage at the external terminal, and an off-circuit configured to forcibly turn off the output element when the detecting element detects occurrence of the negative voltage.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 8, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Makoto Yasusaka, Isamu Iwahashi, Kotaro Iwata
  • Patent number: 11480983
    Abstract: A regulator circuit according to one embodiment includes a first transistor, a filter, and a differential amplifier. The first transistor is provided between an input terminal on a power supply side and an output terminal on an output side. The differential amplifier includes an output node connected to the first transistor, and controls the first transistor on the basis of a result of comparison between a reference voltage and a feedback voltage according to an output voltage applied to the output terminal. The filter is connected to a control node that makes a differential pair with the output node, in the differential amplifier.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: October 25, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuichi Sawahara
  • Patent number: 11467206
    Abstract: The present invention relates to an apparatus for calibrating a battery simulator having an input and an output, wherein a current path with an apparatus for measuring the current strength and with at least one capacitor is provided between the input and output. Furthermore, a voltage path can be provided between the input and output, with an apparatus for measuring the voltage and/or a current transformer, in the secondary current of which the apparatus for measuring the current strength is connected. If a battery simulator is connected to the apparatus it can charge the capacitor and then the capacitor can charge the battery simulator, whilst the current strength and voltage are measured, and on that basis the internal measurement devices of the battery simulator are calibrated.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 11, 2022
    Assignee: KRISTL, SEIBT & CO. GESELLSCHAFT M.B.H.
    Inventors: Arthur Goeldner, Christian Auer, Thomas Haidinger, Stefan Pircher
  • Patent number: 11378991
    Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 5, 2022
    Assignee: NXP B.V.
    Inventors: Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi
  • Patent number: 11360501
    Abstract: A reference voltage generation circuit may include: a first reference current path formed through a first node and a first transistor; a second reference current path formed through a second node and a second transistor; a first feedback loop configured to feed a first current back to the first and second reference current paths such that voltage levels of the first and second nodes are kept the same; and a second feedback loop configured to control the currents flowing through the first and second transistors according to a second current.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventor: Young Sub Yuk
  • Patent number: 11360504
    Abstract: A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: June 14, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stephen Victor Kosonocky
  • Patent number: 11342856
    Abstract: A switched mode power converter has an energy transfer element that delivers an output signal to a load. A power switching device coupled to the primary side of the energy transfer element regulates a transfer of energy to the load. A secondary controller is coupled to receive a feedback signal and output a pulsed signal in response thereto. A primary controller is coupled to receive the pulsed signal and output a drive signal in response thereto, the drive signal being coupled to control switching of the power switching device. A compensation circuit generates an adaptively compensated signal synchronous with the pulsed signal. The adaptively compensated signal has a parameter that is adaptively adjusted in response to a comparison of the feedback signal with a threshold reference signal. The parameter converges towards a final value that produces a desired level of the output signal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 24, 2022
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: Giao Minh Pham, Vikram Balakrishnan, Arthur B. Odell, Antonius Jacobus Johannes Werner, Karl Moore, Matthew David Waterson
  • Patent number: 11342146
    Abstract: A system and method for monitoring energy use in an electronic device. In one embodiment, an energy monitoring system includes a processor and an energy monitor module. The energy monitor module includes instructions that when executed cause the processor to receive values of measured parameters of a pulse signal that controls the switching of energy to an energy storage device in a switch mode power supply that provides power to an electronic device. The instructions also cause the processor to determine, based on the values of measured parameters, attributes of operation of the electronic device powered by the energy source during an interval corresponding to the measured parameters. The instructions further cause the processor to generate, based on the attributes of operation, a control signal that causes the electronic device to change the loading of the power supply by the electronic device.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 24, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Horst Diewald, Johan Zipperer, Peter Weber, Anton Brauchle
  • Patent number: 11307644
    Abstract: A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventor: Shah M. Sharif
  • Patent number: 11295649
    Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 11296596
    Abstract: A voltage regulator circuit comprises a regulator output; an amplifier that is activated in response to a first signal and inactivated in response to a second signal, the error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and an output that generates a differential with respect to the reference voltage and the feedback voltage; an active discharging transistor that, in response to a falling slope of the electronic signal, discharges a present electronic signal at the regulator output; and a first switch at the output of the amplifier that is in open state in response to a receipt of the second signal to disconnect a coupling capacitor path between the regulator output and the reference voltage to negate an effect of noise on the reference voltage in response to the falling slope of the electronic signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 5, 2022
    Assignee: NXP B.V.
    Inventor: Geunwook Kim
  • Patent number: 11290060
    Abstract: A bias circuit includes first and second bipolar transistors, first and second field-effect transistors, and a filter circuit. The first field-effect transistor supplies a bias signal to an amplifier. The filter circuit is connected between a collector terminal of the first bipolar transistor and the ground through a base terminal of the first bipolar transistor. The filter circuit has frequency characteristics for attenuating a high frequency component of an RF signal to be input to the amplifier.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Soga
  • Patent number: 11257414
    Abstract: A display driver comprises: a first grayscale line; output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; and first gamma assist circuitry comprising a first holding node to hold the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 22, 2022
    Assignee: Synaptics Incorporated
    Inventors: Yutaka Saeki, Taisuke Koshino, Yoshinori Ura
  • Patent number: 11201620
    Abstract: A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: December 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Guorui Wang, Zheng Li, Chen Wang, Yu Zhu, Zhenming Zhang
  • Patent number: 11196952
    Abstract: A comparing circuit may include a first amplifier and a second amplifier. The first amplifier performs a correlated double sampling operation in response to a pixel signal and a ramp signal, and the second amplifier amplifies an output signal of the first amplifier. The second amplifier includes a current stabilization circuit that supplies current to the second amplifier during the correlated double sampling operation irrespective of the output signal of the first amplifier.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunhwan Jung, Sunyool Kang, Jaehong Kim
  • Patent number: 11139005
    Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang-Hoon Lee
  • Patent number: 11094274
    Abstract: A circuit device includes a transfer gate, a charge compensation circuit, and a control circuit. The control circuit controls the charge compensation circuit. The charge compensation circuit discharges charge from an output node of the transfer gate when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The charge compensation circuit injects charge into the output node of the transfer gate when a voltage of the input signal to the transfer gate is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 11095280
    Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 17, 2021
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: Timothy Ziemba, Kenneth E. Miller, John G. Carscadden, James Prager
  • Patent number: 11049529
    Abstract: A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Frank Tzen-Wen Guo, Bhuvaneshwari Ayyagari-Sangamalli, Angada B. Sachid, Blessy Alexander
  • Patent number: 11043508
    Abstract: A semiconductor device obtains high current ratio accuracy by eliminating an influence of plasma charging using a MOS-type transistor in which a channel region is isolated and separated from a semiconductor substrate. In a current mirror circuit in which both of a well of a NMOS-type transistor that generates a bias and a well of a NMOS-type transistor that receives the bias are formed insulated and separated from a semiconductor substrate, a connection circuit is connected between gate electrodes and wells of NMOS-type transistors without through the semiconductor substrate, and the connection circuit makes the gate electrodes and the wells in an electrically short-circuited state during manufacturing of the current mirror circuit, and makes the gate electrodes and the wells in a disconnected state in at least one direction during a mounting operation.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 22, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou Wada, Yoichiro Kobayashi, Masato Kita
  • Patent number: 11031050
    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 8, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 11005457
    Abstract: A circuit that produces an output signal having a frequency that is proportional to absolute temperature (PTAT) is disclosed. In one embodiment, the circuit includes a ring oscillator and a bias current circuit coupled thereto. The ring oscillator and the bias current circuit are implemented in close proximity to one another. During operation, the bias current circuit generates a bias current that is provided to the ring oscillator. The amount of bias current generated is dependent upon the temperature of the circuit. In turn, the frequency of an output signal provided by the ring oscillator is dependent on the amount of bias current received from the bias current circuit. Accordingly, the frequency of the ring oscillator output signal is dependent on the temperature of the circuit.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: May 11, 2021
    Assignee: Apple Inc.
    Inventors: Ramy A. Ahmed, Amr A. Hafez, Jafar Savoj
  • Patent number: 10998894
    Abstract: Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving a second input signal and thereby outputting a first output signal to a first output terminal; and a latch circuit coupled between the first and second output terminals. The upper circuit is coupled between a high voltage terminal and the buffer circuit and transmits current to the first and second output terminals according to each of the first and second input signals. The lower circuit is coupled between the buffer circuit and a low voltage terminal and withdraws current flowing through the first and second output terminals according to each of the first and second input signals.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 4, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yung-Chung Chen
  • Patent number: 10962574
    Abstract: An apparatus includes a power switch configured to conduct a dc or ac current, a sense switch having a first drain/source terminal and a gate connected to a first drain/source terminal and a gate of the power switch respectively, an amplifier having a first input coupled to a second drain/source terminal of the power switch and a second input coupled to a second drain/source terminal of the sense switch and a first current sense processing switch having a gate connected to an output of the amplifier.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 30, 2021
    Assignee: NuVolta Technologies (Hefei) Co., Ltd.
    Inventors: Caiqiang Zhou, Sichao Liu
  • Patent number: 10928463
    Abstract: A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor includes a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each TMR element. The current lines are serially or sequentially connected to a current source to receive the bipolar current pulse. The field sensor has an output including a high output and a low output in response to the bipolar pulse. This asymmetric response allows a chopping technique for 1/f noise reduction in the field sensor.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: February 23, 2021
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Bradley Neal Engel, Phillip G. Mather
  • Patent number: 10914761
    Abstract: A voltage detector includes a voltage division circuit which outputs a divided voltage based on an input voltage, a comparison circuit which compares the divided voltage and a reference voltage to output a detection signal and a release signal, and a voltage limiting circuit which limits the divided voltage to a preset voltage.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 9, 2021
    Assignee: ABLIC INC.
    Inventor: Daiki Endo
  • Patent number: 10878738
    Abstract: A display product and a drive chip for driving a display panel are provided. The drive chip includes a gamma voltage divider circuit, which includes a voltage-dividing resistor string, consisting of resistors connected in series, configured to generate binding-point grayscale voltages; OPs, each of which is disposed at an output channel of the binding-point grayscale voltage, each OP having a positive power end receiving a first voltage and a negative power end receiving a second voltage, the first voltage greater than the second voltage; a low-voltage stabilized supply, providing the fixed second voltage to the negative power end; and a DAC, providing the first voltage to the positive power end. The first voltage provided by the DAC is dynamically adjusted based on grayscale or data voltages that are to be inputted to the display panel. By this way, the power loss of the drive chip is reduced.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 29, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Rui Ju
  • Patent number: 10860498
    Abstract: A data processing system is disclosed, which relates to a technology for implementing a convergence memory system provided with a plurality of memories. The data processing system includes a compute blade configured to generate a write command to store data and a read command to read the data, and a memory blade configured to selectively performed read and write operations in response to the read and write commands in a plurality of memories. The compute blade has a memory that stores information about performance characteristics of each of the plurality of memories, and is configured to determine priority information through which eviction of a cache line is carried out based on the stored information.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Gyu Jeong
  • Patent number: 10826438
    Abstract: A bias circuit includes a buffer, a temperature compensation circuit, and a feedback circuit. The buffer includes a first transistor. A first terminal of the first transistor and a second terminal of the first transistor are electrically connected with a first voltage source. A third terminal of the first transistor is electrically connected with an external amplifier. The temperature compensation circuit includes a second transistor and a temperature compensation component. A first terminal of the second transistor is electrically connected with the third terminal of the first transistor. Two terminals of the temperature compensation component are electrically connected with a second terminal of the second transistor and the first voltage source respectively. A third terminal of the second transistor is grounded. The feedback circuit is electrically connected with the first terminal of the first transistor and the second terminal of the second transistor.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 3, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Gao-Ching Lin, Wei-Tsung Li
  • Patent number: 10782723
    Abstract: A reference signal generator circuit can be configured to provide a temperature-compensated voltage reference signal at an output node. The reference signal generator can include a diode-connected first FET device coupled between a supply node and the output node, and a flipped-gate transistor coupled between the output node and a reference node. The reference signal generator can include a bias current source configured to provide a bias current to the output node to adjust a current density in the flipped-gate transistor relative to a current density in the first transistor.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Chiong Yew Lai, Lei Liu
  • Patent number: 10735041
    Abstract: A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jikai Chen, Yuan Rao, Yanli Fan
  • Patent number: 10693292
    Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a surge protection device, coupled to the DC trigger circuit, that generates a clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. A feedback circuit is provided between the surge protection device and the DC trigger circuit. The feedback circuit lowers the clamp voltage so that it does not exceed a failure voltage of the surge protection device.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 23, 2020
    Assignee: NXP USA, Inc.
    Inventors: Shenglan Tang, Jian Qing, Xindong Duan
  • Patent number: 10678280
    Abstract: A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 9, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Korea Advanced Institute of Science and Technology
    Inventors: Gyu-Hyeong Cho, Yongjin Lee, Dae-Yong Kim, Sangho Kim
  • Patent number: 10658048
    Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Loredana Chiaramonte, Anna Rita Maria Lipani
  • Patent number: 10659033
    Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
  • Patent number: 10651835
    Abstract: This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Waymo LLC
    Inventor: Vadim Gutnik
  • Patent number: 10618077
    Abstract: A differential amplifier generates an output voltage waveform exhibiting a slew rate over a rise time. The amplifier is powered from a dc voltage input and includes a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance. A comparator functions to compare a voltage at the dc voltage input against a reference voltage in order to detect when the voltage drops below the reference voltage. A gain stage controls the gain of the differential amplifier and a bias current control circuit controls the bias current of the differential amplifier. In response to the detection by the comparator of the voltage dropping below the reference voltage, the gain stage and the bias current control circuit decrease the gain of the amplifier and jointly decrease the bias current in order to maintain a value of the rise time.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Calcagno, Domenico Cristaudo, Stefano Corradi
  • Patent number: 10606300
    Abstract: Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a current. The current source may be coupled to a voltage source via a transistor. The transistor may be configured to provide the voltage source to the current source based on a voltage of a gate of the transistor. The example apparatus may further include an amplifier configured to provide a voltage to the gate of the transistor based on a voltage differential between two inputs. The voltage differential between the two inputs may adjust due to process, voltage or temperature changes such that the current provided by the current source remains constant.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Wei Lu Chu
  • Patent number: 10598968
    Abstract: A transmitter for an optical device includes semi-conductor waveguides, each incorporating an electro-optic phase-shifter in the semi-conductor waveguide that is operable to change the refractive index of the waveguide to thereby introduce a phase shift in the light propagated through the waveguide. The electro-optic is connected to a phase shift controller and to a temperature measurement component, such as a PTAT circuit, that is integrated into the electronic or photonic chip carrying the waveguide. Temperature measurement by the measurement component can be multiplexed with the normal operation of the phase-shifter so that the temperature measurement function does not interfere with the phase shifting function.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Behnam Behroozpour, Pedram Lajevardi, Jan Niklas Caspers
  • Patent number: 10528069
    Abstract: An integrated circuit includes a highest class core circuit that has a positive power supply terminal connected to a positive power supply terminal of an external power source, and is configured to receive a first supply voltage which is at least a portion of a an input supply voltage that is provided from the external power source based on an operation throughput; and a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to a negative power supply terminal of the external power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeokki Hong, Cheheung Kim, Sungchan Kang, Jinmyoung Kim, Sangha Park, Yongseop Yoon, Choongho Rhee
  • Patent number: 10439421
    Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Selcuk Talay, Fabio Rigoni
  • Patent number: 10410689
    Abstract: A regulator includes: a comparator for generating a comparison signal by comparing a feedback voltage obtained by dividing an output voltage with a reference voltage; a current supply switch for controlling a current amount of a pump voltage applied to a first node in response to the output voltage; a control circuit for controlling a potential of an internal node in response to the comparison signal; and a current supply circuit for supplying a current through the first node and to apply the current to the internal node, and generating the output voltage by controlling an amount of current applied to an output node according to a potential level of the internal node.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae Ho Lee, Tei Cho
  • Patent number: 10394264
    Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
  • Patent number: 10388782
    Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Riccardo Pittassi, Oliver Blank
  • Patent number: 10374647
    Abstract: A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jikai Chen, Yuan Rao, Yanli Fan
  • Patent number: 10348194
    Abstract: The present disclosure provides a pump circuit comprising a plurality of first enabling modules. Each of the plurality of first enabling modules is configured to generate a first enable signal and includes a first voltage input, a first comparing unit, a first digital logic gate and a second digital logic gate. The first comparing unit is coupled to the first voltage input and is configured to compare a voltage of the first voltage input with a first reference voltage. The first digital logic gate is coupled to the first comparing unit and is configured to implement a logical operation. The second digital logic gate is coupled to the first digital logic gate and is configured to implement a logical negation. Each of the plurality of first enabling modules generates the first enable signal when the voltage of the first voltage input is less than the first reference voltage.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 9, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Jen Chen, Ting-Shuo Hsu
  • Patent number: 10338670
    Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: RE49018
    Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 5, 2022
    Assignee: Mosaid Technologies Incorporated
    Inventor: Dieter Haerle