Stabilized (e.g., Compensated, Regulated, Maintained, Etc.) Patents (Class 327/538)
  • Patent number: 10693292
    Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a surge protection device, coupled to the DC trigger circuit, that generates a clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. A feedback circuit is provided between the surge protection device and the DC trigger circuit. The feedback circuit lowers the clamp voltage so that it does not exceed a failure voltage of the surge protection device.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 23, 2020
    Assignee: NXP USA, Inc.
    Inventors: Shenglan Tang, Jian Qing, Xindong Duan
  • Patent number: 10678280
    Abstract: A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 9, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Korea Advanced Institute of Science and Technology
    Inventors: Gyu-Hyeong Cho, Yongjin Lee, Dae-Yong Kim, Sangho Kim
  • Patent number: 10659033
    Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sujan Kundapur Manohar, Michael James Mills, Justin Patrick Vogt
  • Patent number: 10658048
    Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: May 19, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Loredana Chiaramonte, Anna Rita Maria Lipani
  • Patent number: 10651835
    Abstract: This disclosure provides systems, methods and apparatuses for processing analog signals with a wide dynamic range. In some implementations, the analog signal may be a current signal that is logarithmically scaled to decrease its dynamic range and converted to an output voltage using two or more diodes. A first diode may be used to scale a first range of the current signal and a second diode may be used to scale a second range of the current signal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Waymo LLC
    Inventor: Vadim Gutnik
  • Patent number: 10618077
    Abstract: A differential amplifier generates an output voltage waveform exhibiting a slew rate over a rise time. The amplifier is powered from a dc voltage input and includes a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance. A comparator functions to compare a voltage at the dc voltage input against a reference voltage in order to detect when the voltage drops below the reference voltage. A gain stage controls the gain of the differential amplifier and a bias current control circuit controls the bias current of the differential amplifier. In response to the detection by the comparator of the voltage dropping below the reference voltage, the gain stage and the bias current control circuit decrease the gain of the amplifier and jointly decrease the bias current in order to maintain a value of the rise time.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Calcagno, Domenico Cristaudo, Stefano Corradi
  • Patent number: 10606300
    Abstract: Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a current. The current source may be coupled to a voltage source via a transistor. The transistor may be configured to provide the voltage source to the current source based on a voltage of a gate of the transistor. The example apparatus may further include an amplifier configured to provide a voltage to the gate of the transistor based on a voltage differential between two inputs. The voltage differential between the two inputs may adjust due to process, voltage or temperature changes such that the current provided by the current source remains constant.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Wei Lu Chu
  • Patent number: 10598968
    Abstract: A transmitter for an optical device includes semi-conductor waveguides, each incorporating an electro-optic phase-shifter in the semi-conductor waveguide that is operable to change the refractive index of the waveguide to thereby introduce a phase shift in the light propagated through the waveguide. The electro-optic is connected to a phase shift controller and to a temperature measurement component, such as a PTAT circuit, that is integrated into the electronic or photonic chip carrying the waveguide. Temperature measurement by the measurement component can be multiplexed with the normal operation of the phase-shifter so that the temperature measurement function does not interfere with the phase shifting function.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Behnam Behroozpour, Pedram Lajevardi, Jan Niklas Caspers
  • Patent number: 10528069
    Abstract: An integrated circuit includes a highest class core circuit that has a positive power supply terminal connected to a positive power supply terminal of an external power source, and is configured to receive a first supply voltage which is at least a portion of a an input supply voltage that is provided from the external power source based on an operation throughput; and a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to a negative power supply terminal of the external power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeokki Hong, Cheheung Kim, Sungchan Kang, Jinmyoung Kim, Sangha Park, Yongseop Yoon, Choongho Rhee
  • Patent number: 10439421
    Abstract: A linear charger circuit and method for providing an output current at an output node is presented. The circuit contains a pass device connected between an input node and the output node, first and second replica devices connected in parallel to the pass device, with their control terminals coupled to a control terminal of the pass device. The first replica device is coupled to a first circuit path for determining whether current output by the linear charger circuit shall be terminated. The second replica device is coupled to a second circuit path for providing feedback for controlling the pass device, a control circuit coupled to the second circuit path for controlling the pass device based on a quantity indicative of a current flowing through the second circuit path, and a switching circuit coupled to the second circuit path.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mihail Jefremow, Selcuk Talay, Fabio Rigoni
  • Patent number: 10410689
    Abstract: A regulator includes: a comparator for generating a comparison signal by comparing a feedback voltage obtained by dividing an output voltage with a reference voltage; a current supply switch for controlling a current amount of a pump voltage applied to a first node in response to the output voltage; a control circuit for controlling a potential of an internal node in response to the comparison signal; and a current supply circuit for supplying a current through the first node and to apply the current to the internal node, and generating the output voltage by controlling an amount of current applied to an output node according to a potential level of the internal node.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae Ho Lee, Tei Cho
  • Patent number: 10394264
    Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
  • Patent number: 10388782
    Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Giuseppe Bernacchia, Riccardo Pittassi, Oliver Blank
  • Patent number: 10374647
    Abstract: A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jikai Chen, Yuan Rao, Yanli Fan
  • Patent number: 10348194
    Abstract: The present disclosure provides a pump circuit comprising a plurality of first enabling modules. Each of the plurality of first enabling modules is configured to generate a first enable signal and includes a first voltage input, a first comparing unit, a first digital logic gate and a second digital logic gate. The first comparing unit is coupled to the first voltage input and is configured to compare a voltage of the first voltage input with a first reference voltage. The first digital logic gate is coupled to the first comparing unit and is configured to implement a logical operation. The second digital logic gate is coupled to the first digital logic gate and is configured to implement a logical negation. Each of the plurality of first enabling modules generates the first enable signal when the voltage of the first voltage input is less than the first reference voltage.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 9, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Jen Chen, Ting-Shuo Hsu
  • Patent number: 10338670
    Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: William Paul Hovis, Garrett Douglas Blankenburg, Peter Anthony Atkinson, Robert James Ray, Andres Felipe Hernandez Mojica, Samy Boshra-Riad, Erng-Sing Wee, Brian Keith Langendorf
  • Patent number: 10312912
    Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 4, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Michael Graves
  • Patent number: 10270333
    Abstract: A power supply system includes a control module for generating a control signal; a first charging pump module, coupled to the control module, for generating an adjustment charging value according to the control signal, and outputting a charging voltage according to the adjustment charging value and a conduction voltage source; an amplifying module, coupled to the first charging pump module, for utilizing the charging voltage to generate an amplifying voltage; and a load module, coupled to the amplifying module, for processing a dynamic charging operation according to the amplifying voltage.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 23, 2019
    Assignee: Sitronix Technology Corp.
    Inventor: Min-Nan Liao
  • Patent number: 10268228
    Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 23, 2019
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 10200042
    Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: February 5, 2019
    Assignee: Sanechips Technology Co. Ltd.
    Inventor: Hailiang Cui
  • Patent number: 10186969
    Abstract: There is to provide a semiconductor device capable of activating a circuit quickly, operating with a lower power consumption in a steady state, and coping with the dispersion of the elements. The semiconductor device includes an amplifier coupled to a power voltage, to output a voltage based on a reference voltage and a voltage of a negative feedback node, to an output node; and a voltage divider coupled to the output node, to output the divided voltage to the negative feedback node. The voltage divider includes first and second voltage dividing paths with different resistance, a first switching circuit coupled to the first and the second voltage dividing paths, in a dividing ratio adjustable way, and a second switching circuit for controlling the first and the second voltage dividing paths.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 22, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Kohei Hashimoto
  • Patent number: 10185337
    Abstract: A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sungmin Ock, Wenjing Yin, Xuhao Huang
  • Patent number: 10180453
    Abstract: Methods and systems for sourcing and/or sinking current from power supplies of differing voltage levels. A driving circuit may, for example, receive power from first and second power supplies, where the first power supply provides current to the driving circuit at a first voltage level and the second power supply provides current to the driving circuit at a second voltage level, and where the first voltage is greater than the second voltage. As a result, the first power supply allows the driving circuit to provide current over a wide voltage range, and the second power supply allows the driving circuit to provide current at lower voltages with less power consumption.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 15, 2019
    Assignee: Analog Test Engines
    Inventor: Jeffrey Allen King
  • Patent number: 10156882
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 10152107
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 10126768
    Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carmelo Burgio, Mauro Giacomini
  • Patent number: 10116303
    Abstract: A power circuit includes a power source for providing electrical power and two driving transistors being disposed in parallel and receiving electrical power from the power source. Each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection. The power circuit also includes a control voltage source having a first terminal and a second terminal. The control voltage source provides a control signal to the two driving transistors for determining driving currents through the two driving transistors. The first terminal is connected to the gate terminals of the two driving transistors, and the second terminal is connected to the kelvin source connections of the two driving transistors. The kelvin source connections of the two driving transistors are inductively coupled.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 30, 2018
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Yincan Mao, Chi-Ming Wang, Zichen Miao, Khai Ngo
  • Patent number: 10079514
    Abstract: In a non-contact power supply system, an electric power receiving device with suppressed heat generation is provided. The electric power receiving device is configured with a resonance circuit which includes a resonance capacity and a resonance coil acting as a receiving antenna, and receives electric power in a non-contact manner using resonant coupling of the resonance circuit. When receiving electric power, the electric power receiving device monitors the reception electric power received by the resonance circuit and controls the resonance frequency of the resonance circuit so as to keep the reception electric power from exceeding a target electric power level (PTGT). Accordingly, even when an electric power larger than the electric power required by the electric power receiving device is transmitted from the transmitting side, the electric power receiving device operates not to receive the electric power greater than the target electric power level.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 18, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiko Sone
  • Patent number: 10061341
    Abstract: This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Dieter Draxelmayr
  • Patent number: 10031164
    Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Takada, Nobuya Koike, Akihiro Nakahara, Makoto Tanaka
  • Patent number: 9954422
    Abstract: An integrated gate driver for motor control includes a first diode coupled to an upper rail and providing a voltage on a first connector and a power amplifier coupled between the first connector and a second connector that can be coupled to a source of a high-side power transistor. The power amplifier receives a control signal and provides an output signal to a second pin for driving a gate of the high-side power transistor. A first integrated capacitor is coupled between the first and second connector and an integrated charge pump is coupled to supply a current to the first connector. The charge pump includes a second integrated capacitor having a terminal coupled to a high frequency oscillator and a terminal coupled through a second diode to the first connector and a third diode coupled between the second connector and a point between the second capacitor and the second diode.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Miroslav Oljaca, Ajinder Singh, Sanjay Pithadia
  • Patent number: 9953608
    Abstract: The present invention relates to a driving circuit of a display panel. A plurality of driving units produce a reference driving voltage according to a gamma voltage of a gamma circuit, respectively. A plurality of digital-to-analog converting circuits receive the reference driving voltages output by the plurality of driving units, and select one of the plurality of reference driving voltage as a data driving voltage according to pixel data, respectively. The plurality of digital-to-analog converting circuits transmit the plurality of data driving voltages to the display panel for displaying images. A voltage boost circuit is used for producing a first supply voltage and providing the first supply voltage to the plurality of digital-to-analog converting circuits. At least a voltage boost unit is used for producing a second supply voltage and providing the second supply voltage to the plurality of driving units.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 24, 2018
    Assignee: Sitronix Technology Corp.
    Inventors: Min-Nan Liao, Chih-Ping Su
  • Patent number: 9923455
    Abstract: A current control circuit includes a current transformer that detects a primary current, a sensor gain switch that selectively connects the primary current to one of a first gain amplifier and a second gain amplifier to provide a current sensing output, a controller gain switch that selectively connects the current sensing output to one of a first controller amplifier and a second controller amplifier, and a controller that controls switching of the sensor gain switch and the controller gain switch.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: March 20, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Bing Gong, Jahangir Afsharian
  • Patent number: 9909931
    Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 6, 2018
    Assignee: SK HYNIX INC.
    Inventors: Kyu Tae Park, Marco Passerini
  • Patent number: 9898992
    Abstract: The present invention relates to an area-saving driving circuit for a display panel, which comprises a plurality of digital-to-analog converting circuits convert input data, respectively, and produce a pixel signal. A plurality of driving units are coupled to the plurality of digital-to-analog converting circuits, respectively. They produce a driving signal according to the pixel signal and transmit the driving signal to the display panel for displaying. A plurality of voltage booster units are coupled to the plurality of driving units, respectively, and produce a supply voltage according to a control signal. Then the supply voltage is provided to the plurality of driving units. Thereby, by providing the supply voltage to the plurality of driving units of the display panel by means of the plurality of voltage booster units, the area of the external storage capacitor is reduced. Alternative, the external storage capacitor can be even not required.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: February 20, 2018
    Assignee: Sitronix Technology Corp.
    Inventor: Min-Nan Liao
  • Patent number: 9874886
    Abstract: An integrated circuit may include a reference voltage generating circuit for generating a reference voltage. The reference voltage generating circuit may include a digital operation circuit and a digital-to-analog converter. The digital operation circuit is configured to adjust a reference voltage to temperature code relationship using a coefficient that adjusts a relative relationship between the reference voltage and the temperature code, and separate code that adjusts an absolute relationship between the reference voltage and the temperature code, wherein the temperature code reflects a temperature at the integrated circuit. The digital-to-analog converter is configured to generate the reference voltage based on an output from the digital operation circuit.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-cheol Kim
  • Patent number: 9853533
    Abstract: A circuit arrangement including a first branch, a second branch and a switching feedback structure is provided. The switching feedback structure may be coupled to the first branch and to the second branch. The switching feedback structure may be configured to adjust a current in the second branch to track a current in the first branch.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Adriano Sambucco
  • Patent number: 9817427
    Abstract: A voltage mirror circuit, having an input node and an output node provides substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. The voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 14, 2017
    Assignee: Dialog Semiconductor GmbH
    Inventor: Slawomir Malinowski
  • Patent number: 9740219
    Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: August 22, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shigeru Nagatomo
  • Patent number: 9728272
    Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 8, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Miyanishi, Yuichiro Ishii, Yoshisato Yokoyama
  • Patent number: 9681524
    Abstract: A power supply includes a first component arrangement providing a first current output for initializing control circuitry, and a second component arrangement providing a second current output to the control circuitry when the control circuitry initialization is complete, and a method of operating a power supply includes connecting a first component arrangement of the power supply to provide control circuitry with a first current for initializing operations within a predetermined time period, and connecting a second component arrangement of the supply to provide the control circuitry with a second current when initializing operations are complete.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: June 13, 2017
    Assignee: GE LIGHTING SOLUTIONS, LLC
    Inventors: Carre Denise Scheidegger, Gang Yao
  • Patent number: 9634613
    Abstract: A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 25, 2017
    Assignee: Raytheon Company
    Inventors: Edward A. Watters, Christopher M. Laighton, John P. Bettencourt
  • Patent number: 9588541
    Abstract: The embodiments described herein relate to an improved regulator circuit technique having a dual-loop configuration with a current regulation loop to provide the transient response and a voltage regulation loop to provide accurate DC voltage regulation. The current regulation loop comprises a pass transistor, a current sensing transistor, a current summation circuit, and a series of current mirrors to provide a fast load transient response current. The voltage regulation loop includes an output voltage feedback network, an error amplifier, a compensation capacitor, and the current sensing transistor and is configured to provide accurate DC offset regulation to diminish output voltage errors introduced by the transient load currents.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ngai Yeung Ho, Hua Guan
  • Patent number: 9590609
    Abstract: A gate-driver device for operating a field-effect-transistor (FET) includes a pull-down-block and a pull-up-block resistant to or protected from short circuits of the gate drive signal output by the device. The pull-down-block is operable to drive a gate of a FET to a low-voltage. The pull-up-block includes a resistive-pull-up operable to an ON-state and an OFF-state to switchably couple the gate to the high-voltage via an upper-resistive-element, and a current-pull-up arranged in parallel with the resistive-pull-up. The current-pull-up is operable to an ON-state and an OFF-state to control a current-source applied to the gate. When the pull-up-block drives the gate to the high-voltage, the resistive-pull-up and the current-pull-up operates from the OFF-state to the ON-state. A turn-on-interval after the resistive-pull-up operates from the OFF-state to the ON-state the resistive-pull-up operates to the OFF-state while the current-pull-up is maintained in the ON-state.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: March 7, 2017
    Assignee: Delphi Technologies Inc.
    Inventor: Osman Musa
  • Patent number: 9582021
    Abstract: A bandgap reference circuit with curvature compensation. The circuit includes a first current mirror that mirrors the current conducted by the bandgap reference. A difference between the gate-to-source voltages in the two legs provides a first mirrored current with non-linear temperature stability. This first mirrored current is again mirrored by a second current mirror in which the mirror transistors also have differing gate-to-source voltages, with the current from this second current mirror coupled to the bandgap reference to compensate for curvature in the CTAT current over temperature.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Matthias Arnold, Asif Qaiyum
  • Patent number: 9575498
    Abstract: The present disclosure includes circuits and methods for generating bleeding currents. In one embodiment, a pass transistor of a voltage regulator receives a voltage from a feedback circuit. A negative resistance circuit is coupled to a node to produce a bleeding current that turns on when needed and is otherwise off to save power. In one embodiment, the negative resistance circuit includes stacked current mirrors and a resistor. In another embodiment, the resistor has a first terminal that receives the voltage from the feedback circuit and a second terminal is coupled to a constant reference voltage that tracks the input voltage.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vincenzo Peluso, Bing Liu
  • Patent number: 9564886
    Abstract: A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if receiving a first signal, performing a voltage boost process; and if receiving a second signal, stopping the voltage boost process; a voltage division unit including a plurality of different voltage division coefficients, adapted for performing a voltage division process; a comparison unit adapted for: comparing the divided voltage with a reference voltage; if the divided voltage is low, outputting the first signal; and if not, outputting the second signal; a control unit adapted for performing a descending switching operation on the voltage division coefficients; and an output unit. The establishing speed of the operation voltage is effectively controlled, and an effect on device power consumption and performance caused by the threshold voltage and variations of the threshold voltage in the working process is eliminated.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 7, 2017
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Mingyong Huang, Jun Xiao
  • Patent number: 9525349
    Abstract: A power supply decoupling circuit includes an operational amplifier, a capacitor, a source resistor, and a stabilization circuit. The operational amplifier has a positive input terminal coupled to a first reference voltage, a negative input terminal coupled to a common supply node, and an output terminal. The capacitor is coupled between the common supply node and the output terminal of the operational amplifier. The source resistor is coupled between a supply voltage and the common supply node. The stabilization circuit is coupled between the common supply node and a ground voltage. The stabilization circuit stabilizes a voltage level of the common supply node when the voltage level of the common supply node is below a second reference voltage. The common supply node is configured to drive external circuits with the supply voltage as power supply of the external circuits.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 20, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 9521485
    Abstract: A voltage supply circuit included in an audio signal processing device includes a control unit for controlling a signal output from a terminal equipment; a power supply unit for outputting voltage to an earphone device according to a control signal of the control unit; and a variable circuit unit connected to the power supply unit to convert the voltage output from the power supply unit and transmit the converted voltage to the earphone device.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: December 13, 2016
    Assignee: WISOL CO., LTD.
    Inventor: Ahn Kook Lee
  • Patent number: 9484809
    Abstract: Provided herein are apparatus and methods for low voltage high power supply rejection ratio (PSRR) systems. A charge pump converts a supply voltage to a larger charge pump voltage and provides the charge pump voltage to a circuit subsystem. The charge pump voltage is regulated to a state dependent reference. In the steady state the charge pump voltage is regulated with respect to an output voltage of the circuit subsystem; in this way PSRR of the circuit subsystem is enhanced.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 1, 2016
    Inventor: Brian Harold Floyd