Stabilized (e.g., Compensated, Regulated, Maintained, Etc.) Patents (Class 327/538)
  • Patent number: 10312912
    Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 4, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher Michael Graves
  • Patent number: 10270333
    Abstract: A power supply system includes a control module for generating a control signal; a first charging pump module, coupled to the control module, for generating an adjustment charging value according to the control signal, and outputting a charging voltage according to the adjustment charging value and a conduction voltage source; an amplifying module, coupled to the first charging pump module, for utilizing the charging voltage to generate an amplifying voltage; and a load module, coupled to the amplifying module, for processing a dynamic charging operation according to the amplifying voltage.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 23, 2019
    Assignee: Sitronix Technology Corp.
    Inventor: Min-Nan Liao
  • Patent number: 10268228
    Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 23, 2019
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 10200042
    Abstract: Provided is an IO interface level shift circuit, comprising: an intermediate level generation circuit (11) and a level shift circuit (12). The intermediate level generation circuit is configured to provide an intermediate level Vdd_io of an IO interface. The level shift circuit is configured to convert an external logical signal into a signal in an internal power domain of a chip according to the intermediate level Vdd_io of the IO interface. Also provided are an IO interface level shift method and a storage medium. The interface level shift circuit enables level shift on an external IO signal at any level in a voltage withstanding domain of a device without adding a power domain suitable for an external IO level in the circuit.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: February 5, 2019
    Assignee: Sanechips Technology Co. Ltd.
    Inventor: Hailiang Cui
  • Patent number: 10186969
    Abstract: There is to provide a semiconductor device capable of activating a circuit quickly, operating with a lower power consumption in a steady state, and coping with the dispersion of the elements. The semiconductor device includes an amplifier coupled to a power voltage, to output a voltage based on a reference voltage and a voltage of a negative feedback node, to an output node; and a voltage divider coupled to the output node, to output the divided voltage to the negative feedback node. The voltage divider includes first and second voltage dividing paths with different resistance, a first switching circuit coupled to the first and the second voltage dividing paths, in a dividing ratio adjustable way, and a second switching circuit for controlling the first and the second voltage dividing paths.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 22, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Kohei Hashimoto
  • Patent number: 10185337
    Abstract: A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: January 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sungmin Ock, Wenjing Yin, Xuhao Huang
  • Patent number: 10180453
    Abstract: Methods and systems for sourcing and/or sinking current from power supplies of differing voltage levels. A driving circuit may, for example, receive power from first and second power supplies, where the first power supply provides current to the driving circuit at a first voltage level and the second power supply provides current to the driving circuit at a second voltage level, and where the first voltage is greater than the second voltage. As a result, the first power supply allows the driving circuit to provide current over a wide voltage range, and the second power supply allows the driving circuit to provide current at lower voltages with less power consumption.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 15, 2019
    Assignee: Analog Test Engines
    Inventor: Jeffrey Allen King
  • Patent number: 10156882
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 10152107
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 10126768
    Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carmelo Burgio, Mauro Giacomini
  • Patent number: 10116303
    Abstract: A power circuit includes a power source for providing electrical power and two driving transistors being disposed in parallel and receiving electrical power from the power source. Each of the two driving transistors includes a gate terminal, a source connection, and a kelvin source connection. The power circuit also includes a control voltage source having a first terminal and a second terminal. The control voltage source provides a control signal to the two driving transistors for determining driving currents through the two driving transistors. The first terminal is connected to the gate terminals of the two driving transistors, and the second terminal is connected to the kelvin source connections of the two driving transistors. The kelvin source connections of the two driving transistors are inductively coupled.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 30, 2018
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Yincan Mao, Chi-Ming Wang, Zichen Miao, Khai Ngo
  • Patent number: 10079514
    Abstract: In a non-contact power supply system, an electric power receiving device with suppressed heat generation is provided. The electric power receiving device is configured with a resonance circuit which includes a resonance capacity and a resonance coil acting as a receiving antenna, and receives electric power in a non-contact manner using resonant coupling of the resonance circuit. When receiving electric power, the electric power receiving device monitors the reception electric power received by the resonance circuit and controls the resonance frequency of the resonance circuit so as to keep the reception electric power from exceeding a target electric power level (PTGT). Accordingly, even when an electric power larger than the electric power required by the electric power receiving device is transmitted from the transmitting side, the electric power receiving device operates not to receive the electric power greater than the target electric power level.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 18, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiko Sone
  • Patent number: 10061341
    Abstract: This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 28, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Dieter Draxelmayr
  • Patent number: 10031164
    Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Takada, Nobuya Koike, Akihiro Nakahara, Makoto Tanaka
  • Patent number: 9954422
    Abstract: An integrated gate driver for motor control includes a first diode coupled to an upper rail and providing a voltage on a first connector and a power amplifier coupled between the first connector and a second connector that can be coupled to a source of a high-side power transistor. The power amplifier receives a control signal and provides an output signal to a second pin for driving a gate of the high-side power transistor. A first integrated capacitor is coupled between the first and second connector and an integrated charge pump is coupled to supply a current to the first connector. The charge pump includes a second integrated capacitor having a terminal coupled to a high frequency oscillator and a terminal coupled through a second diode to the first connector and a third diode coupled between the second connector and a point between the second capacitor and the second diode.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 24, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Miroslav Oljaca, Ajinder Singh, Sanjay Pithadia
  • Patent number: 9953608
    Abstract: The present invention relates to a driving circuit of a display panel. A plurality of driving units produce a reference driving voltage according to a gamma voltage of a gamma circuit, respectively. A plurality of digital-to-analog converting circuits receive the reference driving voltages output by the plurality of driving units, and select one of the plurality of reference driving voltage as a data driving voltage according to pixel data, respectively. The plurality of digital-to-analog converting circuits transmit the plurality of data driving voltages to the display panel for displaying images. A voltage boost circuit is used for producing a first supply voltage and providing the first supply voltage to the plurality of digital-to-analog converting circuits. At least a voltage boost unit is used for producing a second supply voltage and providing the second supply voltage to the plurality of driving units.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 24, 2018
    Assignee: Sitronix Technology Corp.
    Inventors: Min-Nan Liao, Chih-Ping Su
  • Patent number: 9923455
    Abstract: A current control circuit includes a current transformer that detects a primary current, a sensor gain switch that selectively connects the primary current to one of a first gain amplifier and a second gain amplifier to provide a current sensing output, a controller gain switch that selectively connects the current sensing output to one of a first controller amplifier and a second controller amplifier, and a controller that controls switching of the sensor gain switch and the controller gain switch.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: March 20, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Bing Gong, Jahangir Afsharian
  • Patent number: 9909931
    Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 6, 2018
    Assignee: SK HYNIX INC.
    Inventors: Kyu Tae Park, Marco Passerini
  • Patent number: 9898992
    Abstract: The present invention relates to an area-saving driving circuit for a display panel, which comprises a plurality of digital-to-analog converting circuits convert input data, respectively, and produce a pixel signal. A plurality of driving units are coupled to the plurality of digital-to-analog converting circuits, respectively. They produce a driving signal according to the pixel signal and transmit the driving signal to the display panel for displaying. A plurality of voltage booster units are coupled to the plurality of driving units, respectively, and produce a supply voltage according to a control signal. Then the supply voltage is provided to the plurality of driving units. Thereby, by providing the supply voltage to the plurality of driving units of the display panel by means of the plurality of voltage booster units, the area of the external storage capacitor is reduced. Alternative, the external storage capacitor can be even not required.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: February 20, 2018
    Assignee: Sitronix Technology Corp.
    Inventor: Min-Nan Liao
  • Patent number: 9874886
    Abstract: An integrated circuit may include a reference voltage generating circuit for generating a reference voltage. The reference voltage generating circuit may include a digital operation circuit and a digital-to-analog converter. The digital operation circuit is configured to adjust a reference voltage to temperature code relationship using a coefficient that adjusts a relative relationship between the reference voltage and the temperature code, and separate code that adjusts an absolute relationship between the reference voltage and the temperature code, wherein the temperature code reflects a temperature at the integrated circuit. The digital-to-analog converter is configured to generate the reference voltage based on an output from the digital operation circuit.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-cheol Kim
  • Patent number: 9853533
    Abstract: A circuit arrangement including a first branch, a second branch and a switching feedback structure is provided. The switching feedback structure may be coupled to the first branch and to the second branch. The switching feedback structure may be configured to adjust a current in the second branch to track a current in the first branch.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Adriano Sambucco
  • Patent number: 9817427
    Abstract: A voltage mirror circuit, having an input node and an output node provides substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. The voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 14, 2017
    Assignee: Dialog Semiconductor GmbH
    Inventor: Slawomir Malinowski
  • Patent number: 9740219
    Abstract: A semiconductor device including an input terminal to which a power source, for which the time until a voltage equal or greater than a predetermined voltage value is output fluctuates according to an external environment, is connected, a power source section to which the input terminal supplies power from the power source, a power source supply terminal that supplies power to a driven semiconductor device, a switch that controls a connection between the power source section and the power source supply terminal, and a voltage regulator to which the input terminal supplies power from the power source, and that supplies a voltage to the power source supply terminal is provided.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: August 22, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Shigeru Nagatomo
  • Patent number: 9728272
    Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 8, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Miyanishi, Yuichiro Ishii, Yoshisato Yokoyama
  • Patent number: 9681524
    Abstract: A power supply includes a first component arrangement providing a first current output for initializing control circuitry, and a second component arrangement providing a second current output to the control circuitry when the control circuitry initialization is complete, and a method of operating a power supply includes connecting a first component arrangement of the power supply to provide control circuitry with a first current for initializing operations within a predetermined time period, and connecting a second component arrangement of the supply to provide the control circuitry with a second current when initializing operations are complete.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: June 13, 2017
    Assignee: GE LIGHTING SOLUTIONS, LLC
    Inventors: Carre Denise Scheidegger, Gang Yao
  • Patent number: 9634613
    Abstract: A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 25, 2017
    Assignee: Raytheon Company
    Inventors: Edward A. Watters, Christopher M. Laighton, John P. Bettencourt
  • Patent number: 9588541
    Abstract: The embodiments described herein relate to an improved regulator circuit technique having a dual-loop configuration with a current regulation loop to provide the transient response and a voltage regulation loop to provide accurate DC voltage regulation. The current regulation loop comprises a pass transistor, a current sensing transistor, a current summation circuit, and a series of current mirrors to provide a fast load transient response current. The voltage regulation loop includes an output voltage feedback network, an error amplifier, a compensation capacitor, and the current sensing transistor and is configured to provide accurate DC offset regulation to diminish output voltage errors introduced by the transient load currents.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ngai Yeung Ho, Hua Guan
  • Patent number: 9590609
    Abstract: A gate-driver device for operating a field-effect-transistor (FET) includes a pull-down-block and a pull-up-block resistant to or protected from short circuits of the gate drive signal output by the device. The pull-down-block is operable to drive a gate of a FET to a low-voltage. The pull-up-block includes a resistive-pull-up operable to an ON-state and an OFF-state to switchably couple the gate to the high-voltage via an upper-resistive-element, and a current-pull-up arranged in parallel with the resistive-pull-up. The current-pull-up is operable to an ON-state and an OFF-state to control a current-source applied to the gate. When the pull-up-block drives the gate to the high-voltage, the resistive-pull-up and the current-pull-up operates from the OFF-state to the ON-state. A turn-on-interval after the resistive-pull-up operates from the OFF-state to the ON-state the resistive-pull-up operates to the OFF-state while the current-pull-up is maintained in the ON-state.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: March 7, 2017
    Assignee: Delphi Technologies Inc.
    Inventor: Osman Musa
  • Patent number: 9582021
    Abstract: A bandgap reference circuit with curvature compensation. The circuit includes a first current mirror that mirrors the current conducted by the bandgap reference. A difference between the gate-to-source voltages in the two legs provides a first mirrored current with non-linear temperature stability. This first mirrored current is again mirrored by a second current mirror in which the mirror transistors also have differing gate-to-source voltages, with the current from this second current mirror coupled to the bandgap reference to compensate for curvature in the CTAT current over temperature.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Matthias Arnold, Asif Qaiyum
  • Patent number: 9575498
    Abstract: The present disclosure includes circuits and methods for generating bleeding currents. In one embodiment, a pass transistor of a voltage regulator receives a voltage from a feedback circuit. A negative resistance circuit is coupled to a node to produce a bleeding current that turns on when needed and is otherwise off to save power. In one embodiment, the negative resistance circuit includes stacked current mirrors and a resistor. In another embodiment, the resistor has a first terminal that receives the voltage from the feedback circuit and a second terminal is coupled to a constant reference voltage that tracks the input voltage.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vincenzo Peluso, Bing Liu
  • Patent number: 9564886
    Abstract: A circuit and a method for controlling operation voltage, and a storage device are provided. The circuit includes: a voltage boost unit adapted for: if receiving a first signal, performing a voltage boost process; and if receiving a second signal, stopping the voltage boost process; a voltage division unit including a plurality of different voltage division coefficients, adapted for performing a voltage division process; a comparison unit adapted for: comparing the divided voltage with a reference voltage; if the divided voltage is low, outputting the first signal; and if not, outputting the second signal; a control unit adapted for performing a descending switching operation on the voltage division coefficients; and an output unit. The establishing speed of the operation voltage is effectively controlled, and an effect on device power consumption and performance caused by the threshold voltage and variations of the threshold voltage in the working process is eliminated.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 7, 2017
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Mingyong Huang, Jun Xiao
  • Patent number: 9525349
    Abstract: A power supply decoupling circuit includes an operational amplifier, a capacitor, a source resistor, and a stabilization circuit. The operational amplifier has a positive input terminal coupled to a first reference voltage, a negative input terminal coupled to a common supply node, and an output terminal. The capacitor is coupled between the common supply node and the output terminal of the operational amplifier. The source resistor is coupled between a supply voltage and the common supply node. The stabilization circuit is coupled between the common supply node and a ground voltage. The stabilization circuit stabilizes a voltage level of the common supply node when the voltage level of the common supply node is below a second reference voltage. The common supply node is configured to drive external circuits with the supply voltage as power supply of the external circuits.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 20, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 9521485
    Abstract: A voltage supply circuit included in an audio signal processing device includes a control unit for controlling a signal output from a terminal equipment; a power supply unit for outputting voltage to an earphone device according to a control signal of the control unit; and a variable circuit unit connected to the power supply unit to convert the voltage output from the power supply unit and transmit the converted voltage to the earphone device.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: December 13, 2016
    Assignee: WISOL CO., LTD.
    Inventor: Ahn Kook Lee
  • Patent number: 9484809
    Abstract: Provided herein are apparatus and methods for low voltage high power supply rejection ratio (PSRR) systems. A charge pump converts a supply voltage to a larger charge pump voltage and provides the charge pump voltage to a circuit subsystem. The charge pump voltage is regulated to a state dependent reference. In the steady state the charge pump voltage is regulated with respect to an output voltage of the circuit subsystem; in this way PSRR of the circuit subsystem is enhanced.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 1, 2016
    Inventor: Brian Harold Floyd
  • Patent number: 9442509
    Abstract: The electronic circuit with a self-calibrated PTAT current reference includes a PTAT current generator dependent on at least one integrated resistor for supplying a PTAT output current. It further includes a reference current generator dependent on at least one switched capacitor resistor, for supplying a reference current. The reference current and the PTAT output current are compared in a comparator so as to digitally adapt the programmable integrated resistor, or to digitally adapt the dimensional ratio of the transistors of a current mirror in the PTAT current generator, to supply the adapted PTAT output current.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: September 13, 2016
    Assignee: The Swatch Group Research and Development Ltd.
    Inventors: Arnaud Casagrande, Jean-Luc Arend
  • Patent number: 9417676
    Abstract: Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 16, 2016
    Assignee: INTEL CORPORATION
    Inventor: Anthony Kozaczuk
  • Patent number: 9404991
    Abstract: Magnetic field sensor including a magnetic field sensing circuit (2) comprising a reference magnetic field generator (8) and a magnetic field sensing cell (6), and a signal processing circuit (4) connected to the output of the magnetic field sensing cell and comprising a demodulator circuit and a gain correction feedback circuit (30, 28, 47) for correcting error fluctuations in the transfer characteristic of the magnetic field sensor. The sensor further comprises a reference current generator (3) configured to generate a reference current I ref, the reference current generator connected to the magnetic field sensing circuit (2) configured for generating the reference magnetic field B ref and to the gain correction feedback circuit configured for providing a reference signal (yref) to which an output signal of the demodulator circuit may be compared.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: August 2, 2016
    Assignee: LEM Intellectual Property SA
    Inventors: Giovanni Maria Anelli, Marc Pastre, Andrea Ajbl, Maher Kayal
  • Patent number: 9367114
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 9360879
    Abstract: A sense current generation apparatus constituted of: a main electronically controlled switch arranged to provide a current path for an input current; a sense electronically controlled switch arranged to generate a sense current; a voltage matching circuit arranged to adjust the voltage across the first and second terminals of the sense switch to equal the voltage across the first and second terminals of the main switch, within a predetermined maximum error voltage, such that the sense current is representative of the input current; and a voltage governor arranged to: receive an indication of the voltage across the first and second terminals of the main switch; and responsive to the received voltage indication, adjust the control voltage of the main switch such that the absolute value of the voltage across the terminals thereof is maintained above a predetermined voltage threshold greater than a boundary of the error range.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: June 7, 2016
    Assignee: Microsemi Corp.-Analog Mixed Signal Group, Ltd.
    Inventors: Gabi Levhar, Shimon Cohen
  • Patent number: 9356590
    Abstract: Systems and methods for production test trimming acceleration. In an illustrative, non-limiting embodiment, a method may include providing a first trim code to a reference circuit, where the reference circuit is configured to output a first signal in response to the first trim code; integrating a difference between the first signal and a target voltage value into a first integrated value; providing a second trim code to the reference circuit, where the reference circuit is configured to output a second signal in response to the second trim code; integrating a difference between the second signal and the target voltage value into a second integrated value; and adjusting at least one of the first or second trim codes in response to a comparison between the first and second integrated values.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 31, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edevaldo Pereira da Silva, Jr., Joe Chayachinda, Ricardo P. Coimbra, Marcelo de Paula Campos
  • Patent number: 9348347
    Abstract: In one embodiment, a regulator circuit for generating a regulated output voltage Vout has an error amplifier using a pair of bipolar transistors at its front end. The error amplifier compares the regulated output voltage to a reference voltage Vref. A precision current source draws a first current through a user-selected set resistance to generate the desired Vref. The regulator circuit controls a power stage to cause Vout to be equal to Vref. The base current into one of the bipolar transistors normally distorts the current through the set resistance. A base current compensation circuit is coupled to the current source to adjust the first current by a value equal to the base current to offset the base current. Therefore, Vref is not affected by the base current. The error amplifier may be in a linear regulator or a switching regulator. The compensation circuit may be used in other applications.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 24, 2016
    Assignee: Linear Technology Corporation
    Inventors: Robert Dobkin, Amitkumar Pravin Patel
  • Patent number: 9337827
    Abstract: An electronic circuit includes a reverse-conducting IGBT and a driver circuit. A first diode emitter efficiency of the reverse-conducting IGBT at a first off-state gate voltage differs from a second diode emitter efficiency at a second off-state gate voltage. A driver terminal of the driver circuit is electrically coupled to a gate terminal of the reverse-conducting IGBT. In a first state the driver circuit supplies an on-state gate voltage at the driver terminal. In a second state the driver circuit supplies the first off-state gate voltage, and in a third state the driver circuit supplies the second off-state gate voltage at the driver terminal. The reverse-conducting IGBT may be operated in different modes such that, for example, overall losses may be reduced.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventor: Dorothea Werber
  • Patent number: 9337772
    Abstract: An impulse generation circuit for a voltage controlled oscillator includes a zero-crossing detector configured to detect a zero-crossing time of an output signal of the voltage controlled oscillator. The zero-crossing time corresponds to a time that the output signal crosses from a first polarity to a second polarity. A delay circuit is configured to wait for a delay period based on the zero-crossing time and a voltage peak of the output signal. An impulse generation module is configured to generate an impulse subsequent to the delay period. An energy injector is configured to, in response to the impulse, connect a supply voltage to the output signal of the voltage controlled oscillator for a duration of the impulse.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: May 10, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9310824
    Abstract: The present document relates to voltage mirror circuits. A voltage mirror circuit, having an input node and an output node is configured to provide substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. An output gain transistor is wherein the voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 12, 2016
    Assignee: Dialog Semiconductor GmbH
    Inventor: Slawomir Malinowski
  • Patent number: 9304152
    Abstract: A current monitoring circuit is disclosed. The current monitoring circuit includes a main transistor arrangement for connection in series with a load and a set of one or more measurement branches in parallel with the main transistor arrangement. Each measurement branch comprises a series resistor and switch for controlling the connection of the branch into circuit. A gate controller is provided for controlling the switching of the main transistor arrangement and branch switches and a sense amplifier is included for measuring a current through the load based on the current flowing through the main transistor arrangement or a branch.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 5, 2016
    Assignee: NXP B.V.
    Inventor: Steven Aerts
  • Patent number: 9285821
    Abstract: A negative reference voltage generating circuit includes a clamp-type reference voltage circuit and a differential amplifier. The clamp-type reference voltage circuit is connected between a node of a first negative voltage which is equal to or lower than the ground voltage and a node of a second negative voltage which is lower than the first negative voltage, and is formed by connecting a first circuit and a second circuit in parallel. The differential amplifier amplifies the difference between a node voltage in the first circuit and a node voltage in the second circuit, and outputs a negative reference voltage.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 15, 2016
    Assignee: POWERCHIP TECHNOLOGY CORPORATION
    Inventors: Teruaki Maeda, Nobuhiko Ito
  • Patent number: 9264030
    Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: February 16, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Jun Zhu, Joseph Jun Cao, Ian Swarbrick
  • Patent number: 9249005
    Abstract: A filling device for filling containers with a food product is provided for use in the food industry. The filling device comprises at least one weighing device including at least one piezoelement configured to determine a filling amount of the food product.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 2, 2016
    Assignee: KRONES AG
    Inventor: Mathias Haeuslmann
  • Patent number: 9239652
    Abstract: A current conveyor circuit, which comprises: a first current transmitting route; a second current transmitting route, which has the same devices as the first current transmitting route; and at least one control circuit, to control the first current transmitting route and the second current transmitting route to enter a normal mode or a current splitting mode, wherein the first current transmitting route and the second current transmitting route are both enabled and can transmit current in the normal mode, where the first current transmitting route is enabled to transmit current but the second current transmitting route is disabled thus can not transmit current in the current splitting mode.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: January 19, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Harish Naga Venkata
  • Patent number: 9225241
    Abstract: A PWM DC-DC converter includes a switching unit converting an input voltage into an output voltage, a PID controller producing a PID control voltage, a comparator producing a switching control voltage, a switching controller which supplies a switching control signal to the switching unit, turns on a charge switch and at the same time turns off a discharge switch in an on-period of the switching control voltage, and turns off the charge switch and at the same time turns on the discharge switch in an off-period of the switching control voltage, and an operating point compensation unit which operates in response to an operating point compensation signal and supplies an initialization voltage of a uniform level to a node during a predetermined period for an initial drive.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 29, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seungyun Lee